1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdbool.h>
16 #include <stdint.h>
17 #include <stddef.h>
18 #include <stdlib.h>
19 #include "esp32/rom/ets_sys.h" // for ets_update_cpu_frequency
20 #include "esp32/rom/rtc.h"
21 #include "esp_rom_gpio.h"
22 #include "esp_efuse.h"
23 #include "soc/rtc.h"
24 #include "soc/rtc_periph.h"
25 #include "soc/sens_periph.h"
26 #include "soc/dport_reg.h"
27 #include "soc/efuse_periph.h"
28 #include "soc/apb_ctrl_reg.h"
29 #include "soc/gpio_struct.h"
30 #include "hal/cpu_hal.h"
31 #include "hal/gpio_ll.h"
32 #include "regi2c_ctrl.h"
33 #include "soc_log.h"
34 #include "sdkconfig.h"
35 #include "rtc_clk_common.h"
36
37 /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
38 #define RTC_FAST_CLK_FREQ_8M 8500000
39 #define RTC_SLOW_CLK_FREQ_150K 150000
40 #define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256)
41 #define RTC_SLOW_CLK_FREQ_32K 32768
42
43 /* BBPLL configuration values */
44 #define BBPLL_ENDIV5_VAL_320M 0x43
45 #define BBPLL_BBADC_DSMP_VAL_320M 0x84
46 #define BBPLL_ENDIV5_VAL_480M 0xc3
47 #define BBPLL_BBADC_DSMP_VAL_480M 0x74
48 #define BBPLL_IR_CAL_DELAY_VAL 0x18
49 #define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
50 #define BBPLL_OC_ENB_FCAL_VAL 0x9a
51 #define BBPLL_OC_ENB_VCON_VAL 0x00
52 #define BBPLL_BBADC_CAL_7_0_VAL 0x00
53
54 #define APLL_SDM_STOP_VAL_1 0x09
55 #define APLL_SDM_STOP_VAL_2_REV0 0x69
56 #define APLL_SDM_STOP_VAL_2_REV1 0x49
57
58 #define APLL_CAL_DELAY_1 0x0f
59 #define APLL_CAL_DELAY_2 0x3f
60 #define APLL_CAL_DELAY_3 0x1f
61
62 #define XTAL_32K_DAC_VAL 1
63 #define XTAL_32K_DRES_VAL 3
64 #define XTAL_32K_DBIAS_VAL 0
65
66 #define XTAL_32K_BOOTSTRAP_DAC_VAL 3
67 #define XTAL_32K_BOOTSTRAP_DRES_VAL 3
68 #define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
69 #define XTAL_32K_BOOTSTRAP_TIME_US 7
70
71 #define XTAL_32K_EXT_DAC_VAL 2
72 #define XTAL_32K_EXT_DRES_VAL 3
73 #define XTAL_32K_EXT_DBIAS_VAL 1
74
75 /* Delays for various clock sources to be enabled/switched.
76 * All values are in microseconds.
77 * TODO: some of these are excessive, and should be reduced.
78 */
79 #define DELAY_PLL_DBIAS_RAISE 3
80 #define DELAY_PLL_ENABLE_WITH_150K 80
81 #define DELAY_PLL_ENABLE_WITH_32K 160
82 #define DELAY_FAST_CLK_SWITCH 3
83 #define DELAY_SLOW_CLK_SWITCH 300
84 #define DELAY_8M_ENABLE 50
85
86 /* Core voltage needs to be increased in two cases:
87 * 1. running at 240 MHz
88 * 2. running with 80MHz Flash frequency
89 *
90 * There is a record in efuse which indicates the proper voltage for these two cases.
91 */
92 #define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
93 #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
94 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
95 #else
96 #define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
97 #endif
98 #define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
99 #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
100 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
101
102 #define RTC_PLL_FREQ_320M 320
103 #define RTC_PLL_FREQ_480M 480
104 #define DELAY_RTC_CLK_SWITCH 5
105
106 static void rtc_clk_cpu_freq_to_8m(void);
107 static void rtc_clk_bbpll_disable(void);
108 static void rtc_clk_bbpll_enable(void);
109 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz);
110
111 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
112 static uint32_t s_cur_pll_freq;
113
114 static const char* TAG = "rtc_clk";
115
rtc_clk_32k_enable_common(int dac,int dres,int dbias)116 static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
117 {
118 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
119 RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | RTC_IO_X32N_RUE |
120 RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE | RTC_IO_X32P_FUN_IE);
121 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
122 /* Set the parameters of xtal
123 dac --> current
124 dres --> resistance
125 dbias --> bais voltage
126 */
127 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, dac);
128 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, dres);
129 REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
130
131 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
132 uint8_t chip_ver = esp_efuse_get_chip_ver();
133 // version0 and version1 need provide additional current to external XTAL.
134 if(chip_ver == 0 || chip_ver == 1) {
135 /* TOUCH sensor can provide additional current to external XTAL.
136 In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
137 SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
138 /* Tie PAD Touch8 to VDD
139 NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead*/
140 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
141 /* Set the current used to compensate TOUCH PAD8 */
142 SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 4, RTC_IO_TOUCH_PAD8_DAC_S);
143 /* Power up TOUCH8
144 So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)*/
145 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
146 }
147 #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
148 uint8_t chip_ver = esp_efuse_get_chip_ver();
149 if(chip_ver == 0 || chip_ver == 1) {
150 /* TOUCH sensor can provide additional current to external XTAL.
151 In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
152 SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
153 SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_DCUR, 3, RTC_IO_TOUCH_DCUR_S);
154 CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FSM_EN_M);
155 /* Tie PAD Touch8 to VDD
156 NOTE: TOUCH8 and TOUCH9 register settings are reversed except for DAC, so we set RTC_IO_TOUCH_PAD9_REG here instead
157 */
158 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_TIE_OPT_M);
159 /* Set the current used to compensate TOUCH PAD8 */
160 SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_DAC, 1, RTC_IO_TOUCH_PAD8_DAC_S);
161 /* Power up TOUCH8
162 So the Touch DAC start to drive some current from VDD to TOUCH8(which is also XTAL-N)
163 */
164 SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
165 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_START_M);
166 }
167 #endif
168 /* Power up external xtal */
169 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
170 }
171
rtc_clk_32k_enable(bool enable)172 void rtc_clk_32k_enable(bool enable)
173 {
174 if (enable) {
175 rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
176 } else {
177 /* Disable X32N and X32P pad drive external xtal */
178 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K_M);
179 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
180
181 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
182 uint8_t chip_ver = esp_efuse_get_chip_ver();
183 if(chip_ver == 0 || chip_ver == 1) {
184 /* Power down TOUCH */
185 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
186 }
187 #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
188 uint8_t chip_ver = esp_efuse_get_chip_ver();
189 if(chip_ver == 0 || chip_ver == 1) {
190 /* Power down TOUCH */
191 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
192 SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_DCUR, 0, RTC_IO_TOUCH_DCUR_S);
193 CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
194 SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FSM_EN_M);
195 }
196 #endif
197 }
198 }
199
rtc_clk_32k_enable_external(void)200 void rtc_clk_32k_enable_external(void)
201 {
202 rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
203 }
204
205 /* Helping external 32kHz crystal to start up.
206 * External crystal connected to outputs GPIO32 GPIO33.
207 * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
208 */
rtc_clk_32k_bootstrap(uint32_t cycle)209 void rtc_clk_32k_bootstrap(uint32_t cycle)
210 {
211 if (cycle){
212 const uint32_t pin_32 = 32;
213 const uint32_t pin_33 = 33;
214
215 esp_rom_gpio_pad_select_gpio(pin_32);
216 esp_rom_gpio_pad_select_gpio(pin_33);
217 gpio_ll_output_enable(&GPIO, pin_32);
218 gpio_ll_output_enable(&GPIO, pin_33);
219 gpio_ll_set_level(&GPIO, pin_32, 1);
220 gpio_ll_set_level(&GPIO, pin_33, 0);
221
222 const uint32_t delay_us = (1000000 / RTC_SLOW_CLK_FREQ_32K / 2);
223 while(cycle){
224 gpio_ll_set_level(&GPIO, pin_32, 1);
225 gpio_ll_set_level(&GPIO, pin_33, 0);
226 esp_rom_delay_us(delay_us);
227 gpio_ll_set_level(&GPIO, pin_33, 1);
228 gpio_ll_set_level(&GPIO, pin_32, 0);
229 esp_rom_delay_us(delay_us);
230 cycle--;
231 }
232 // disable pins
233 gpio_ll_output_disable(&GPIO, pin_32);
234 gpio_ll_output_disable(&GPIO, pin_33);
235 }
236
237 CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
238 SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
239 esp_rom_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
240
241 rtc_clk_32k_enable_common(XTAL_32K_BOOTSTRAP_DAC_VAL,
242 XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
243 }
244
rtc_clk_32k_enabled(void)245 bool rtc_clk_32k_enabled(void)
246 {
247 return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
248 }
249
rtc_clk_8m_enable(bool clk_8m_en,bool d256_en)250 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
251 {
252 if (clk_8m_en) {
253 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
254 /* no need to wait once enabled by software */
255 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
256 if (d256_en) {
257 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
258 } else {
259 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
260 }
261 esp_rom_delay_us(DELAY_8M_ENABLE);
262 } else {
263 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
264 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
265 }
266 }
267
rtc_clk_8m_enabled(void)268 bool rtc_clk_8m_enabled(void)
269 {
270 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
271 }
272
rtc_clk_8md256_enabled(void)273 bool rtc_clk_8md256_enabled(void)
274 {
275 return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
276 }
277
rtc_clk_apll_enable(bool enable,uint32_t sdm0,uint32_t sdm1,uint32_t sdm2,uint32_t o_div)278 void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
279 {
280 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
281 REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
282
283 if (!enable &&
284 REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) {
285 REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
286 } else {
287 REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
288 }
289
290 if (enable) {
291 uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
292 uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
293 if (is_rev0) {
294 sdm0 = 0;
295 sdm1 = 0;
296 sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
297 }
298 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
299 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
300 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
301 REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
302 REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, sdm_stop_val_2);
303 REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
304
305 /* calibration */
306 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
307 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
308 REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
309
310 /* wait for calibration end */
311 while (!(REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END))) {
312 /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
313 esp_rom_delay_us(1);
314 }
315 }
316 }
317
rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)318 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
319 {
320 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
321
322 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
323 (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
324
325 esp_rom_delay_us(DELAY_SLOW_CLK_SWITCH);
326 }
327
rtc_clk_slow_freq_get(void)328 rtc_slow_freq_t rtc_clk_slow_freq_get(void)
329 {
330 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
331 }
332
rtc_clk_slow_freq_get_hz(void)333 uint32_t rtc_clk_slow_freq_get_hz(void)
334 {
335 switch(rtc_clk_slow_freq_get()) {
336 case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
337 case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
338 case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
339 }
340 return 0;
341 }
342
rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)343 void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
344 {
345 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
346 esp_rom_delay_us(DELAY_FAST_CLK_SWITCH);
347 }
348
rtc_clk_fast_freq_get(void)349 rtc_fast_freq_t rtc_clk_fast_freq_get(void)
350 {
351 return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
352 }
353
rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq,int pll_freq)354 void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
355 {
356 uint8_t div_ref;
357 uint8_t div7_0;
358 uint8_t div10_8;
359 uint8_t lref;
360 uint8_t dcur;
361 uint8_t bw;
362
363 if (pll_freq == RTC_PLL_FREQ_320M) {
364 /* Raise the voltage, if needed */
365 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
366 /* Configure 320M PLL */
367 switch (xtal_freq) {
368 case RTC_XTAL_FREQ_40M:
369 div_ref = 0;
370 div7_0 = 32;
371 div10_8 = 0;
372 lref = 0;
373 dcur = 6;
374 bw = 3;
375 break;
376 case RTC_XTAL_FREQ_26M:
377 div_ref = 12;
378 div7_0 = 224;
379 div10_8 = 4;
380 lref = 1;
381 dcur = 0;
382 bw = 1;
383 break;
384 case RTC_XTAL_FREQ_24M:
385 div_ref = 11;
386 div7_0 = 224;
387 div10_8 = 4;
388 lref = 1;
389 dcur = 0;
390 bw = 1;
391 break;
392 default:
393 div_ref = 12;
394 div7_0 = 224;
395 div10_8 = 4;
396 lref = 0;
397 dcur = 0;
398 bw = 0;
399 break;
400 }
401 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
402 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M);
403 } else {
404 /* Raise the voltage */
405 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
406 esp_rom_delay_us(DELAY_PLL_DBIAS_RAISE);
407 /* Configure 480M PLL */
408 switch (xtal_freq) {
409 case RTC_XTAL_FREQ_40M:
410 div_ref = 0;
411 div7_0 = 28;
412 div10_8 = 0;
413 lref = 0;
414 dcur = 6;
415 bw = 3;
416 break;
417 case RTC_XTAL_FREQ_26M:
418 div_ref = 12;
419 div7_0 = 144;
420 div10_8 = 4;
421 lref = 1;
422 dcur = 0;
423 bw = 1;
424 break;
425 case RTC_XTAL_FREQ_24M:
426 div_ref = 11;
427 div7_0 = 144;
428 div10_8 = 4;
429 lref = 1;
430 dcur = 0;
431 bw = 1;
432 break;
433 default:
434 div_ref = 12;
435 div7_0 = 224;
436 div10_8 = 4;
437 lref = 0;
438 dcur = 0;
439 bw = 0;
440 break;
441 }
442 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
443 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
444 }
445
446 uint8_t i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
447 uint8_t i2c_bbpll_div_7_0 = div7_0;
448 uint8_t i2c_bbpll_dcur = (bw << 6) | dcur;
449 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
450 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
451 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
452 uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
453 DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
454 esp_rom_delay_us(delay_pll_en);
455 s_cur_pll_freq = pll_freq;
456 }
457
458 /**
459 * Switch to XTAL frequency. Does not disable the PLL.
460 */
rtc_clk_cpu_freq_to_xtal(int freq,int div)461 void rtc_clk_cpu_freq_to_xtal(int freq, int div)
462 {
463 ets_update_cpu_frequency(freq);
464 /* set divider from XTAL to APB clock */
465 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
466 /* adjust ref_tick */
467 REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, freq * MHZ / REF_CLK_FREQ - 1);
468 /* switch clock source */
469 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
470 rtc_clk_apb_freq_update(freq * MHZ);
471 /* lower the voltage */
472 if (freq <= 2) {
473 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
474 } else {
475 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
476 }
477 }
478
rtc_clk_cpu_freq_to_8m(void)479 static void rtc_clk_cpu_freq_to_8m(void)
480 {
481 ets_update_cpu_frequency(8);
482 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
483 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
484 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
485 rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
486 }
487
rtc_clk_bbpll_disable(void)488 static void rtc_clk_bbpll_disable(void)
489 {
490 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
491 RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
492 RTC_CNTL_BBPLL_I2C_FORCE_PD);
493 s_cur_pll_freq = 0;
494
495 /* is APLL under force power down? */
496 uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
497 if (apll_fpd) {
498 /* then also power down the internal I2C bus */
499 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
500 }
501 }
502
rtc_clk_bbpll_enable(void)503 static void rtc_clk_bbpll_enable(void)
504 {
505 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
506 RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
507 RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
508
509 /* reset BBPLL configuration */
510 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
511 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
512 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
513 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
514 REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
515 }
516
517 /**
518 * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
519 * PLL must already be enabled.
520 * @param cpu_freq new CPU frequency
521 */
rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)522 static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
523 {
524 int dbias = DIG_DBIAS_80M_160M;
525 int per_conf = DPORT_CPUPERIOD_SEL_80;
526 if (cpu_freq_mhz == 80) {
527 /* nothing to do */
528 } else if (cpu_freq_mhz == 160) {
529 per_conf = DPORT_CPUPERIOD_SEL_160;
530 } else if (cpu_freq_mhz == 240) {
531 dbias = DIG_DBIAS_240M;
532 per_conf = DPORT_CPUPERIOD_SEL_240;
533 } else {
534 SOC_LOGE(TAG, "invalid frequency");
535 abort();
536 }
537 DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
538 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
539 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
540 rtc_clk_apb_freq_update(80 * MHZ);
541 ets_update_cpu_frequency(cpu_freq_mhz);
542 rtc_clk_wait_for_slow_cycle();
543 }
544
rtc_clk_cpu_freq_set_xtal(void)545 void rtc_clk_cpu_freq_set_xtal(void)
546 {
547 int freq_mhz = (int) rtc_clk_xtal_freq_get();
548
549 rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
550 rtc_clk_wait_for_slow_cycle();
551 rtc_clk_bbpll_disable();
552 }
553
rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq,rtc_cpu_freq_config_t * out_config)554 void rtc_clk_cpu_freq_to_config(rtc_cpu_freq_t cpu_freq, rtc_cpu_freq_config_t* out_config)
555 {
556 uint32_t source_freq_mhz;
557 rtc_cpu_freq_src_t source;
558 uint32_t freq_mhz;
559 uint32_t divider;
560
561 switch (cpu_freq) {
562 case RTC_CPU_FREQ_XTAL:
563 case RTC_CPU_FREQ_2M:
564 source_freq_mhz = rtc_clk_xtal_freq_get();
565 source = RTC_CPU_FREQ_SRC_XTAL;
566 if (cpu_freq == RTC_CPU_FREQ_2M) {
567 freq_mhz = 2;
568 divider = source_freq_mhz / 2;
569 } else {
570 freq_mhz = source_freq_mhz;
571 divider = 1;
572 }
573 break;
574 case RTC_CPU_FREQ_80M:
575 source = RTC_CPU_FREQ_SRC_PLL;
576 source_freq_mhz = RTC_PLL_FREQ_320M;
577 divider = 4;
578 freq_mhz = 80;
579 break;
580 case RTC_CPU_FREQ_160M:
581 source = RTC_CPU_FREQ_SRC_PLL;
582 source_freq_mhz = RTC_PLL_FREQ_320M;
583 divider = 2;
584 freq_mhz = 160;
585 break;
586 case RTC_CPU_FREQ_240M:
587 source = RTC_CPU_FREQ_SRC_PLL;
588 source_freq_mhz = RTC_PLL_FREQ_480M;
589 divider = 2;
590 freq_mhz = 240;
591 break;
592 default:
593 SOC_LOGE(TAG, "invalid rtc_cpu_freq_t value");
594 abort();
595 }
596
597 *out_config = (rtc_cpu_freq_config_t) {
598 .source = source,
599 .source_freq_mhz = source_freq_mhz,
600 .div = divider,
601 .freq_mhz = freq_mhz
602 };
603 }
604
rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz,rtc_cpu_freq_config_t * out_config)605 bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t* out_config)
606 {
607 uint32_t source_freq_mhz;
608 rtc_cpu_freq_src_t source;
609 uint32_t divider;
610 uint32_t real_freq_mhz;
611
612 uint32_t xtal_freq = (uint32_t) rtc_clk_xtal_freq_get();
613 if (freq_mhz <= xtal_freq) {
614 divider = xtal_freq / freq_mhz;
615 real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
616 if (real_freq_mhz != freq_mhz) {
617 // no suitable divider
618 return false;
619 }
620
621 source_freq_mhz = xtal_freq;
622 source = RTC_CPU_FREQ_SRC_XTAL;
623 } else if (freq_mhz == 80) {
624 real_freq_mhz = freq_mhz;
625 source = RTC_CPU_FREQ_SRC_PLL;
626 source_freq_mhz = RTC_PLL_FREQ_320M;
627 divider = 4;
628 } else if (freq_mhz == 160) {
629 real_freq_mhz = freq_mhz;
630 source = RTC_CPU_FREQ_SRC_PLL;
631 source_freq_mhz = RTC_PLL_FREQ_320M;
632 divider = 2;
633 } else if (freq_mhz == 240) {
634 real_freq_mhz = freq_mhz;
635 source = RTC_CPU_FREQ_SRC_PLL;
636 source_freq_mhz = RTC_PLL_FREQ_480M;
637 divider = 2;
638 } else {
639 // unsupported frequency
640 return false;
641 }
642 *out_config = (rtc_cpu_freq_config_t) {
643 .source = source,
644 .div = divider,
645 .source_freq_mhz = source_freq_mhz,
646 .freq_mhz = real_freq_mhz
647 };
648 return true;
649 }
650
rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t * config)651 void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t* config)
652 {
653 rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
654 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
655 if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) {
656 rtc_clk_cpu_freq_to_xtal(xtal_freq, 1);
657 rtc_clk_wait_for_slow_cycle();
658 }
659 if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
660 rtc_clk_bbpll_disable();
661 }
662 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
663 if (config->div > 1) {
664 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
665 }
666 } else if (config->source == RTC_CPU_FREQ_SRC_PLL) {
667 rtc_clk_bbpll_enable();
668 rtc_clk_wait_for_slow_cycle();
669 rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
670 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
671 } else if (config->source == RTC_CPU_FREQ_SRC_8M) {
672 rtc_clk_cpu_freq_to_8m();
673 }
674 }
675
rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t * out_config)676 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t* out_config)
677 {
678 rtc_cpu_freq_src_t source;
679 uint32_t source_freq_mhz;
680 uint32_t div;
681 uint32_t freq_mhz;
682 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
683 switch (soc_clk_sel) {
684 case RTC_CNTL_SOC_CLK_SEL_XTL: {
685 source = RTC_CPU_FREQ_SRC_XTAL;
686 div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT) + 1;
687 source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
688 freq_mhz = source_freq_mhz / div;
689 }
690 break;
691 case RTC_CNTL_SOC_CLK_SEL_PLL: {
692 source = RTC_CPU_FREQ_SRC_PLL;
693 uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
694 if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
695 source_freq_mhz = RTC_PLL_FREQ_320M;
696 div = 4;
697 freq_mhz = 80;
698 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
699 source_freq_mhz = RTC_PLL_FREQ_320M;
700 div = 2;
701 freq_mhz = 160;
702 } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
703 source_freq_mhz = RTC_PLL_FREQ_480M;
704 div = 2;
705 freq_mhz = 240;
706 } else {
707 SOC_LOGE(TAG, "unsupported frequency configuration");
708 abort();
709 }
710 break;
711 }
712 case RTC_CNTL_SOC_CLK_SEL_8M:
713 source = RTC_CPU_FREQ_SRC_8M;
714 source_freq_mhz = 8;
715 div = 1;
716 freq_mhz = source_freq_mhz;
717 break;
718 case RTC_CNTL_SOC_CLK_SEL_APLL:
719 default:
720 SOC_LOGE(TAG, "unsupported frequency configuration");
721 abort();
722 }
723 *out_config = (rtc_cpu_freq_config_t) {
724 .source = source,
725 .source_freq_mhz = source_freq_mhz,
726 .div = div,
727 .freq_mhz = freq_mhz
728 };
729 }
730
rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t * config)731 void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
732 {
733 if (config->source == RTC_CPU_FREQ_SRC_XTAL) {
734 rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
735 } else if (config->source == RTC_CPU_FREQ_SRC_PLL &&
736 s_cur_pll_freq == config->source_freq_mhz) {
737 rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
738 } else {
739 /* fallback */
740 rtc_clk_cpu_freq_set_config(config);
741 }
742 }
743
rtc_clk_xtal_freq_get(void)744 rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
745 {
746 /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
747 uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
748 if (!clk_val_is_valid(xtal_freq_reg)) {
749 return RTC_XTAL_FREQ_AUTO;
750 }
751 return reg_val_to_clk_val(xtal_freq_reg & ~RTC_DISABLE_ROM_LOG);
752 }
753
rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)754 void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
755 {
756 uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
757 if (reg == RTC_DISABLE_ROM_LOG) {
758 xtal_freq |= 1;
759 }
760 WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
761 }
762
rtc_clk_apb_freq_update(uint32_t apb_freq)763 void rtc_clk_apb_freq_update(uint32_t apb_freq)
764 {
765 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
766 }
767
rtc_clk_apb_freq_get(void)768 uint32_t rtc_clk_apb_freq_get(void)
769 {
770 uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
771 // round to the nearest MHz
772 freq_hz += MHZ / 2;
773 uint32_t remainder = freq_hz % MHZ;
774 return freq_hz - remainder;
775 }
776
rtc_dig_clk8m_enable(void)777 void rtc_dig_clk8m_enable(void)
778 {
779 SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
780 esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
781 }
782
rtc_dig_clk8m_disable(void)783 void rtc_dig_clk8m_disable(void)
784 {
785 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
786 esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
787 }
788
789 /* Name used in libphy.a:phy_chip_v7.o
790 * TODO: update the library to use rtc_clk_xtal_freq_get
791 */
792 rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
793