1 // Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdbool.h>
16 #include <stdint.h>
17 #include <stddef.h>
18 #include <stdlib.h>
19 #include "esp32/rom/rtc.h"
20 #include "esp_rom_uart.h"
21 #include "soc/rtc.h"
22 #include "soc/rtc_periph.h"
23 #include "soc/sens_periph.h"
24 #include "soc/efuse_periph.h"
25 #include "soc/apb_ctrl_reg.h"
26 #include "hal/cpu_hal.h"
27 #include "regi2c_ctrl.h"
28 #include "soc_log.h"
29 #include "sdkconfig.h"
30 #include "rtc_clk_common.h"
31
32 /* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
33 * 10 cycles will take approximately 300 microseconds.
34 */
35 #define XTAL_FREQ_EST_CYCLES 10
36
37 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void);
38
39 static const char* TAG = "rtc_clk_init";
40
rtc_clk_init(rtc_clk_config_t cfg)41 void rtc_clk_init(rtc_clk_config_t cfg)
42 {
43 rtc_cpu_freq_config_t old_config, new_config;
44
45 /* If we get a TG WDT system reset while running at 240MHz,
46 * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
47 * APB and CPU frequencies after reset. This will cause issues with XTAL
48 * frequency estimation, so we switch to XTAL frequency first.
49 *
50 * Ideally we would only do this if RTC_CNTL_SOC_CLK_SEL == PLL and
51 * PLL is configured for 480M, but it takes less time to switch to 40M and
52 * run the following code than querying the PLL does.
53 */
54 if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) {
55 /* We don't know actual XTAL frequency yet, assume 40MHz.
56 * REF_TICK divider will be corrected below, once XTAL frequency is
57 * determined.
58 */
59 rtc_clk_cpu_freq_to_xtal(40, 1);
60 }
61
62 /* Set tuning parameters for 8M and 150k clocks.
63 * Note: this doesn't attempt to set the clocks to precise frequencies.
64 * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
65 * - SCK_DCAP value controls tuning of 150k clock.
66 * The higher the value of DCAP is, the lower is the frequency.
67 * - CK8M_DFREQ value controls tuning of 8M clock.
68 * CLK_8M_DFREQ constant gives the best temperature characteristics.
69 */
70 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
71 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
72
73 /* Configure 8M clock division */
74 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div);
75
76 /* Enable the internal bus used to configure PLLs */
77 SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
78 CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
79
80 /* Estimate XTAL frequency */
81 rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
82 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
83 if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
84 /* XTAL frequency has already been set, use existing value */
85 xtal_freq = rtc_clk_xtal_freq_get();
86 } else {
87 /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
88 xtal_freq = rtc_clk_xtal_freq_estimate();
89 if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
90 SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
91 xtal_freq = RTC_XTAL_FREQ_26M;
92 }
93 }
94 } else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
95 /* Exact frequency was set in sdkconfig, but still warn if autodetected
96 * frequency is different. If autodetection failed, worst case we get a
97 * bit of garbage output.
98 */
99
100 rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
101 if (est_xtal_freq != xtal_freq) {
102 SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
103 xtal_freq, est_xtal_freq);
104 }
105 }
106 esp_rom_uart_tx_wait_idle(0);
107 rtc_clk_xtal_freq_update(xtal_freq);
108 rtc_clk_apb_freq_update(xtal_freq * MHZ);
109
110 /* Set CPU frequency */
111
112 rtc_clk_cpu_freq_get_config(&old_config);
113 uint32_t freq_before = old_config.freq_mhz;
114
115 bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
116 if (!res) {
117 SOC_LOGE(TAG, "invalid CPU frequency value");
118 abort();
119 }
120 rtc_clk_cpu_freq_set_config(&new_config);
121
122 /* Configure REF_TICK */
123 REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq - 1);
124 REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */
125
126 /* Re-calculate the ccount to make time calculation correct. */
127 cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
128
129 /* Slow & fast clocks setup */
130 if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
131 rtc_clk_32k_enable(true);
132 }
133 if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
134 bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
135 rtc_clk_8m_enable(true, need_8md256);
136 }
137 rtc_clk_fast_freq_set(cfg.fast_freq);
138 rtc_clk_slow_freq_set(cfg.slow_freq);
139 }
140
rtc_clk_xtal_freq_estimate(void)141 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
142 {
143 /* Enable 8M/256 clock if needed */
144 const bool clk_8m_enabled = rtc_clk_8m_enabled();
145 const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
146 if (!clk_8md256_enabled) {
147 rtc_clk_8m_enable(true, true);
148 }
149
150 uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
151 /* cal_val contains period of 8M/256 clock in XTAL clock cycles
152 * (shifted by RTC_CLK_CAL_FRACT bits).
153 * Xtal frequency will be (cal_val * 8M / 256) / 2^19
154 */
155 uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT;
156 /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
157 */
158 switch (freq_mhz) {
159 case 21 ... 31:
160 return RTC_XTAL_FREQ_26M;
161 case 32 ... 33:
162 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
163 return RTC_XTAL_FREQ_26M;
164 case 34 ... 35:
165 SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
166 return RTC_XTAL_FREQ_40M;
167 case 36 ... 45:
168 return RTC_XTAL_FREQ_40M;
169 default:
170 SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
171 return RTC_XTAL_FREQ_AUTO;
172 }
173 /* Restore 8M and 8md256 clocks to original state */
174 rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
175 }
176