1 /*
2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #ifndef ETH_MAC_H
17 #define ETH_MAC_H
18
19 #include <asm/platform.h>
20 #include <hdf_netbuf.h>
21 #include <los_base.h>
22 #include <osal_timer.h>
23
24 #include "eth_phy.h"
25 #include "eth_drv.h"
26 #include "hieth_pri.h"
27
28 #ifdef __cplusplus
29 #if __cplusplus
30 extern "C" {
31 #endif /* __cplusplus */
32 #endif /* __cplusplus */
33
34 #define U_MAC_PORTSEL 0x0200
35 #define D_MAC_PORTSEL 0x2200
36 #define U_MAC_RO_STAT 0x0204
37 #define D_MAC_RO_STAT 0x2204
38 #define U_MAC_PORTSET 0x0208
39 #define D_MAC_PORTSET 0x2208
40 #define U_MAC_STAT_CHANGE 0x020C
41 #define D_MAC_STAT_CHANGE 0x220C
42 #define U_MAC_SET 0x0210
43 #define D_MAC_SET 0x2210
44 #define U_MAC_RX_IPGCTRL 0x0214
45 #define D_MAC_RX_IPGCTRL 0x2214
46 #define U_MAC_TX_IPGCTRL 0x0218
47 #define D_MAC_TX_IPGCTRL 0x2218
48
49 /* bits of UD_MAC_PORTSET and UD_MAC_RO_STAT */
50 #define BITS_MACSTAT MK_BITS(0, 3)
51
52 /* bits of U_MAC_PORTSEL and D_MAC_PORTSEL */
53 #define BITS_NEGMODE MK_BITS(0, 1)
54 #define BITS_MII_MODE MK_BITS(1, 1)
55
56 /* bits of U_MAC_TX_IPGCTRL and D_MAC_TX_IPGCTRL */
57 #define BITS_PRE_CNT_LIMIT MK_BITS(23, 3)
58 #define BITS_IPG MK_BITS(16, 7)
59 #define BITS_FC_INTER MK_BITS(0, 16)
60
61 #define HIETH_SPD_100M (1 << 2)
62 #define HIETH_LINKED (1 << 1)
63 #define HIETH_DUP_FULL 1
64
65 #define HIETH_MAX_RCV_LEN 1535
66 #define BITS_LEN_MAX MK_BITS(0, 10)
67
68 #define HIETH_NEGMODE_CPUSET 1
69 #define HIETH_NEGMODE_AUTO 0
70
71 #define HIETH_MII_MODE 0
72 #define HIETH_RMII_MODE 1
73
74 struct PbufInfo {
75 struct pbuf_dma_info *dmaInfo[MAX_ETH_DRV_SG];
76 uint32_t sgLen;
77 NetBuf *buf;
78 };
79
80 void NetDmaCacheInv(void *addr, uint32_t size);
81 void NetDmaCacheClean(void *addr, uint32_t size);
82
83 typedef struct EthRamCfg {
84 struct TxPktInfo *txqInfo;
85 NetBuf **rxNetbuf;
86 struct PbufInfo *pbufInfo;
87 } EthRamCfg;
88
89 typedef struct HiethPriv {
90 uint32_t vector;
91 uint8_t *enaddr;
92 uint32_t base; /* Base address of device */
93 EthPhyAccess *phy;
94 uint32_t totalLen;
95 uint8_t iterator;
96 volatile EthRamCfg *ram;
97 uint32_t rxFeed;
98 uint32_t rxRelease;
99 #ifdef INT_IO_ETH_INT_SUPPORT_REQUIRED
100 interrupt intr;
101 handle_t intr_handle;
102 #endif
103 OsalTimer phyTimer;
104 OsalTimer monitorTimer;
105 uint32_t index; /* dev id */
106 } HiethPriv;
107
IsMulticastEtherAddr(const uint8_t * addr)108 static inline int32_t IsMulticastEtherAddr(const uint8_t *addr)
109 {
110 return 0x01 & addr[0];
111 }
112
113 void EthHisiRandomAddr(uint8_t *addr, int32_t len);
114
115 int32_t HiethSetMacLeadcodeCntLimit(struct HiethNetdevLocal *ld, int32_t cnt);
116 int32_t HiethSetMacTransIntervalBits(struct HiethNetdevLocal *ld, int32_t nbits);
117 int32_t HiethSetMacFcInterval(struct HiethNetdevLocal *ld, int32_t para);
118
119 int32_t HiethSetLinkStat(struct HiethNetdevLocal *ld, unsigned long mode);
120 int32_t HiethGetLinkStat(struct HiethNetdevLocal *ld);
121
122 int32_t HiethSetNegMode(struct HiethNetdevLocal *ld, int32_t mode);
123 int32_t HiethGetNegmode(struct HiethNetdevLocal *ld);
124
125 int32_t HiethSetMiiMode(struct HiethNetdevLocal *ld, int32_t mode);
126 void HiethSetRcvLenMax(struct HiethNetdevLocal *ld, int32_t cnt);
127
128 #ifdef __cplusplus
129 #if __cplusplus
130 }
131 #endif /* __cplusplus */
132 #endif /* __cplusplus */
133
134 #endif /* ETH_MAC_H */
135