1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 /*-------------------------------------------------------------------------------
16
17 For type defines and data structure defines
18
19 --------------------------------------------------------------------------------*/
20
21
22 #ifndef __DRV_TYPES_H__
23 #define __DRV_TYPES_H__
24
25 #include <drv_conf.h>
26 #include <basic_types.h>
27 #include <osdep_service.h>
28 #include <rtw_byteorder.h>
29 #include <wlan_bssdef.h>
30 #include <wifi.h>
31 #include <ieee80211.h>
32 #ifdef CONFIG_ARP_KEEP_ALIVE
33 #include <net/neighbour.h>
34 #include <net/arp.h>
35 #endif
36
37 #ifdef PLATFORM_OS_XP
38 #include <drv_types_xp.h>
39 #endif
40
41 #ifdef PLATFORM_OS_CE
42 #include <drv_types_ce.h>
43 #endif
44
45 #ifdef PLATFORM_LINUX
46 #include <drv_types_linux.h>
47 #endif
48
49 enum _NIC_VERSION {
50
51 RTL8711_NIC,
52 RTL8712_NIC,
53 RTL8713_NIC,
54 RTL8716_NIC
55
56 };
57
58 typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER;
59
60 #include <rtw_debug.h>
61 #include <cmn_info/rtw_sta_info.h>
62 #include <rtw_rf.h>
63 #include "../core/rtw_chplan.h"
64
65 #ifdef CONFIG_80211N_HT
66 #include <rtw_ht.h>
67 #endif
68
69 #ifdef CONFIG_80211AC_VHT
70 #include <rtw_vht.h>
71 #endif
72
73 #include <rtw_cmd.h>
74 #include <cmd_osdep.h>
75 #include <rtw_security.h>
76 #include <rtw_xmit.h>
77 #include <xmit_osdep.h>
78 #include <rtw_recv.h>
79 #include <rtw_rm.h>
80
81 #ifdef CONFIG_BEAMFORMING
82 #include <rtw_beamforming.h>
83 #endif
84
85 #include <recv_osdep.h>
86 #include <rtw_efuse.h>
87 #include <rtw_sreset.h>
88 #include <hal_intf.h>
89 #include <hal_com.h>
90 #include<hal_com_h2c.h>
91 #include <hal_com_led.h>
92 #include "../hal/hal_dm.h"
93 #include <rtw_qos.h>
94 #include <rtw_pwrctrl.h>
95 #ifdef CONFIG_RTW_80211R
96 #include <rtw_ft.h>
97 #endif
98 #if defined(CONFIG_RTW_WNM) || defined(CONFIG_RTW_80211K)
99 #include <rtw_wnm.h>
100 #endif
101 #ifdef CONFIG_RTW_MBO
102 #include <rtw_mbo.h>
103 #endif
104 #include <rtw_mlme.h>
105 #include <mlme_osdep.h>
106 #include <rtw_io.h>
107 #include <rtw_ioctl.h>
108 #include <rtw_ioctl_set.h>
109 #include <rtw_ioctl_query.h>
110 #include <osdep_intf.h>
111 #include <rtw_eeprom.h>
112 #include <sta_info.h>
113 #include <rtw_event.h>
114 #include <rtw_mlme_ext.h>
115 #include <rtw_mi.h>
116 #include <rtw_ap.h>
117 #ifdef CONFIG_RTW_WDS
118 #include "../core/wds/rtw_wds.h"
119 #endif
120 #ifdef CONFIG_RTW_MESH
121 #include "../core/mesh/rtw_mesh.h"
122 #endif
123 #ifdef CONFIG_WIFI_MONITOR
124 #include "../core/monitor/rtw_radiotap.h"
125 #endif
126 #include <rtw_efuse.h>
127 #include <rtw_version.h>
128 #include <rtw_odm.h>
129
130 #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
131 #include <rtw_mem.h>
132 #endif
133
134 #include <rtw_p2p.h>
135
136 #ifdef CONFIG_TDLS
137 #include <rtw_tdls.h>
138 #endif /* CONFIG_TDLS */
139
140 #ifdef CONFIG_WAPI_SUPPORT
141 #include <rtw_wapi.h>
142 #endif /* CONFIG_WAPI_SUPPORT */
143
144 #ifdef CONFIG_MP_INCLUDED
145 #include <rtw_mp.h>
146 #endif /* CONFIG_MP_INCLUDED */
147
148 #ifdef CONFIG_BR_EXT
149 #include <rtw_br_ext.h>
150 #endif /* CONFIG_BR_EXT */
151
152 #ifdef CONFIG_IOL
153 #include <rtw_iol.h>
154 #endif /* CONFIG_IOL */
155
156 #include <ip.h>
157 #include <if_ether.h>
158 #include <ethernet.h>
159 #include <circ_buf.h>
160
161 #include <rtw_android.h>
162
163 #include <rtw_btcoex_wifionly.h>
164 #include <rtw_btcoex.h>
165
166 #ifdef CONFIG_MCC_MODE
167 #include <rtw_mcc.h>
168 #endif /*CONFIG_MCC_MODE */
169
170 #ifdef CONFIG_RTW_REPEATER_SON
171 #include <rtw_rson.h>
172 #endif /*CONFIG_RTW_REPEATER_SON */
173
174 #include <rtw_roch.h>
175
176 #define SPEC_DEV_ID_NONE BIT(0)
177 #define SPEC_DEV_ID_DISABLE_HT BIT(1)
178 #define SPEC_DEV_ID_ENABLE_PS BIT(2)
179 #define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3)
180 #define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4)
181 #define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5)
182
183 struct specific_device_id {
184
185 u32 flags;
186
187 u16 idVendor;
188 u16 idProduct;
189
190 };
191
192 struct registry_priv {
193 u8 chip_version;
194 u8 rfintfs;
195 u8 lbkmode;
196 u8 hci;
197 NDIS_802_11_SSID ssid;
198 u8 network_mode; /* infra, ad-hoc, auto */
199 u8 channel;/* ad-hoc support requirement */
200 u8 wireless_mode;/* A, B, G, auto */
201 u8 scan_mode;/* active, passive */
202 u8 radio_enable;
203 u8 preamble;/* long, short, auto */
204 u8 vrtl_carrier_sense;/* Enable, Disable, Auto */
205 u8 vcs_type;/* RTS/CTS, CTS-to-self */
206 u16 rts_thresh;
207 u16 frag_thresh;
208 u8 adhoc_tx_pwr;
209 u8 soft_ap;
210 u8 power_mgnt;
211 u8 ips_mode;
212 u8 lps_level;
213 #ifdef CONFIG_LPS_1T1R
214 u8 lps_1t1r;
215 #endif
216 u8 lps_chk_by_tp;
217 #ifdef CONFIG_WOWLAN
218 u8 wow_power_mgnt;
219 u8 wow_lps_level;
220 #ifdef CONFIG_LPS_1T1R
221 u8 wow_lps_1t1r;
222 #endif
223 #endif /* CONFIG_WOWLAN */
224 u8 smart_ps;
225 #ifdef CONFIG_WMMPS_STA
226 u8 wmm_smart_ps;
227 #endif /* CONFIG_WMMPS_STA */
228 u8 usb_rxagg_mode;
229 u8 dynamic_agg_enable;
230 u8 long_retry_lmt;
231 u8 short_retry_lmt;
232 u16 busy_thresh;
233 u16 max_bss_cnt;
234 u8 ack_policy;
235 u8 mp_mode;
236 #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR)
237 u8 mp_customer_str;
238 #endif
239 u8 mp_dm;
240 u8 software_encrypt;
241 u8 software_decrypt;
242 #ifdef CONFIG_TX_EARLY_MODE
243 u8 early_mode;
244 #endif
245 #ifdef CONFIG_NARROWBAND_SUPPORTING
246 u8 rtw_nb_config;
247 #endif
248 u8 acm_method;
249 /* WMM */
250 u8 wmm_enable;
251 #ifdef CONFIG_WMMPS_STA
252 /* uapsd (unscheduled automatic power-save delivery) = a kind of wmmps */
253 u8 uapsd_max_sp_len;
254 /* BIT0: AC_VO UAPSD, BIT1: AC_VI UAPSD, BIT2: AC_BK UAPSD, BIT3: AC_BE UAPSD */
255 u8 uapsd_ac_enable;
256 #endif /* CONFIG_WMMPS_STA */
257
258 WLAN_BSSID_EX dev_network;
259
260 #if CONFIG_TX_AC_LIFETIME
261 u8 tx_aclt_flags;
262 struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
263 #endif
264
265 u8 tx_bw_mode;
266 #ifdef CONFIG_AP_MODE
267 u8 bmc_tx_rate;
268 #if CONFIG_RTW_AP_DATA_BMC_TO_UC
269 u8 ap_src_b2u_flags;
270 u8 ap_fwd_b2u_flags;
271 #endif
272 #endif
273
274 #ifdef CONFIG_RTW_MESH
275 #if CONFIG_RTW_MESH_DATA_BMC_TO_UC
276 u8 msrc_b2u_flags;
277 u8 mfwd_b2u_flags;
278 #endif
279 #endif
280
281 #ifdef CONFIG_80211N_HT
282 u8 ht_enable;
283 /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */
284 /* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */
285 /* 0x21 means enable 2.4G 40MHz & 5G 80MHz */
286 u8 bw_mode;
287 u8 ampdu_enable;/* for tx */
288 u8 rx_stbc;
289 u8 rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */
290 u8 tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */
291 u8 tx_quick_addba_req;
292 u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */
293 /* Short GI support Bit Map */
294 /* BIT0 - 20MHz, 1: support, 0: non-support */
295 /* BIT1 - 40MHz, 1: support, 0: non-support */
296 /* BIT2 - 80MHz, 1: support, 0: non-support */
297 /* BIT3 - 160MHz, 1: support, 0: non-support */
298 u8 short_gi;
299 /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */
300 u8 ldpc_cap;
301 /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */
302 u8 stbc_cap;
303 #if defined(CONFIG_RTW_TX_NPATH_EN)
304 u8 tx_npath;
305 #endif
306 #if defined(CONFIG_RTW_PATH_DIV)
307 u8 path_div;
308 #endif
309 /*
310 * BIT0: Enable VHT SU Beamformer
311 * BIT1: Enable VHT SU Beamformee
312 * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer
313 * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee
314 * BIT4: Enable HT Beamformer
315 * BIT5: Enable HT Beamformee
316 */
317 u8 beamform_cap;
318 u8 beamformer_rf_num;
319 u8 beamformee_rf_num;
320 #endif /* CONFIG_80211N_HT */
321
322 #ifdef CONFIG_80211AC_VHT
323 u8 vht_enable; /* 0:disable, 1:enable, 2:auto */
324 u8 vht_24g_enable; /* 0:disable, 1:enable */
325 u8 ampdu_factor;
326 u8 vht_rx_mcs_map[2];
327 #endif /* CONFIG_80211AC_VHT */
328
329 u8 low_power ;
330
331 u8 wifi_spec;/* !turbo_mode */
332
333 u8 trx_path_bmp; /* [7:4]TX path bmp, [0:3]RX path bmp, 0: not specified */
334 u8 tx_path_lmt; /* limit of TX path number, 0: not specified */
335 u8 rx_path_lmt; /* limit of TX path number, 0: not specified */
336 u8 tx_nss;
337 u8 rx_nss;
338
339 #ifdef CONFIG_ACTIVE_TPC_REPORT
340 u8 active_tpc_report;
341 #endif
342
343 #ifdef CONFIG_REGD_SRC_FROM_OS
344 enum regd_src_t regd_src;
345 #endif
346 char alpha2[2];
347 u8 channel_plan;
348 u8 excl_chs[MAX_CHANNEL_NUM_2G_5G];
349 #if CONFIG_IEEE80211_BAND_6GHZ
350 u8 channel_plan_6g;
351 u8 excl_chs_6g[MAX_CHANNEL_NUM_6G];
352 #endif
353 u8 full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/
354
355 #ifdef CONFIG_BT_COEXIST
356 u8 btcoex;
357 u8 bt_iso;
358 u8 bt_sco;
359 u8 bt_ampdu;
360 u8 ant_num;
361 u8 single_ant_path;
362 #endif
363 BOOLEAN bAcceptAddbaReq;
364
365 u8 antdiv_cfg;
366 u8 antdiv_type;
367 u8 drv_ant_band_switch;
368
369 u8 switch_usb_mode;
370
371 u8 usbss_enable;/* 0:disable,1:enable */
372 u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */
373 u8 hwpwrp_detect;/* 0:disable,1:enable */
374
375 u8 hw_wps_pbc;/* 0:disable,1:enable */
376
377 #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE
378 char adaptor_info_caching_file_path[PATH_LENGTH_MAX];
379 #endif
380
381 #ifdef CONFIG_LAYER2_ROAMING
382 u8 max_roaming_times; /* the max number driver will try to roaming */
383 #endif
384
385 #ifdef CONFIG_IOL
386 u8 fw_iol; /* enable iol without other concern */
387 #endif
388
389 #ifdef CONFIG_80211D
390 u8 country_ie_slave_en_role;
391 u8 country_ie_slave_en_ifbmp;
392 #endif
393
394 u8 ifname[16];
395 u8 if2name[16];
396 #if defined(CONFIG_PLATFORM_ANDROID) && (CONFIG_IFACE_NUMBER > 2)
397 u8 if3name[16];
398 #endif
399 u8 notch_filter;
400
401 /* for pll reference clock selction */
402 u8 pll_ref_clk_sel;
403
404 /* define for tx power adjust */
405 #if CONFIG_TXPWR_LIMIT
406 u8 RegEnableTxPowerLimit;
407 #endif
408 u8 RegEnableTxPowerByRate;
409
410 u8 target_tx_pwr_valid;
411 s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM];
412 #if CONFIG_IEEE80211_BAND_5GHZ
413 s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1];
414 #endif
415 s16 antenna_gain;
416
417 u8 tsf_update_pause_factor;
418 u8 tsf_update_restore_factor;
419
420 s8 TxBBSwing_2G;
421 s8 TxBBSwing_5G;
422 u8 AmplifierType_2G;
423 u8 AmplifierType_5G;
424 u8 bEn_RFE;
425 u8 RFE_Type;
426 u8 PowerTracking_Type;
427 u8 GLNA_Type;
428 u8 check_fw_ps;
429 u8 RegPwrTrimEnable;
430
431 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
432 u8 load_phy_file;
433 u8 RegDecryptCustomFile;
434 #endif
435 #ifdef CONFIG_CONCURRENT_MODE
436 u8 virtual_iface_num;
437 #ifdef CONFIG_P2P
438 u8 sel_p2p_iface;
439 #endif
440 #endif
441 u8 qos_opt_enable;
442
443 u8 hiq_filter;
444 u8 adaptivity_en;
445 u8 adaptivity_mode;
446 s8 adaptivity_th_l2h_ini;
447 s8 adaptivity_th_edcca_hl_diff;
448
449 u8 boffefusemask;
450 BOOLEAN bFileMaskEfuse;
451 BOOLEAN bBTFileMaskEfuse;
452 #ifdef CONFIG_RTW_ACS
453 u8 acs_auto_scan;
454 u8 acs_mode;
455 #endif
456
457 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
458 u8 nm_mode;
459 #endif
460 u32 reg_rxgain_offset_2g;
461 u32 reg_rxgain_offset_5gl;
462 u32 reg_rxgain_offset_5gm;
463 u32 reg_rxgain_offset_5gh;
464
465 #ifdef CONFIG_DFS_MASTER
466 u8 dfs_region_domain;
467 #endif
468 u8 amsdu_mode;
469 #ifdef CONFIG_MCC_MODE
470 u8 en_mcc;
471 u32 rtw_mcc_single_tx_cri;
472 u32 rtw_mcc_ap_bw20_target_tx_tp;
473 u32 rtw_mcc_ap_bw40_target_tx_tp;
474 u32 rtw_mcc_ap_bw80_target_tx_tp;
475 u32 rtw_mcc_sta_bw20_target_tx_tp;
476 u32 rtw_mcc_sta_bw40_target_tx_tp;
477 u32 rtw_mcc_sta_bw80_target_tx_tp;
478 s8 rtw_mcc_policy_table_idx;
479 u8 rtw_mcc_duration;
480 u8 rtw_mcc_enable_runtime_duration;
481 u8 rtw_mcc_phydm_offload;
482 #endif /* CONFIG_MCC_MODE */
483
484 #ifdef CONFIG_RTW_NAPI
485 u8 en_napi;
486 #ifdef CONFIG_RTW_NAPI_DYNAMIC
487 u32 napi_threshold; /* unit: Mbps */
488 #endif /* CONFIG_RTW_NAPI_DYNAMIC */
489 #ifdef CONFIG_RTW_GRO
490 u8 en_gro;
491 #endif /* CONFIG_RTW_GRO */
492 #endif /* CONFIG_RTW_NAPI */
493
494 #ifdef CONFIG_WOWLAN
495 u8 wowlan_enable;
496 u8 wakeup_event;
497 u8 suspend_type;
498 #endif
499
500 u8 recvbuf_nr;
501
502 #ifdef CONFIG_SUPPORT_TRX_SHARED
503 u8 trx_share_mode;
504 #endif
505 u8 check_hw_status;
506 u8 wowlan_sta_mix_mode;
507
508 #ifdef CONFIG_PCI_HCI
509 u32 pci_aspm_config;
510 u32 pci_dynamic_aspm_linkctrl;
511 #endif
512
513 u8 iqk_fw_offload;
514 u8 ch_switch_offload;
515
516 #ifdef CONFIG_TDLS
517 u8 en_tdls;
518 #endif
519
520 #ifdef CONFIG_ADVANCE_OTA
521 u8 adv_ota;
522 #endif
523
524 #ifdef CONFIG_FW_OFFLOAD_PARAM_INIT
525 u8 fw_param_init;
526 #endif
527 #ifdef CONFIG_DYNAMIC_SOML
528 u8 dyn_soml_en;
529 u8 dyn_soml_train_num;
530 u8 dyn_soml_interval;
531 u8 dyn_soml_period;
532 u8 dyn_soml_delay;
533 #endif
534 #ifdef CONFIG_FW_HANDLE_TXBCN
535 u8 fw_tbtt_rpt;
536 #endif
537
538 #ifdef DBG_LA_MODE
539 u8 la_mode_en;
540 #endif
541 u32 phydm_ability;
542 u32 halrf_ability;
543 #ifdef CONFIG_TDMADIG
544 u8 tdmadig_en;
545 u8 tdmadig_mode;
546 u8 tdmadig_dynamic;
547 #endif/*CONFIG_TDMADIG*/
548 u8 en_dyn_rrsr;
549 u32 set_rrsr_value;
550 #ifdef CONFIG_RTW_MESH
551 u8 peer_alive_based_preq;
552 #endif
553
554 #ifdef RTW_BUSY_DENY_SCAN
555 /*
556 * scan_interval_thr means scan interval threshold which is used to
557 * judge if user is in scan page or not.
558 * If scan interval < scan_interval_thr we guess user is in scan page,
559 * and driver won't deny any scan request at that time.
560 * Its default value comes from compiler flag
561 * BUSY_TRAFFIC_SCAN_DENY_PERIOD, and unit is ms.
562 */
563 u32 scan_interval_thr;
564 #endif
565
566 #ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
567 u8 rtw_8822c_xcap_overwrite;
568 #endif
569 #ifdef CONFIG_RTW_MULTI_AP
570 u8 unassoc_sta_mode_of_stype[UNASOC_STA_SRC_NUM];
571 u16 max_unassoc_sta_cnt;
572 #endif
573 #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_AP_MODE)
574 u8 ap_csa_cnt;
575 #endif
576 u8 nbi_en;
577 };
578
579 /* For registry parameters */
580 #define RGTRY_OFT(field) ((u32)FIELD_OFFSET(struct registry_priv, field))
581 #define RGTRY_SZ(field) sizeof(((struct registry_priv *) 0)->field)
582
583 #define GetRegAmplifierType2G(_Adapter) (_Adapter->registrypriv.AmplifierType_2G)
584 #define GetRegAmplifierType5G(_Adapter) (_Adapter->registrypriv.AmplifierType_5G)
585
586 #define GetRegTxBBSwing_2G(_Adapter) (_Adapter->registrypriv.TxBBSwing_2G)
587 #define GetRegTxBBSwing_5G(_Adapter) (_Adapter->registrypriv.TxBBSwing_5G)
588
589 #define GetRegbENRFEType(_Adapter) (_Adapter->registrypriv.bEn_RFE)
590 #define GetRegRFEType(_Adapter) (_Adapter->registrypriv.RFE_Type)
591 #define GetRegGLNAType(_Adapter) (_Adapter->registrypriv.GLNA_Type)
592 #define GetRegPowerTrackingType(_Adapter) (_Adapter->registrypriv.PowerTracking_Type)
593
594 #define WOWLAN_IS_STA_MIX_MODE(_Adapter) (_Adapter->registrypriv.wowlan_sta_mix_mode)
595 #define BSSID_OFT(field) ((u32)FIELD_OFFSET(WLAN_BSSID_EX, field))
596 #define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field)
597
598 #define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F)
599 #define BW_MODE_5G(bw_mode) ((bw_mode) >> 4)
600 #ifdef CONFIG_80211N_HT
601 #define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode)
602 #define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode)
603 #else
604 #define REGSTY_BW_2G(regsty) CHANNEL_WIDTH_20
605 #define REGSTY_BW_5G(regsty) CHANNEL_WIDTH_20
606 #endif
607 #define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw))
608 #define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw))
609
610 #ifdef CONFIG_80211AC_VHT
611 #define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0)
612 #define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2)
613 #define REGSTY_IS_11AC_24G_ENABLE(regsty) ((regsty)->vht_24g_enable != 0)
614 #else
615 #define REGSTY_IS_11AC_ENABLE(regsty) 0
616 #define REGSTY_IS_11AC_AUTO(regsty) 0
617 #define REGSTY_IS_11AC_24G_ENABLE(regsty) 0
618 #endif
619
620 #ifdef CONFIG_ACTIVE_TPC_REPORT
621 #define REGSTY_IS_ACTIVE_TPC_REPORT_CAPABLE(regsty) ((regsty)->active_tpc_report != 0)
622 #define REGSTY_IS_ACTIVE_TPC_REPORT_AUTO(regsty) ((regsty)->active_tpc_report == 2)
623 #else
624 #define REGSTY_IS_ACTIVE_TPC_REPORT_CAPABLE(regsty) 0
625 #define REGSTY_IS_ACTIVE_TPC_REPORT_AUTO(regsty) 0
626 #endif
627
628 #ifdef CONFIG_REGD_SRC_FROM_OS
629 #define REGSTY_REGD_SRC_FROM_OS(regsty) ((regsty)->regd_src == REGD_SRC_OS)
630 #else
631 #define REGSTY_REGD_SRC_FROM_OS(regsty) 0
632 #endif
633
634 typedef struct rtw_if_operations {
635 int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf,
636 size_t len, bool fixed);
637 int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf,
638 size_t len, bool fixed);
639 } RTW_IF_OPS, *PRTW_IF_OPS;
640
641 #ifdef CONFIG_SDIO_HCI
642 #include <drv_types_sdio.h>
643 #define INTF_DATA SDIO_DATA
644 #define INTF_OPS PRTW_IF_OPS
645 #elif defined(CONFIG_GSPI_HCI)
646 #include <drv_types_gspi.h>
647 #define INTF_DATA GSPI_DATA
648 #elif defined(CONFIG_PCI_HCI)
649 #include <drv_types_pci.h>
650 #endif
651
652 #define get_hw_port(adapter) (adapter->hw_port)
653
654 #ifdef CONFIG_CONCURRENT_MODE
655 #define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER)
656 #define is_vir_adapter(adapter) (adapter->adapter_type == VIRTUAL_ADAPTER)
657 #else
658 #define is_primary_adapter(adapter) (1)
659 #define is_vir_adapter(adapter) (0)
660 #endif
661 #define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0])
662 #define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums)
663 #define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id])
664
665 #define GetDefaultAdapter(padapter) padapter
666
667 enum _IFACE_ID {
668 IFACE_ID0, /*PRIMARY_ADAPTER*/
669 IFACE_ID1,
670 IFACE_ID2,
671 IFACE_ID3,
672 IFACE_ID4,
673 IFACE_ID5,
674 IFACE_ID6,
675 IFACE_ID7,
676 IFACE_ID_MAX,
677 };
678
679 #define VIF_START_ID 1
680
681 #ifdef CONFIG_DBG_COUNTER
682
683 struct rx_logs {
684 u32 intf_rx;
685 u32 intf_rx_err_recvframe;
686 u32 intf_rx_err_skb;
687 u32 intf_rx_report;
688 u32 core_rx;
689 u32 core_rx_pre;
690 u32 core_rx_pre_ver_err;
691 u32 core_rx_pre_mgmt;
692 u32 core_rx_pre_mgmt_err_80211w;
693 u32 core_rx_pre_mgmt_err;
694 u32 core_rx_pre_ctrl;
695 u32 core_rx_pre_ctrl_err;
696 u32 core_rx_pre_data;
697 u32 core_rx_pre_data_wapi_seq_err;
698 u32 core_rx_pre_data_wapi_key_err;
699 u32 core_rx_pre_data_handled;
700 u32 core_rx_pre_data_err;
701 u32 core_rx_pre_data_unknown;
702 u32 core_rx_pre_unknown;
703 u32 core_rx_enqueue;
704 u32 core_rx_dequeue;
705 u32 core_rx_post;
706 u32 core_rx_post_decrypt;
707 u32 core_rx_post_decrypt_wep;
708 u32 core_rx_post_decrypt_tkip;
709 u32 core_rx_post_decrypt_aes;
710 u32 core_rx_post_decrypt_wapi;
711 u32 core_rx_post_decrypt_gcmp;
712 u32 core_rx_post_decrypt_hw;
713 u32 core_rx_post_decrypt_unknown;
714 u32 core_rx_post_decrypt_err;
715 u32 core_rx_post_defrag_err;
716 u32 core_rx_post_portctrl_err;
717 u32 core_rx_post_indicate;
718 u32 core_rx_post_indicate_in_oder;
719 u32 core_rx_post_indicate_reoder;
720 u32 core_rx_post_indicate_err;
721 u32 os_indicate;
722 u32 os_indicate_ap_mcast;
723 u32 os_indicate_ap_forward;
724 u32 os_indicate_ap_self;
725 u32 os_indicate_err;
726 u32 os_netif_ok;
727 u32 os_netif_err;
728 };
729
730 struct tx_logs {
731 u32 os_tx;
732 u32 os_tx_err_up;
733 u32 os_tx_err_xmit;
734 u32 os_tx_m2u;
735 u32 os_tx_m2u_ignore_fw_linked;
736 u32 os_tx_m2u_ignore_self;
737 u32 os_tx_m2u_entry;
738 u32 os_tx_m2u_entry_err_xmit;
739 u32 os_tx_m2u_entry_err_skb;
740 u32 os_tx_m2u_stop;
741 u32 core_tx;
742 u32 core_tx_err_pxmitframe;
743 u32 core_tx_err_brtx;
744 u32 core_tx_upd_attrib;
745 u32 core_tx_upd_attrib_adhoc;
746 u32 core_tx_upd_attrib_sta;
747 u32 core_tx_upd_attrib_ap;
748 u32 core_tx_upd_attrib_unknown;
749 u32 core_tx_upd_attrib_dhcp;
750 u32 core_tx_upd_attrib_icmp;
751 u32 core_tx_upd_attrib_active;
752 u32 core_tx_upd_attrib_err_ucast_sta;
753 u32 core_tx_upd_attrib_err_ucast_ap_link;
754 u32 core_tx_upd_attrib_err_sta;
755 u32 core_tx_upd_attrib_err_link;
756 u32 core_tx_upd_attrib_err_sec;
757 u32 core_tx_ap_enqueue_warn_fwstate;
758 u32 core_tx_ap_enqueue_warn_sta;
759 u32 core_tx_ap_enqueue_warn_nosta;
760 u32 core_tx_ap_enqueue_warn_link;
761 u32 core_tx_ap_enqueue_warn_trigger;
762 u32 core_tx_ap_enqueue_mcast;
763 u32 core_tx_ap_enqueue_ucast;
764 u32 core_tx_ap_enqueue;
765 u32 intf_tx;
766 u32 intf_tx_pending_ac;
767 u32 intf_tx_pending_fw_under_survey;
768 u32 intf_tx_pending_fw_under_linking;
769 u32 intf_tx_pending_xmitbuf;
770 u32 intf_tx_enqueue;
771 u32 core_tx_enqueue;
772 u32 core_tx_enqueue_class;
773 u32 core_tx_enqueue_class_err_sta;
774 u32 core_tx_enqueue_class_err_nosta;
775 u32 core_tx_enqueue_class_err_fwlink;
776 u32 intf_tx_direct;
777 u32 intf_tx_direct_err_coalesce;
778 u32 intf_tx_dequeue;
779 u32 intf_tx_dequeue_err_coalesce;
780 u32 intf_tx_dump_xframe;
781 u32 intf_tx_dump_xframe_err_txdesc;
782 u32 intf_tx_dump_xframe_err_port;
783 };
784
785 struct int_logs {
786 u32 all;
787 u32 err;
788 u32 tbdok;
789 u32 tbder;
790 u32 bcnderr;
791 u32 bcndma;
792 u32 bcndma_e;
793 u32 rx;
794 u32 rx_rdu;
795 u32 rx_fovw;
796 u32 txfovw;
797 u32 mgntok;
798 u32 highdok;
799 u32 bkdok;
800 u32 bedok;
801 u32 vidok;
802 u32 vodok;
803 };
804
805 #endif /* CONFIG_DBG_COUNTER */
806
807 struct debug_priv {
808 u32 dbg_sdio_free_irq_error_cnt;
809 u32 dbg_sdio_alloc_irq_error_cnt;
810 u32 dbg_sdio_free_irq_cnt;
811 u32 dbg_sdio_alloc_irq_cnt;
812 u32 dbg_sdio_deinit_error_cnt;
813 u32 dbg_sdio_init_error_cnt;
814 u32 dbg_suspend_error_cnt;
815 u32 dbg_suspend_cnt;
816 u32 dbg_resume_cnt;
817 u32 dbg_resume_error_cnt;
818 u32 dbg_deinit_fail_cnt;
819 u32 dbg_carddisable_cnt;
820 u32 dbg_carddisable_error_cnt;
821 u32 dbg_ps_insuspend_cnt;
822 u32 dbg_dev_unload_inIPS_cnt;
823 u32 dbg_wow_leave_ps_fail_cnt;
824 u32 dbg_scan_pwr_state_cnt;
825 u32 dbg_downloadfw_pwr_state_cnt;
826 u32 dbg_fw_read_ps_state_fail_cnt;
827 u32 dbg_leave_ips_fail_cnt;
828 u32 dbg_leave_lps_fail_cnt;
829 u32 dbg_h2c_leave32k_fail_cnt;
830 u32 dbg_diswow_dload_fw_fail_cnt;
831 u32 dbg_enwow_dload_fw_fail_cnt;
832 u32 dbg_ips_drvopen_fail_cnt;
833 u32 dbg_poll_fail_cnt;
834 u32 dbg_rpwm_toogle_cnt;
835 u32 dbg_rpwm_timeout_fail_cnt;
836 u32 dbg_sreset_cnt;
837 u32 dbg_fw_mem_dl_error_cnt;
838 u64 dbg_rx_fifo_last_overflow;
839 u64 dbg_rx_fifo_curr_overflow;
840 u64 dbg_rx_fifo_diff_overflow;
841 };
842
843 struct rtw_traffic_statistics {
844 /* tx statistics */
845 u64 tx_bytes;
846 u64 tx_pkts;
847 u64 tx_drop;
848 u64 cur_tx_bytes;
849 u64 last_tx_bytes;
850 u32 cur_tx_tp; /* Tx throughput in Mbps. */
851
852 /* rx statistics */
853 u64 rx_bytes;
854 u64 rx_pkts;
855 u64 rx_drop;
856 u64 cur_rx_bytes;
857 u64 last_rx_bytes;
858 u32 cur_rx_tp; /* Rx throughput in Mbps. */
859 };
860
861 #define SEC_CAP_CHK_BMC BIT0
862 #define SEC_CAP_CHK_EXTRA_SEC BIT1 /* 256 bit */
863 #define SEC_CAP_CHK_WRITE_CAM_NEW_RULE BIT2
864
865 #define MACID_DROP BIT0
866 #define MACID_DROP_INDIRECT BIT1
867
868 #define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0
869
870 struct sec_cam_bmp {
871 u32 m0;
872 #if (SEC_CAM_ENT_NUM_SW_LIMIT > 32)
873 u32 m1;
874 #endif
875 #if (SEC_CAM_ENT_NUM_SW_LIMIT > 64)
876 u32 m2;
877 #endif
878 #if (SEC_CAM_ENT_NUM_SW_LIMIT > 96)
879 u32 m3;
880 #endif
881 };
882
883 struct cam_ctl_t {
884 _lock lock;
885
886 u8 sec_cap;
887 u32 flags;
888
889 u8 num;
890 struct sec_cam_bmp used;
891
892 _mutex sec_cam_access_mutex;
893 };
894
895 struct sec_cam_ent {
896 u16 ctrl;
897 u8 mac[ETH_ALEN];
898 u8 key[16];
899 };
900
901 #define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x"
902 #define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
903 ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \
904 ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15]
905
906 #define RTW_DEFAULT_MGMT_MACID 1
907
908 struct macid_bmp {
909 u32 m0;
910 #if (MACID_NUM_SW_LIMIT > 32)
911 u32 m1;
912 #endif
913 #if (MACID_NUM_SW_LIMIT > 64)
914 u32 m2;
915 #endif
916 #if (MACID_NUM_SW_LIMIT > 96)
917 u32 m3;
918 #endif
919 };
920
921 #ifdef CONFIG_CLIENT_PORT_CFG
922 struct clt_port_t{
923 _lock lock;
924 u8 bmp;
925 s8 num;
926 };
927 #define get_clt_num(adapter) (adapter_to_dvobj(adapter)->clt_port.num)
928 #endif
929
930 struct macid_ctl_t {
931 _lock lock;
932 u8 num;
933 struct macid_bmp used;
934 struct macid_bmp bmc;
935 struct macid_bmp if_g[CONFIG_IFACE_NUMBER];
936 struct macid_bmp ch_g[2]; /* 2 ch concurrency */
937
938 u8 iface_bmc[CONFIG_IFACE_NUMBER]; /* bmc TX macid for each iface*/
939
940 u8 h2c_msr[MACID_NUM_SW_LIMIT];
941 u8 bw[MACID_NUM_SW_LIMIT];
942 u8 vht_en[MACID_NUM_SW_LIMIT];
943 u32 rate_bmp0[MACID_NUM_SW_LIMIT];
944 u32 rate_bmp1[MACID_NUM_SW_LIMIT];
945 u8 op_num[H2C_MSR_ROLE_MAX]; /* number of macid having h2c_msr's OPMODE = 1 for specific ROLE */
946
947 struct sta_info *sta[MACID_NUM_SW_LIMIT]; /* corresponding stainfo when macid is not shared */
948 u8 macid_cap;
949 /* macid sleep registers */
950 #ifdef CONFIG_PROTSEL_MACSLEEP
951 u16 reg_sleep_ctrl;
952 u16 reg_sleep_info;
953 u16 reg_drop_ctrl;
954 u16 reg_drop_info;
955 #else
956 u16 reg_sleep_m0;
957 u16 reg_drop_m0;
958 #if (MACID_NUM_SW_LIMIT > 32)
959 u16 reg_sleep_m1;
960 u16 reg_drop_m1;
961 #endif
962 #if (MACID_NUM_SW_LIMIT > 64)
963 u16 reg_sleep_m2;
964 u16 reg_drop_m2;
965 #endif
966 #if (MACID_NUM_SW_LIMIT > 96)
967 u16 reg_sleep_m3;
968 u16 reg_drop_m3;
969 #endif
970 #endif
971 u16 macid_txrpt;
972 u8 macid_txrpt_pgsz;
973 };
974
975 /* used for rf_ctl_t.rate_bmp_cck_ofdm */
976 #define RATE_BMP_CCK 0x000F
977 #define RATE_BMP_OFDM 0xFFF0
978 #define RATE_BMP_HAS_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK)
979 #define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_OFDM)
980 #define RATE_BMP_GET_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK)
981 #define RATE_BMP_GET_OFDM(_bmp_cck_ofdm) ((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4)
982
983 /* used for rf_ctl_t.rate_bmp_ht_by_bw */
984 #define RATE_BMP_HT_1SS 0x000000FF
985 #define RATE_BMP_HT_2SS 0x0000FF00
986 #define RATE_BMP_HT_3SS 0x00FF0000
987 #define RATE_BMP_HT_4SS 0xFF000000
988 #define RATE_BMP_HAS_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS)
989 #define RATE_BMP_HAS_HT_2SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_2SS)
990 #define RATE_BMP_HAS_HT_3SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_3SS)
991 #define RATE_BMP_HAS_HT_4SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_4SS)
992 #define RATE_BMP_GET_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS)
993 #define RATE_BMP_GET_HT_2SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_2SS) >> 8)
994 #define RATE_BMP_GET_HT_3SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_3SS) >> 16)
995 #define RATE_BMP_GET_HT_4SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_4SS) >> 24)
996
997 /* used for rf_ctl_t.rate_bmp_vht_by_bw */
998 #define RATE_BMP_VHT_1SS 0x00000003FF
999 #define RATE_BMP_VHT_2SS 0x00000FFC00
1000 #define RATE_BMP_VHT_3SS 0x003FF00000
1001 #define RATE_BMP_VHT_4SS 0xFFC0000000
1002 #define RATE_BMP_HAS_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS)
1003 #define RATE_BMP_HAS_VHT_2SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_2SS)
1004 #define RATE_BMP_HAS_VHT_3SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_3SS)
1005 #define RATE_BMP_HAS_VHT_4SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_4SS)
1006 #define RATE_BMP_GET_VHT_1SS(_bmp_vht) ((u16)(_bmp_vht & RATE_BMP_VHT_1SS))
1007 #define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_2SS) >> 10))
1008 #define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_3SS) >> 20))
1009 #define RATE_BMP_GET_VHT_4SS(_bmp_vht) ((u16)((_bmp_vht & RATE_BMP_VHT_4SS) >> 30))
1010
1011 #define TXPWR_LMT_REF_VHT_FROM_HT BIT0
1012 #define TXPWR_LMT_REF_HT_FROM_VHT BIT1
1013
1014 #define TXPWR_LMT_HAS_CCK_1T BIT0
1015 #define TXPWR_LMT_HAS_CCK_2T BIT1
1016 #define TXPWR_LMT_HAS_CCK_3T BIT2
1017 #define TXPWR_LMT_HAS_CCK_4T BIT3
1018 #define TXPWR_LMT_HAS_OFDM_1T BIT4
1019 #define TXPWR_LMT_HAS_OFDM_2T BIT5
1020 #define TXPWR_LMT_HAS_OFDM_3T BIT6
1021 #define TXPWR_LMT_HAS_OFDM_4T BIT7
1022
1023 #define OFFCHS_NONE 0
1024 #define OFFCHS_LEAVING_OP 1
1025 #define OFFCHS_LEAVE_OP 2
1026 #define OFFCHS_BACKING_OP 3
1027
1028 #define TPC_MODE_DISABLE 0
1029 #define TPC_MODE_MANUAL 1
1030 #define TPC_MODE_INVALID 2 /* keep last */
1031
1032 #define TPC_MANUAL_CONSTRAINT_MAX 600 /* mB */
1033
1034 #define COUNTRY_IE_SLAVE_EN_ROLE_STA BIT0 /* pure STA mode */
1035 #define COUNTRY_IE_SLAVE_EN_ROLE_GC BIT1 /* P2P group client */
1036
1037 #define MAX_CSA_CNT 10
1038
1039 struct rf_ctl_t {
1040 bool disable_sw_chplan;
1041 enum regd_src_t regd_src;
1042 enum rtw_regd_inr regd_inr;
1043 char alpha2[2];
1044 u8 ChannelPlan;
1045 #if CONFIG_IEEE80211_BAND_6GHZ
1046 u8 chplan_6g;
1047 #endif
1048 u8 edcca_mode_2g_override;
1049 #if CONFIG_IEEE80211_BAND_5GHZ
1050 u8 edcca_mode_5g_override;
1051 #endif
1052 #if CONFIG_IEEE80211_BAND_6GHZ
1053 u8 edcca_mode_6g_override;
1054 #endif
1055 #if CONFIG_TXPWR_LIMIT
1056 u8 txpwr_lmt_override;
1057 #endif
1058
1059 #if defined(CONFIG_80211AX_HE) || defined(CONFIG_80211AC_VHT)
1060 u8 proto_en;
1061 #endif
1062
1063 /* initial channel plan selectors */
1064 char init_alpha2[2];
1065 u8 init_ChannelPlan;
1066 #if CONFIG_IEEE80211_BAND_6GHZ
1067 u8 init_chplan_6g;
1068 #endif
1069
1070 /* channel plan selectors by user */
1071 char user_alpha2[2]; /* "\x00\x00" is not set */
1072 u8 user_ChannelPlan;
1073 #if CONFIG_IEEE80211_BAND_6GHZ
1074 u8 user_chplan_6g;
1075 #endif
1076
1077 #ifdef CONFIG_80211D
1078 u8 country_ie_slave_en_role;
1079 u8 country_ie_slave_en_ifbmp;
1080
1081 struct country_ie_slave_record cisr[CONFIG_IFACE_NUMBER];
1082 u8 effected_cisr_id;
1083 #endif
1084
1085 u8 max_chan_nums;
1086 RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM];
1087 struct op_class_pref_t **spt_op_class_ch;
1088 u8 cap_spt_op_class_num;
1089 u8 reg_spt_op_class_num;
1090 u8 cur_spt_op_class_num;
1091 struct p2p_channels channel_list;
1092 #ifdef CONFIG_RTW_MBO
1093 struct npref_ch_rtp ch_rtp;
1094 #endif
1095
1096 s16 antenna_gain; /* mBi */
1097
1098 u8 op_class;
1099 u8 op_ch;
1100 s16 op_txpwr_max; /* EIRP in mBm */
1101 u8 if_op_class[CONFIG_IFACE_NUMBER];
1102 u8 if_op_ch[CONFIG_IFACE_NUMBER];
1103
1104 _mutex offch_mutex;
1105 u8 offch_state;
1106
1107 /* used for debug or by tx power limit */
1108 u16 rate_bmp_cck_ofdm; /* 20MHz */
1109 u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */
1110 u64 rate_bmp_vht_by_bw[4]; /* 20MHz, 40MHz, 80MHz, 160MHz. 4SS supported */
1111
1112 #if CONFIG_TXPWR_LIMIT
1113 u8 highest_ht_rate_bw_bmp;
1114 u8 highest_vht_rate_bw_bmp;
1115
1116 _mutex txpwr_lmt_mutex;
1117 _list reg_exc_list;
1118 u8 regd_exc_num;
1119 _list txpwr_lmt_list;
1120 u8 txpwr_lmt_num;
1121 const char *txpwr_lmt_name[BAND_MAX];
1122
1123 u8 txpwr_lmt_2g_cck_ofdm_state;
1124 #if CONFIG_IEEE80211_BAND_5GHZ
1125 u8 txpwr_lmt_5g_cck_ofdm_state;
1126 u8 txpwr_lmt_5g_20_40_ref;
1127 #endif
1128 #endif
1129 u8 tpc_mode;
1130 u16 tpc_manual_constraint; /* mB */
1131
1132 bool ch_sel_within_same_band;
1133
1134 u8 adaptivity_en; /* runtime status, hook to phydm */
1135 u8 edcca_mode_2g;
1136 #if CONFIG_IEEE80211_BAND_5GHZ
1137 u8 edcca_mode_5g;
1138 #endif
1139 #if CONFIG_IEEE80211_BAND_6GHZ
1140 u8 edcca_mode_6g;
1141 #endif
1142
1143 u8 ap_csa_ch;
1144 u8 ap_csa_switch_cnt;
1145 u8 ap_csa_ch_offset;
1146 u8 ap_csa_ch_width;
1147 u8 ap_csa_en;
1148 #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_AP_MODE)
1149 u8 ap_csa_cnt_input; /* Input from proc, default value is DEFAULT_CSA_CNT */
1150 #endif
1151
1152 #if CONFIG_DFS
1153 u8 csa_ch;
1154 u8 csa_switch_cnt;
1155 u8 csa_ch_offset;
1156 u8 csa_ch_width;
1157 u8 csa_ch_freq_seg0; /* Channel Center Frequency Segment 0 */
1158 u8 csa_ch_freq_seg1; /* Channel Center Frequency Segment 1 */
1159 #ifdef CONFIG_ECSA
1160 u8 ecsa_mode;
1161 u8 ecsa_op_class;
1162 #endif
1163
1164 #ifdef CONFIG_DFS_MASTER
1165 u8 dfs_region_domain;
1166 _timer radar_detect_timer;
1167 bool radar_detect_by_others;
1168 u8 radar_detect_enabled;
1169 bool radar_detected;
1170
1171 u8 radar_detect_ch;
1172 u8 radar_detect_bw;
1173 u8 radar_detect_offset;
1174
1175 systime cac_start_time;
1176 systime cac_end_time;
1177 u8 cac_force_stop;
1178
1179 #if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
1180 u8 dfs_slave_with_rd;
1181 #endif
1182 u8 dfs_ch_sel_e_flags;
1183 u8 dfs_ch_sel_d_flags;
1184
1185 u8 dbg_dfs_fake_radar_detect_cnt;
1186 u8 dbg_dfs_radar_detect_trigger_non;
1187 u8 dbg_dfs_choose_dfs_ch_first;
1188 #endif /* CONFIG_DFS_MASTER */
1189 #endif /* CONFIG_DFS */
1190 };
1191
1192 struct wow_ctl_t {
1193 u8 wow_cap;
1194 };
1195
1196 #define WOW_CAP_TKIP_OL BIT0
1197 #define WOW_CAP_HALMAC_ACCESS_PATTERN_IN_TXFIFO BIT1
1198
1199 #define RFCTL_REG_WORLDWIDE(rfctl) (IS_ALPHA2_WORLDWIDE(rfctl->alpha2))
1200 #define RFCTL_REG_ALPHA2_UNSPEC(rfctl) (IS_ALPHA2_UNSPEC(rfctl->alpha2)) /* ex: only domain code is specified */
1201
1202 #ifdef CONFIG_80211AC_VHT
1203 #define RFCTL_REG_EN_11AC(rfctl) (((rfctl)->proto_en & CHPLAN_PROTO_EN_AC) ? 1 : 0)
1204 #else
1205 #define RFCTL_REG_EN_11AC(rfctl) 0
1206 #endif
1207
1208 #ifdef CONFIG_80211AX_HE
1209 #define RFCTL_REG_EN_11AX(rfctl) (((rfctl)->proto_en & CHPLAN_PROTO_EN_AX) ? 1 : 0)
1210 #else
1211 #define RFCTL_REG_EN_11AX(rfctl) 0
1212 #endif
1213
1214 #define RTW_CAC_STOPPED 0
1215 #ifdef CONFIG_DFS_MASTER
1216 #define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED)
1217 #define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && rtw_time_after((rfctl)->cac_end_time, rtw_get_current_time()))
1218 #define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && rtw_time_after(rtw_get_current_time(), (rfctl)->cac_start_time))
1219 #define IS_RADAR_DETECTED(rfctl) ((rfctl)->radar_detected)
1220 #else
1221 #define IS_CAC_STOPPED(rfctl) 1
1222 #define IS_CH_WAITING(rfctl) 0
1223 #define IS_UNDER_CAC(rfctl) 0
1224 #define IS_RADAR_DETECTED(rfctl) 0
1225 #endif /* CONFIG_DFS_MASTER */
1226
1227 #if CONFIG_DFS_SLAVE_WITH_RADAR_DETECT
1228 #define IS_DFS_SLAVE_WITH_RD(rfctl) ((rfctl)->dfs_slave_with_rd)
1229 #else
1230 #define IS_DFS_SLAVE_WITH_RD(rfctl) 0
1231 #endif
1232
1233 #ifdef CONFIG_MBSSID_CAM
1234 #define TOTAL_MBID_CAM_NUM 8
1235 #define INVALID_CAM_ID 0xFF
1236 struct mbid_cam_ctl_t {
1237 _lock lock;
1238 u8 bitmap;
1239 ATOMIC_T mbid_entry_num;
1240 };
1241 struct mbid_cam_cache {
1242 u8 iface_id;
1243 /*u8 role;*/ /*WIFI_STATION_STATE or WIFI_AP_STATE*/
1244 u8 mac_addr[ETH_ALEN];
1245 };
1246 #endif /*CONFIG_MBSSID_CAM*/
1247
1248 #ifdef RTW_HALMAC
1249 struct halmac_indicator {
1250 struct submit_ctx *sctx;
1251 u8 *buffer;
1252 u32 buf_size;
1253 u32 ret_size;
1254 u32 status;
1255 };
1256
1257 struct halmacpriv {
1258 /* flags */
1259 #ifdef CONFIG_SDIO_HCI
1260 /*
1261 * Indirect Access for SDIO,
1262 * 0:default, 1:enable, 2:disable
1263 */
1264 u8 sdio_io_indir;
1265 #endif /* CONFIG_SDIO_HCI */
1266
1267 /* For asynchronous functions */
1268 struct halmac_indicator *indicator;
1269
1270 /* Hardware parameters */
1271 #ifdef CONFIG_SDIO_HCI
1272 /* Store hardware tx queue page number setting */
1273 u16 txpage[HW_QUEUE_ENTRY];
1274 #endif /* CONFIG_SDIO_HCI */
1275 };
1276 #endif /* RTW_HALMAC */
1277
1278 #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
1279 /*info for H2C-0x2C*/
1280 struct dft_info {
1281 u8 port_id;
1282 u8 mac_id;
1283 };
1284 #endif
1285
1286 #ifdef CONFIG_HW_P0_TSF_SYNC
1287 struct tsf_info {
1288 u8 sync_port;/*port_x's tsf sync to port_0*/
1289 u8 offset; /*tsf timer offset*/
1290 };
1291 #endif
1292
1293 struct protsel {
1294 _mutex mutex; /* protect this structure */
1295 ATOMIC_T refcnt; /* reference count */
1296 u32 sel; /* save the last sel port */
1297 };
1298
1299 #ifdef CONFIG_RTL8814B
1300 #define MAX_BULKOUT_NUM 7
1301 #ifdef CONFIG_USB_HCI
1302 #define MAX_ENDPOINT_NUM 8
1303 #endif
1304 #else
1305 #define MAX_BULKOUT_NUM 4
1306 #ifdef CONFIG_USB_HCI
1307 #define MAX_ENDPOINT_NUM 6
1308 #endif
1309 #endif
1310
1311 struct dvobj_priv {
1312 /*-------- below is common data --------*/
1313 u8 chip_type;
1314 u8 HardwareType;
1315 u8 interface_type;/*USB,SDIO,SPI,PCI*/
1316
1317 ATOMIC_T bSurpriseRemoved;
1318 ATOMIC_T bDriverStopped;
1319
1320 s32 processing_dev_remove;
1321
1322 struct debug_priv drv_dbg;
1323
1324 _mutex hw_init_mutex;
1325 _mutex h2c_fwcmd_mutex;
1326
1327 _mutex ioctrl_mutex;
1328
1329 #ifdef CONFIG_RTW_CUSTOMER_STR
1330 _mutex customer_str_mutex;
1331 struct submit_ctx *customer_str_sctx;
1332 u8 customer_str[RTW_CUSTOMER_STR_LEN];
1333 #endif
1334
1335 _mutex setch_mutex;
1336 _mutex setbw_mutex;
1337 _mutex rf_read_reg_mutex;
1338 #ifdef CONFIG_SDIO_INDIRECT_ACCESS
1339 _mutex sd_indirect_access_mutex;
1340 #endif
1341
1342 #ifdef CONFIG_SYSON_INDIRECT_ACCESS
1343 _mutex syson_indirect_access_mutex; /* System On Reg R/W */
1344 #endif
1345
1346 unsigned char oper_channel; /* saved channel info when call set_channel_bw */
1347 unsigned char oper_bwmode;
1348 unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */
1349 systime on_oper_ch_time;
1350
1351 u8 union_ch;
1352 u8 union_bw;
1353 u8 union_offset;
1354 /* backup values when union_ch is set to 0 */
1355 u8 union_ch_bak;
1356 u8 union_bw_bak;
1357 u8 union_offset_bak;
1358
1359 _adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/
1360 u8 iface_nums; /* total number of ifaces used runtime */
1361 struct mi_state iface_state;
1362
1363 #ifdef CONFIG_AP_MODE
1364 #ifdef CONFIG_SUPPORT_MULTI_BCN
1365 u8 nr_ap_if; /* total interface number of ap /go /mesh / nan mode. */
1366 u16 inter_bcn_space; /* unit:ms */
1367 _queue ap_if_q;
1368 u8 vap_map;
1369 u8 fw_bcn_offload;
1370 u8 vap_tbtt_rpt_map;
1371 #endif /*CONFIG_SUPPORT_MULTI_BCN*/
1372 #ifdef CONFIG_RTW_REPEATER_SON
1373 struct rtw_rson_struct rson_data;
1374 #endif
1375 #endif
1376 #ifdef CONFIG_CLIENT_PORT_CFG
1377 struct clt_port_t clt_port;
1378 #endif
1379
1380 #ifdef CONFIG_HW_P0_TSF_SYNC
1381 struct tsf_info p0_tsf;
1382 #endif
1383 systime periodic_tsf_update_etime;
1384 _timer periodic_tsf_update_end_timer;
1385
1386 struct macid_ctl_t macid_ctl;
1387
1388 struct cam_ctl_t cam_ctl;
1389 struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT];
1390
1391 struct wow_ctl_t wow_ctl;
1392
1393 #ifdef CONFIG_MBSSID_CAM
1394 struct mbid_cam_ctl_t mbid_cam_ctl;
1395 struct mbid_cam_cache mbid_cam_cache[TOTAL_MBID_CAM_NUM];
1396 #endif
1397
1398 struct rf_ctl_t rf_ctl;
1399
1400 #if CONFIG_TX_AC_LIFETIME
1401 struct tx_aclt_conf_t tx_aclt_force_val;
1402 u8 tx_aclt_flags;
1403 struct tx_aclt_conf_t tx_aclt_confs[TX_ACLT_CONF_NUM];
1404 #endif
1405
1406 /* In /Out Pipe information */
1407 int RtInPipe[2];
1408 int RtOutPipe[MAX_BULKOUT_NUM];
1409 u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */
1410
1411 u8 irq_alloc;
1412 ATOMIC_T continual_io_error;
1413
1414 ATOMIC_T disable_func;
1415
1416 u8 xmit_block;
1417 _lock xmit_block_lock;
1418
1419 struct pwrctrl_priv pwrctl_priv;
1420
1421 struct rtw_traffic_statistics traffic_stat;
1422
1423 #ifdef PLATFORM_LINUX
1424 _thread_hdl_ rtnl_lock_holder;
1425
1426 #if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY)
1427 struct wiphy *wiphy;
1428 #endif
1429 #endif /* PLATFORM_LINUX */
1430
1431 #ifdef CONFIG_SWTIMER_BASED_TXBCN
1432 _timer txbcn_timer;
1433 #endif
1434 _timer dynamic_chk_timer; /* dynamic/periodic check timer */
1435
1436 #ifdef CONFIG_RTW_NAPI_DYNAMIC
1437 u8 en_napi_dynamic;
1438 #endif /* CONFIG_RTW_NAPI_DYNAMIC */
1439
1440 #ifdef RTW_HALMAC
1441 void *halmac;
1442 struct halmacpriv hmpriv;
1443 #endif /* RTW_HALMAC */
1444
1445 #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
1446 /*info for H2C-0x2C*/
1447 struct dft_info dft;
1448 #endif
1449
1450 #ifdef CONFIG_RTW_WIFI_HAL
1451 u32 nodfs;
1452 #endif
1453
1454 /*-------- below is for SDIO INTERFACE --------*/
1455
1456 #ifdef INTF_DATA
1457 INTF_DATA intf_data;
1458 #endif
1459 #ifdef INTF_OPS
1460 INTF_OPS intf_ops;
1461 #endif
1462
1463 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
1464 u8 tx_aval_int_thr_mode;/* if 0=>threhold set by reques(default) ;if 1=>fixed by proc; if 2: fixed by sdio_tx_max_len */
1465 u8 tx_aval_int_thr_value;
1466 #endif/*CONFIG_SDIO_TX_ENABLE_AVAL_INT*/
1467
1468 /*-------- below is for USB INTERFACE --------*/
1469
1470 #ifdef CONFIG_USB_HCI
1471
1472 u8 usb_speed; /* 1.1, 2.0 or 3.0 */
1473 u8 nr_endpoint;
1474 u8 RtNumInPipes;
1475 u8 RtNumOutPipes;
1476 int ep_num[MAX_ENDPOINT_NUM]; /* endpoint number */
1477
1478 int RegUsbSS;
1479
1480 _sema usb_suspend_sema;
1481
1482 #ifdef CONFIG_USB_VENDOR_REQ_MUTEX
1483 _mutex usb_vendor_req_mutex;
1484 #endif
1485
1486 #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC
1487 u8 *usb_alloc_vendor_req_buf;
1488 u8 *usb_vendor_req_buf;
1489 #endif
1490
1491 #ifdef PLATFORM_LINUX
1492 struct usb_interface *pusbintf;
1493 struct usb_device *pusbdev;
1494 #endif/* PLATFORM_LINUX */
1495
1496 #ifdef PLATFORM_FREEBSD
1497 struct usb_interface *pusbintf;
1498 struct usb_device *pusbdev;
1499 #endif/* PLATFORM_FREEBSD */
1500
1501 #endif/* CONFIG_USB_HCI */
1502
1503 /*-------- below is for PCIE INTERFACE --------*/
1504
1505 #ifdef CONFIG_PCI_HCI
1506
1507 #ifdef PLATFORM_LINUX
1508 struct pci_dev *ppcidev;
1509
1510 /* PCI MEM map */
1511 unsigned long pci_mem_end; /* shared mem end */
1512 unsigned long pci_mem_start; /* shared mem start */
1513
1514 /* PCI IO map */
1515 unsigned long pci_base_addr; /* device I/O address */
1516
1517 #ifdef CONFIG_PLATFORM_RTK129X
1518 unsigned long ctrl_start;
1519 /* PCI MASK addr */
1520 unsigned long mask_addr;
1521
1522 /* PCI TRANSLATE addr */
1523 unsigned long tran_addr;
1524
1525 _lock io_reg_lock;
1526 #endif
1527
1528 /* PciBridge */
1529 struct pci_priv pcipriv;
1530
1531 unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */
1532 u16 irqline;
1533 u8 irq_enabled;
1534 RT_ISR_CONTENT isr_content;
1535 _lock irq_th_lock;
1536
1537 u8 bdma64;
1538 #endif/* PLATFORM_LINUX */
1539
1540 #endif/* CONFIG_PCI_HCI */
1541
1542 #ifdef CONFIG_MCC_MODE
1543 struct mcc_obj_priv mcc_objpriv;
1544 #endif /*CONFIG_MCC_MODE */
1545
1546 #ifdef CONFIG_RTW_TPT_MODE
1547 u8 tpt_mode; /* RTK T/P Testing Mode, 0:default mode */
1548 u32 edca_be_ul;
1549 u32 edca_be_dl;
1550 #endif
1551 /* also for RTK T/P Testing Mode */
1552 u8 scan_deny;
1553
1554 /* protect sel to safely access */
1555 #ifdef CONFIG_PROTSEL_PORT
1556 struct protsel protsel_port;
1557 #endif
1558 #ifdef CONFIG_PROTSEL_ATIMDTIM
1559 struct protsel protsel_atimdtim;
1560 #endif
1561 #ifdef CONFIG_PROTSEL_MACSLEEP
1562 struct protsel protsel_macsleep;
1563 #endif
1564 #ifdef CONFIG_WOWLAN
1565 u8 bcn_ctrl_clint3_bf_suspend;
1566 u16 rxfltmap2_bf_suspend;
1567 u8 lifetime_en;
1568 u32 pkt_lifetime;
1569 u32 rcr_bf_suspend;
1570 u32 cr_ext_bf_suspend;
1571 #endif /* CONFIG_WOWLAN */
1572 #if defined (CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC)
1573 u16 sync_tsfr_counter;
1574 #endif
1575
1576 /* WPAS maintain from w1.fi */
1577 #define RTW_WPAS_W1FI 0x00
1578 /* WPAS maintain from android */
1579 #define RTW_WPAS_ANDROID 0x01
1580 u8 wpas_type;
1581 };
1582
1583 #define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state))
1584 #define DEV_STA_LD_NUM(_dvobj) MSTATE_STA_LD_NUM(&((_dvobj)->iface_state))
1585 #define DEV_STA_LG_NUM(_dvobj) MSTATE_STA_LG_NUM(&((_dvobj)->iface_state))
1586 #define DEV_TDLS_LD_NUM(_dvobj) MSTATE_TDLS_LD_NUM(&((_dvobj)->iface_state))
1587 #define DEV_AP_NUM(_dvobj) MSTATE_AP_NUM(&((_dvobj)->iface_state))
1588 #define DEV_AP_STARTING_NUM(_dvobj) MSTATE_AP_STARTING_NUM(&((_dvobj)->iface_state))
1589 #define DEV_AP_LD_NUM(_dvobj) MSTATE_AP_LD_NUM(&((_dvobj)->iface_state))
1590 #define DEV_ADHOC_NUM(_dvobj) MSTATE_ADHOC_NUM(&((_dvobj)->iface_state))
1591 #define DEV_ADHOC_LD_NUM(_dvobj) MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state))
1592 #define DEV_MESH_NUM(_dvobj) MSTATE_MESH_NUM(&((_dvobj)->iface_state))
1593 #define DEV_MESH_LD_NUM(_dvobj) MSTATE_MESH_LD_NUM(&((_dvobj)->iface_state))
1594 #define DEV_P2P_DV_NUM(_dvobj) MSTATE_P2P_DV_NUM(&((_dvobj)->iface_state))
1595 #define DEV_P2P_GC_NUM(_dvobj) MSTATE_P2P_GC_NUM(&((_dvobj)->iface_state))
1596 #define DEV_P2P_GO_NUM(_dvobj) MSTATE_P2P_GO_NUM(&((_dvobj)->iface_state))
1597 #define DEV_SCAN_NUM(_dvobj) MSTATE_SCAN_NUM(&((_dvobj)->iface_state))
1598 #define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state))
1599 #define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state))
1600 #define DEV_MGMT_TX_NUM(_dvobj) MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state))
1601
1602 #define DEV_U_CH(_dvobj) ((_dvobj)->union_ch)
1603 #define DEV_U_BW(_dvobj) ((_dvobj)->union_bw)
1604 #define DEV_U_OFFSET(_dvobj) ((_dvobj)->union_offset)
1605
1606 #define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv))
1607 #define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv)
1608 #define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl))
1609 #define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl))
1610 #define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv))
1611 #ifdef CONFIG_IOCTL_CFG80211
1612 #ifdef RTW_SINGLE_WIPHY
1613 #define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy)
1614 #else
1615 #define dvobj_to_wiphy(dvobj) (adapter_to_wiphy(dvobj_get_primary_adapter(dvobj)))
1616 #endif
1617 #endif /* CONFIG_IOCTL_CFG80211 */
1618 #define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl))
1619 #define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl)
1620
dev_set_surprise_removed(struct dvobj_priv * dvobj)1621 static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj)
1622 {
1623 ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE);
1624 }
dev_clr_surprise_removed(struct dvobj_priv * dvobj)1625 static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj)
1626 {
1627 ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE);
1628 }
dev_set_drv_stopped(struct dvobj_priv * dvobj)1629 static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj)
1630 {
1631 ATOMIC_SET(&dvobj->bDriverStopped, _TRUE);
1632 }
dev_clr_drv_stopped(struct dvobj_priv * dvobj)1633 static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj)
1634 {
1635 ATOMIC_SET(&dvobj->bDriverStopped, _FALSE);
1636 }
1637 #define dev_is_surprise_removed(dvobj) (ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE)
1638 #define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE)
1639
1640 #ifdef PLATFORM_LINUX
dvobj_to_dev(struct dvobj_priv * dvobj)1641 static inline struct device *dvobj_to_dev(struct dvobj_priv *dvobj)
1642 {
1643 /* todo: get interface type from dvobj and the return the dev accordingly */
1644 #ifdef RTW_DVOBJ_CHIP_HW_TYPE
1645 #endif
1646
1647 #ifdef CONFIG_USB_HCI
1648 return &dvobj->pusbintf->dev;
1649 #endif
1650 #ifdef CONFIG_SDIO_HCI
1651 return &dvobj->intf_data.func->dev;
1652 #endif
1653 #ifdef CONFIG_GSPI_HCI
1654 return &dvobj->intf_data.func->dev;
1655 #endif
1656 #ifdef CONFIG_PCI_HCI
1657 return &dvobj->ppcidev->dev;
1658 #endif
1659 }
1660 #endif
1661
1662 _adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj);
1663 _adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj);
1664 _adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr);
1665 #define dvobj_get_primary_adapter(dvobj) ((dvobj)->padapters[IFACE_ID0])
1666
1667 enum _hw_port {
1668 HW_PORT0,
1669 HW_PORT1,
1670 HW_PORT2,
1671 HW_PORT3,
1672 HW_PORT4,
1673 MAX_HW_PORT,
1674 };
1675
1676 #ifdef CONFIG_CLIENT_PORT_CFG
1677 enum _client_port {
1678 CLT_PORT0 = HW_PORT1,
1679 CLT_PORT1 = HW_PORT2,
1680 CLT_PORT2 = HW_PORT3,
1681 CLT_PORT3 = HW_PORT4,
1682 CLT_PORT_INVALID = HW_PORT0,
1683 };
1684
1685 #define MAX_CLIENT_PORT_NUM 4
1686 #define get_clt_port(adapter) (adapter->client_port)
1687 #endif
1688
1689 enum _ADAPTER_TYPE {
1690 PRIMARY_ADAPTER,
1691 VIRTUAL_ADAPTER,
1692 MAX_ADAPTER = 0xFF,
1693 };
1694
1695 typedef enum _DRIVER_STATE {
1696 DRIVER_NORMAL = 0,
1697 DRIVER_DISAPPEAR = 1,
1698 DRIVER_REPLACE_DONGLE = 2,
1699 } DRIVER_STATE;
1700
1701 #ifdef CONFIG_RTW_NAPI
1702 enum _NAPI_STATE {
1703 NAPI_DISABLE = 0,
1704 NAPI_ENABLE = 1,
1705 };
1706 #endif
1707
1708 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1709 typedef struct loopbackdata {
1710 _sema sema;
1711 _thread_hdl_ lbkthread;
1712 u8 bstop;
1713 u32 cnt;
1714 u16 size;
1715 u16 txsize;
1716 u8 txbuf[0x8000];
1717 u16 rxsize;
1718 u8 rxbuf[0x8000];
1719 u8 msg[100];
1720
1721 } LOOPBACKDATA, *PLOOPBACKDATA;
1722 #endif
1723
1724 #define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode)
1725 #define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode)
1726
1727 struct _ADAPTER {
1728 int DriverState;/* for disable driver using module, use dongle to replace module. */
1729 int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */
1730 int bDongle;/* build-in module or external dongle */
1731
1732 #if defined(CONFIG_AP_MODE) && defined(CONFIG_SUPPORT_MULTI_BCN)
1733 _list list;
1734 u8 vap_id;
1735 #endif
1736 struct dvobj_priv *dvobj;
1737 struct mlme_priv mlmepriv;
1738 struct mlme_ext_priv mlmeextpriv;
1739 struct cmd_priv cmdpriv;
1740 struct evt_priv evtpriv;
1741
1742 #ifdef CONFIG_RTW_80211K
1743 struct rm_priv rmpriv;
1744 #endif
1745 /* struct io_queue *pio_queue; */
1746 struct io_priv iopriv;
1747 struct xmit_priv xmitpriv;
1748 struct recv_priv recvpriv;
1749 struct sta_priv stapriv;
1750 struct security_priv securitypriv;
1751 _lock security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */
1752 struct registry_priv registrypriv;
1753
1754 #ifdef CONFIG_RTW_NAPI
1755 struct napi_struct napi;
1756 u8 napi_state;
1757 #endif
1758
1759 #ifdef CONFIG_MP_INCLUDED
1760 struct mp_priv mppriv;
1761 #endif
1762
1763 #ifdef CONFIG_AP_MODE
1764 struct hostapd_priv *phostapdpriv;
1765 #endif
1766
1767 #if defined(CONFIG_P2P) && defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_IOCTL_CFG80211)
1768 struct roch_info rochinfo;
1769 #endif
1770
1771 u32 setband;
1772 ATOMIC_T bandskip;
1773
1774 #ifdef CONFIG_P2P
1775 struct wifidirect_info wdinfo;
1776 #endif /* CONFIG_P2P */
1777
1778 #ifdef CONFIG_TDLS
1779 struct tdls_info tdlsinfo;
1780 #endif /* CONFIG_TDLS */
1781
1782 #ifdef CONFIG_WAPI_SUPPORT
1783 u8 WapiSupport;
1784 RT_WAPI_T wapiInfo;
1785 #endif
1786
1787 #ifdef CONFIG_RTW_REPEATER_SON
1788 u8 rtw_rson_scanstage;
1789 #endif
1790
1791 #ifdef CONFIG_WFD
1792 struct wifi_display_info wfd_info;
1793 #endif /* CONFIG_WFD */
1794
1795 #ifdef CONFIG_BT_COEXIST_SOCKET_TRX
1796 struct bt_coex_info coex_info;
1797 #endif /* CONFIG_BT_COEXIST_SOCKET_TRX */
1798
1799 ERROR_CODE LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */
1800
1801 void *HalData;
1802 u32 hal_data_sz;
1803 struct hal_ops hal_func;
1804
1805 u32 IsrContent;
1806 u32 ImrContent;
1807
1808 u8 EepromAddressSize;
1809 u8 bDriverIsGoingToUnload;
1810 u8 init_adpt_in_progress;
1811 u8 bHaltInProgress;
1812 #ifdef CONFIG_GPIO_API
1813 u8 pre_gpio_pin;
1814 struct gpio_int_priv {
1815 u8 interrupt_mode;
1816 u8 interrupt_enable_mask;
1817 void (*callback[8])(u8 level);
1818 } gpiointpriv;
1819 #endif
1820 _thread_hdl_ cmdThread;
1821 #ifdef CONFIG_EVENT_THREAD_MODE
1822 _thread_hdl_ evtThread;
1823 #endif
1824 #ifdef CONFIG_XMIT_THREAD_MODE
1825 _thread_hdl_ xmitThread;
1826 #endif
1827 #ifdef CONFIG_RECV_THREAD_MODE
1828 _thread_hdl_ recvThread;
1829 #endif
1830 u8 registered;
1831
1832 void (*intf_start)(_adapter *adapter);
1833 void (*intf_stop)(_adapter *adapter);
1834
1835 #ifdef PLATFORM_LINUX
1836 _nic_hdl pnetdev;
1837 char old_ifname[IFNAMSIZ];
1838 u8 ndev_unregistering;
1839 int bup;
1840 struct net_device_stats stats;
1841 struct iw_statistics iwstats;
1842 struct proc_dir_entry *dir_dev;/* for proc directory */
1843 struct proc_dir_entry *dir_odm;
1844
1845 #ifdef CONFIG_MCC_MODE
1846 struct proc_dir_entry *dir_mcc;
1847 #endif /* CONFIG_MCC_MODE */
1848
1849 #ifdef CONFIG_IOCTL_CFG80211
1850 struct wireless_dev *rtw_wdev;
1851 struct rtw_wdev_priv wdev_data;
1852
1853 #if !defined(RTW_SINGLE_WIPHY)
1854 struct wiphy *wiphy;
1855 #endif
1856
1857 #endif /* CONFIG_IOCTL_CFG80211 */
1858
1859 #ifdef CONFIG_PLATFORM_CMAP_INTFS
1860 void *cmap_bss_status_evt;
1861 u32 cmap_bss_status_evt_len;
1862 u8 cmap_unassoc_sta_measure_en;
1863 #endif
1864
1865 #endif /* PLATFORM_LINUX */
1866
1867 #ifdef PLATFORM_FREEBSD
1868 _nic_hdl pifp;
1869 int bup;
1870 _lock glock;
1871 #endif /* PLATFORM_FREEBSD */
1872 u8 mac_addr[ETH_ALEN];
1873 int net_closed;
1874
1875 u8 netif_up;
1876
1877 u8 bLinkInfoDump;
1878 /* Added by Albert 2012/10/26 */
1879 /* The driver will show up the desired channel number when this flag is 1. */
1880 u8 bNotifyChannelChange;
1881 u8 bsta_tp_dump;
1882 #ifdef CONFIG_P2P
1883 /* Added by Albert 2012/12/06 */
1884 /* The driver will show the current P2P status when the upper application reads it. */
1885 u8 bShowGetP2PState;
1886 #endif
1887
1888 u8 isprimary; /* is primary adapter or not */
1889 /* notes:
1890 ** if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER
1891 ** if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER
1892 ** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/
1893 u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/
1894 u8 hw_port; /*interface port type, it depends on HW port */
1895
1896 #ifdef CONFIG_CLIENT_PORT_CFG
1897 u8 client_id;
1898 u8 client_port;
1899 #endif
1900 /*struct tsf_info tsf;*//*reserve define for 8814B*/
1901
1902 /*extend to support multi interface*/
1903 u8 iface_id;
1904
1905 #ifdef CONFIG_BR_EXT
1906 _lock br_ext_lock;
1907 /* unsigned int macclone_completed; */
1908 struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE];
1909 int pppoe_connection_in_progress;
1910 unsigned char pppoe_addr[MACADDRLEN];
1911 unsigned char scdb_mac[MACADDRLEN];
1912 unsigned char scdb_ip[4];
1913 struct nat25_network_db_entry *scdb_entry;
1914 unsigned char br_mac[MACADDRLEN];
1915 unsigned char br_ip[4];
1916
1917 struct br_ext_info ethBrExtInfo;
1918 #endif /* CONFIG_BR_EXT */
1919
1920 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1921 PLOOPBACKDATA ploopback;
1922 #endif
1923 #ifdef CONFIG_AP_MODE
1924 u8 bmc_tx_rate;
1925 #if CONFIG_RTW_AP_DATA_BMC_TO_UC
1926 u8 b2u_flags_ap_src;
1927 u8 b2u_flags_ap_fwd;
1928 #endif
1929 #endif
1930
1931 /* for debug purpose */
1932 u8 fix_rate;
1933 u8 fix_bw;
1934 u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */
1935 u8 power_offset;
1936 u8 driver_tx_bw_mode;
1937 u8 rsvd_page_offset;
1938 u8 rsvd_page_num;
1939 u8 ch_clm_ratio;
1940 u8 ch_nhm_ratio;
1941 #ifdef CONFIG_SUPPORT_FIFO_DUMP
1942 u8 fifo_sel;
1943 u32 fifo_addr;
1944 u32 fifo_size;
1945 #endif
1946
1947 u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */
1948 u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */
1949 u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */
1950 u8 driver_rx_ampdu_factor;/* 0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; */
1951 u8 driver_rx_ampdu_spacing; /* driver control Rx AMPDU Density */
1952 u8 fix_rx_ampdu_accept;
1953 u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */
1954 #ifdef CONFIG_TX_AMSDU
1955 u8 tx_amsdu;
1956 u16 tx_amsdu_rate;
1957 #endif
1958 u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/
1959 #ifdef DBG_RX_COUNTER_DUMP
1960 u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/
1961 u32 drv_rx_cnt_ok;
1962 u32 drv_rx_cnt_crcerror;
1963 u32 drv_rx_cnt_drop;
1964 #endif
1965
1966 #ifdef CONFIG_DBG_COUNTER
1967 struct rx_logs rx_logs;
1968 struct tx_logs tx_logs;
1969 struct int_logs int_logs;
1970 #endif
1971
1972 #ifdef CONFIG_MCC_MODE
1973 struct mcc_adapter_priv mcc_adapterpriv;
1974 #endif /* CONFIG_MCC_MODE */
1975
1976 #ifdef CONFIG_RTW_WDS
1977 bool use_wds; /* for STA, AP mode */
1978
1979 /* for STA mode */
1980 struct rtw_wds_gptr_table *wds_gpt_records;
1981 ATOMIC_T wds_gpt_record_num;
1982
1983 /* for AP mode */
1984 #ifdef CONFIG_AP_MODE
1985 struct rtw_wds_table *wds_paths;
1986 ATOMIC_T wds_path_num;
1987 #endif
1988 #endif /* CONFIG_RTW_WDS */
1989
1990 #ifdef CONFIG_RTW_MULTI_AP
1991 u8 multi_ap;
1992 u8 ch_util_threshold;
1993 #endif
1994
1995 #ifdef CONFIG_RTW_MESH
1996 struct rtw_mesh_cfg mesh_cfg;
1997 struct rtw_mesh_info mesh_info;
1998 _timer mesh_path_timer;
1999 _timer mesh_path_root_timer;
2000 _timer mesh_atlm_param_req_timer; /* airtime link metrics param request timer */
2001 _workitem mesh_work;
2002 unsigned long wrkq_flags;
2003 #endif /* CONFIG_RTW_MESH */
2004
2005 #ifdef CONFIG_RTW_TOKEN_BASED_XMIT
2006 ATOMIC_T tbtx_tx_pause;
2007 ATOMIC_T tbtx_remove_tx_pause;
2008 u8 tbtx_capability;
2009 u32 tbtx_duration;
2010 #endif /* CONFIG_RTW_TOKEN_BASED_XMIT */
2011
2012 #ifdef RTW_SIMPLE_CONFIG
2013 u8 rtw_simple_config;
2014 #endif
2015 };
2016
2017 #define adapter_to_dvobj(adapter) ((adapter)->dvobj)
2018 #define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter)))
2019 #define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter)))
2020 #define adapter_wdev_data(adapter) (&((adapter)->wdev_data))
2021 #if defined(RTW_SINGLE_WIPHY)
2022 #define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter))
2023 #else
2024 #define adapter_to_wiphy(adapter) ((adapter)->wiphy)
2025 #endif
2026
2027 #define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter)))
2028 #define adapter_to_macidctl(adapter) dvobj_to_macidctl(adapter_to_dvobj((adapter)))
2029
2030 #ifdef CONFIG_RTW_WDS
2031 #define adapter_use_wds(adapter) (adapter->use_wds)
2032 #define adapter_set_use_wds(adapter, en) do { \
2033 (adapter)->use_wds = (en) ? 1 : 0; \
2034 RTW_INFO(FUNC_ADPT_FMT" set use_wds=%d\n", FUNC_ADPT_ARG(adapter), (adapter)->use_wds); \
2035 } while (0)
2036 #else
2037 #define adapter_use_wds(adapter) 0
2038 #endif
2039
2040 #define adapter_mac_addr(adapter) (adapter->mac_addr)
2041 #if defined(CONFIG_RTW_CFGVENDOR_RANDOM_MAC_OUI) || defined(CONFIG_RTW_SCAN_RAND)
2042 #define adapter_pno_mac_addr(adapter) \
2043 ((adapter_wdev_data(adapter))->pno_mac_addr)
2044 #endif
2045
2046 #define adapter_to_chset(adapter) (adapter_to_rfctl((adapter))->channel_set)
2047
2048 #define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv)
2049 #define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo)
2050
2051 #define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type)
2052 #define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType)
2053 #define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type)
2054
2055 #define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums)
2056
rtw_set_surprise_removed(_adapter * padapter)2057 static inline void rtw_set_surprise_removed(_adapter *padapter)
2058 {
2059 dev_set_surprise_removed(adapter_to_dvobj(padapter));
2060 }
rtw_clr_surprise_removed(_adapter * padapter)2061 static inline void rtw_clr_surprise_removed(_adapter *padapter)
2062 {
2063 dev_clr_surprise_removed(adapter_to_dvobj(padapter));
2064 }
rtw_set_drv_stopped(_adapter * padapter)2065 static inline void rtw_set_drv_stopped(_adapter *padapter)
2066 {
2067 dev_set_drv_stopped(adapter_to_dvobj(padapter));
2068 }
rtw_clr_drv_stopped(_adapter * padapter)2069 static inline void rtw_clr_drv_stopped(_adapter *padapter)
2070 {
2071 dev_clr_drv_stopped(adapter_to_dvobj(padapter));
2072 }
2073 #define rtw_is_surprise_removed(padapter) (dev_is_surprise_removed(adapter_to_dvobj(padapter)))
2074 #define rtw_is_drv_stopped(padapter) (dev_is_drv_stopped(adapter_to_dvobj(padapter)))
2075
2076 /*
2077 * Function disabled.
2078 * */
2079 #define DF_TX_BIT BIT0 /*write_port_cancel*/
2080 #define DF_RX_BIT BIT1 /*read_port_cancel*/
2081 #define DF_IO_BIT BIT2
2082
2083 /* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */
2084 /* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */
RTW_DISABLE_FUNC(_adapter * padapter,int func_bit)2085 __inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit)
2086 {
2087 int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
2088 df |= func_bit;
2089 ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
2090 }
2091
RTW_ENABLE_FUNC(_adapter * padapter,int func_bit)2092 __inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit)
2093 {
2094 int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func);
2095 df &= ~(func_bit);
2096 ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df);
2097 }
2098
2099 #define RTW_CANNOT_RUN(padapter) \
2100 (rtw_is_surprise_removed(padapter) || \
2101 rtw_is_drv_stopped(padapter))
2102
2103 #define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit))
2104
2105 #define RTW_CANNOT_IO(padapter) \
2106 (rtw_is_surprise_removed(padapter) || \
2107 RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT))
2108
2109 #define RTW_CANNOT_RX(padapter) \
2110 (RTW_CANNOT_RUN(padapter) || \
2111 RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT))
2112
2113 #define RTW_CANNOT_TX(padapter) \
2114 (RTW_CANNOT_RUN(padapter) || \
2115 RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT))
2116
2117 #ifdef CONFIG_PNO_SUPPORT
2118 int rtw_parse_ssid_list_tlv(char **list_str, pno_ssid_t *ssid, int max, int *bytes_left);
2119 int rtw_dev_pno_set(struct net_device *net, pno_ssid_t *ssid, int num,
2120 int pno_time, int pno_repeat, int pno_freq_expo_max);
2121 #ifdef CONFIG_PNO_SET_DEBUG
2122 void rtw_dev_pno_debug(struct net_device *net);
2123 #endif /* CONFIG_PNO_SET_DEBUG */
2124 #endif /* CONFIG_PNO_SUPPORT */
2125
2126 int rtw_suspend_free_assoc_resource(_adapter *padapter);
2127 #ifdef CONFIG_WOWLAN
2128 int rtw_suspend_wow(_adapter *padapter);
2129 int rtw_resume_process_wow(_adapter *padapter);
2130 #endif
2131
2132 /* HCI Related header file */
2133 #ifdef CONFIG_USB_HCI
2134 #include <usb_osintf.h>
2135 #include <usb_ops.h>
2136 #include <usb_hal.h>
2137 #endif
2138
2139 #ifdef CONFIG_SDIO_HCI
2140 #include <sdio_osintf.h>
2141 #include <sdio_ops.h>
2142 #include <sdio_hal.h>
2143 #endif
2144
2145 #ifdef CONFIG_GSPI_HCI
2146 #include <gspi_osintf.h>
2147 #include <gspi_ops.h>
2148 #include <gspi_hal.h>
2149 #endif
2150
2151 #ifdef CONFIG_PCI_HCI
2152 #include <pci_osintf.h>
2153 #include <pci_ops.h>
2154 #include <pci_hal.h>
2155 #endif
2156
2157 #endif /* __DRV_TYPES_H__ */
2158