1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36 struct clk;
37 struct clk_hw;
38 struct clk_core;
39 struct dentry;
40
41 /**
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
44 *
45 * @rate: Requested clock rate. This field will be adjusted by
46 * clock drivers according to hardware capabilities.
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 * requested constraints.
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
52 * requested constraints.
53 *
54 */
55 struct clk_rate_request {
56 unsigned long rate;
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
61 };
62
63 /**
64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
65 *
66 * @num: Numerator of the duty cycle ratio
67 * @den: Denominator of the duty cycle ratio
68 */
69 struct clk_duty {
70 unsigned int num;
71 unsigned int den;
72 };
73
74 /**
75 * struct clk_ops - Callback operations for hardware clocks; these are to
76 * be provided by the clock implementation, and will be called by drivers
77 * through the clk_* api.
78 *
79 * @prepare: Prepare the clock for enabling. This must not return until
80 * the clock is fully prepared, and it's safe to call clk_enable.
81 * This callback is intended to allow clock implementations to
82 * do any initialisation that may sleep. Called with
83 * prepare_lock held.
84 *
85 * @unprepare: Release the clock from its prepared state. This will typically
86 * undo any work done in the @prepare callback. Called with
87 * prepare_lock held.
88 *
89 * @is_prepared: Queries the hardware to determine if the clock is prepared.
90 * This function is allowed to sleep. Optional, if this op is not
91 * set then the prepare count will be used.
92 *
93 * @unprepare_unused: Unprepare the clock atomically. Only called from
94 * clk_disable_unused for prepare clocks with special needs.
95 * Called with prepare mutex held. This function may sleep.
96 *
97 * @enable: Enable the clock atomically. This must not return until the
98 * clock is generating a valid clock signal, usable by consumer
99 * devices. Called with enable_lock held. This function must not
100 * sleep.
101 *
102 * @disable: Disable the clock atomically. Called with enable_lock held.
103 * This function must not sleep.
104 *
105 * @is_enabled: Queries the hardware to determine if the clock is enabled.
106 * This function must not sleep. Optional, if this op is not
107 * set then the enable count will be used.
108 *
109 * @disable_unused: Disable the clock atomically. Only called from
110 * clk_disable_unused for gate clocks with special needs.
111 * Called with enable_lock held. This function must not
112 * sleep.
113 *
114 * @save_context: Save the context of the clock in prepration for poweroff.
115 *
116 * @restore_context: Restore the context of the clock after a restoration
117 * of power.
118 *
119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
120 * parent rate is an input parameter. It is up to the caller to
121 * ensure that the prepare_mutex is held across this call.
122 * Returns the calculated rate. Optional, but recommended - if
123 * this op is not set then clock rate will be initialized to 0.
124 *
125 * @round_rate: Given a target rate as input, returns the closest rate actually
126 * supported by the clock. The parent rate is an input/output
127 * parameter.
128 *
129 * @determine_rate: Given a target rate as input, returns the closest rate
130 * actually supported by the clock, and optionally the parent clock
131 * that should be used to provide the clock rate.
132 *
133 * @set_parent: Change the input source of this clock; for clocks with multiple
134 * possible parents specify a new parent by passing in the index
135 * as a u8 corresponding to the parent in either the .parent_names
136 * or .parents arrays. This function in affect translates an
137 * array index into the value programmed into the hardware.
138 * Returns 0 on success, -EERROR otherwise.
139 *
140 * @get_parent: Queries the hardware to determine the parent of a clock. The
141 * return value is a u8 which specifies the index corresponding to
142 * the parent clock. This index can be applied to either the
143 * .parent_names or .parents arrays. In short, this function
144 * translates the parent value read from hardware into an array
145 * index. Currently only called when the clock is initialized by
146 * __clk_init. This callback is mandatory for clocks with
147 * multiple parents. It is optional (and unnecessary) for clocks
148 * with 0 or 1 parents.
149 *
150 * @set_rate: Change the rate of this clock. The requested rate is specified
151 * by the second argument, which should typically be the return
152 * of .round_rate call. The third argument gives the parent rate
153 * which is likely helpful for most .set_rate implementation.
154 * Returns 0 on success, -EERROR otherwise.
155 *
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 * requested rate is specified by the second argument, which
158 * should typically be the return of .round_rate call. The
159 * third argument gives the parent rate which is likely helpful
160 * for most .set_rate_and_parent implementation. The fourth
161 * argument gives the parent index. This callback is optional (and
162 * unnecessary) for clocks with 0 or 1 parents as well as
163 * for clocks that can tolerate switching the rate and the parent
164 * separately via calls to .set_parent and .set_rate.
165 * Returns 0 on success, -EERROR otherwise.
166 *
167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168 * is expressed in ppb (parts per billion). The parent accuracy is
169 * an input parameter.
170 * Returns the calculated accuracy. Optional - if this op is not
171 * set then clock accuracy will be initialized to parent accuracy
172 * or 0 (perfect clock) if clock has no parent.
173 *
174 * @get_phase: Queries the hardware to get the current phase of a clock.
175 * Returned values are 0-359 degrees on success, negative
176 * error codes on failure.
177 *
178 * @set_phase: Shift the phase this clock signal in degrees specified
179 * by the second argument. Valid values for degrees are
180 * 0-359. Return 0 on success, otherwise -EERROR.
181 *
182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183 * of a clock. Returned values denominator cannot be 0 and must be
184 * superior or equal to the numerator.
185 *
186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187 * the numerator (2nd argurment) and denominator (3rd argument).
188 * Argument must be a valid ratio (denominator > 0
189 * and >= numerator) Return 0 on success, otherwise -EERROR.
190 *
191 * @init: Perform platform-specific initialization magic.
192 * This is not used by any of the basic clock types.
193 * This callback exist for HW which needs to perform some
194 * initialisation magic for CCF to get an accurate view of the
195 * clock. It may also be used dynamic resource allocation is
196 * required. It shall not used to deal with clock parameters,
197 * such as rate or parents.
198 * Returns 0 on success, -EERROR otherwise.
199 *
200 * @terminate: Free any resource allocated by init.
201 *
202 * @debug_init: Set up type-specific debugfs entries for this clock. This
203 * is called once, after the debugfs directory entry for this
204 * clock has been created. The dentry pointer representing that
205 * directory is provided as an argument. Called with
206 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
207 *
208 *
209 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
210 * implementations to split any work between atomic (enable) and sleepable
211 * (prepare) contexts. If enabling a clock requires code that might sleep,
212 * this must be done in clk_prepare. Clock enable code that will never be
213 * called in a sleepable context may be implemented in clk_enable.
214 *
215 * Typically, drivers will call clk_prepare when a clock may be needed later
216 * (eg. when a device is opened), and clk_enable when the clock is actually
217 * required (eg. from an interrupt). Note that clk_prepare MUST have been
218 * called before clk_enable.
219 */
220 struct clk_ops {
221 int (*prepare)(struct clk_hw *hw);
222 void (*unprepare)(struct clk_hw *hw);
223 int (*is_prepared)(struct clk_hw *hw);
224 void (*unprepare_unused)(struct clk_hw *hw);
225 int (*enable)(struct clk_hw *hw);
226 void (*disable)(struct clk_hw *hw);
227 int (*is_enabled)(struct clk_hw *hw);
228 void (*disable_unused)(struct clk_hw *hw);
229 int (*save_context)(struct clk_hw *hw);
230 void (*restore_context)(struct clk_hw *hw);
231 unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate);
232 long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate);
233 int (*determine_rate)(struct clk_hw *hw, struct clk_rate_request *req);
234 int (*set_parent)(struct clk_hw *hw, u8 index);
235 u8 (*get_parent)(struct clk_hw *hw);
236 int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate);
237 int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index);
238 unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy);
239 int (*get_phase)(struct clk_hw *hw);
240 int (*set_phase)(struct clk_hw *hw, int degrees);
241 int (*get_duty_cycle)(struct clk_hw *hw, struct clk_duty *duty);
242 int (*set_duty_cycle)(struct clk_hw *hw, struct clk_duty *duty);
243 int (*init)(struct clk_hw *hw);
244 void (*terminate)(struct clk_hw *hw);
245 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
246 };
247
248 /**
249 * struct clk_parent_data - clk parent information
250 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
251 * @fw_name: parent name local to provider registering clk
252 * @name: globally unique parent name (used as a fallback)
253 * @index: parent index local to provider registering clk (if @fw_name absent)
254 */
255 struct clk_parent_data {
256 const struct clk_hw *hw;
257 const char *fw_name;
258 const char *name;
259 int index;
260 };
261
262 /**
263 * struct clk_init_data - holds init data that's common to all clocks and is
264 * shared between the clock provider and the common clock framework.
265 *
266 * @name: clock name
267 * @ops: operations this clock supports
268 * @parent_names: array of string names for all possible parents
269 * @parent_data: array of parent data for all possible parents (when some
270 * parents are external to the clk controller)
271 * @parent_hws: array of pointers to all possible parents (when all parents
272 * are internal to the clk controller)
273 * @num_parents: number of possible parents
274 * @flags: framework-level hints and quirks
275 */
276 struct clk_init_data {
277 const char *name;
278 const struct clk_ops *ops;
279 /* Only one of the following three should be assigned */
280 const char *const *parent_names;
281 const struct clk_parent_data *parent_data;
282 const struct clk_hw **parent_hws;
283 u8 num_parents;
284 unsigned long flags;
285 };
286
287 /**
288 * struct clk_hw - handle for traversing from a struct clk to its corresponding
289 * hardware-specific structure. struct clk_hw should be declared within struct
290 * clk_foo and then referenced by the struct clk instance that uses struct
291 * clk_foo's clk_ops
292 *
293 * @core: pointer to the struct clk_core instance that points back to this
294 * struct clk_hw instance
295 *
296 * @clk: pointer to the per-user struct clk instance that can be used to call
297 * into the clk API
298 *
299 * @init: pointer to struct clk_init_data that contains the init data shared
300 * with the common clock framework. This pointer will be set to NULL once
301 * a clk_register() variant is called on this clk_hw pointer.
302 */
303 struct clk_hw {
304 struct clk_core *core;
305 struct clk *clk;
306 const struct clk_init_data *init;
307 };
308
309 /*
310 * DOC: Basic clock implementations common to many platforms
311 *
312 * Each basic clock hardware type is comprised of a structure describing the
313 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
314 * unique flags for that hardware type, a registration function and an
315 * alternative macro for static initialization
316 */
317
318 /**
319 * struct clk_fixed_rate - fixed-rate clock
320 * @hw: handle between common and hardware-specific interfaces
321 * @fixed_rate: constant frequency of clock
322 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
323 * @flags: hardware specific flags
324 *
325 * Flags:
326 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
327 * instead of what's set in @fixed_accuracy.
328 */
329 struct clk_fixed_rate {
330 struct clk_hw hw;
331 unsigned long fixed_rate;
332 unsigned long fixed_accuracy;
333 unsigned long flags;
334 };
335
336 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
337
338 extern const struct clk_ops clk_fixed_rate_ops;
339 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev, struct device_node *np, const char *name,
340 const char *parent_name, const struct clk_hw *parent_hw,
341 const struct clk_parent_data *parent_data, unsigned long flags,
342 unsigned long fixed_rate, unsigned long fixed_accuracy,
343 unsigned long clk_fixed_flags);
344 struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags,
345 unsigned long fixed_rate);
346 /**
347 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
348 * framework
349 * @dev: device that is registering this clock
350 * @name: name of this clock
351 * @parent_name: name of clock's parent
352 * @flags: framework-specific flags
353 * @fixed_rate: non-adjustable clock rate
354 */
355 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
356 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (fixed_rate), 0, 0)
357 /**
358 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
359 * the clock framework
360 * @dev: device that is registering this clock
361 * @name: name of this clock
362 * @parent_hw: pointer to parent clk
363 * @flags: framework-specific flags
364 * @fixed_rate: non-adjustable clock rate
365 */
366 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, fixed_rate) \
367 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), NULL, (flags), (fixed_rate), 0, 0)
368 /**
369 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
370 * the clock framework
371 * @dev: device that is registering this clock
372 * @name: name of this clock
373 * @parent_data: parent clk data
374 * @flags: framework-specific flags
375 * @fixed_rate: non-adjustable clock rate
376 */
377 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, fixed_rate) \
378 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, (parent_data), (flags), (fixed_rate), 0, 0)
379 /**
380 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
381 * the clock framework
382 * @dev: device that is registering this clock
383 * @name: name of this clock
384 * @parent_name: name of clock's parent
385 * @flags: framework-specific flags
386 * @fixed_rate: non-adjustable clock rate
387 * @fixed_accuracy: non-adjustable clock accuracy
388 */
389 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, flags, fixed_rate, fixed_accuracy) \
390 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (fixed_rate), \
391 (fixed_accuracy), 0)
392 /**
393 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
394 * clock with the clock framework
395 * @dev: device that is registering this clock
396 * @name: name of this clock
397 * @parent_hw: pointer to parent clk
398 * @flags: framework-specific flags
399 * @fixed_rate: non-adjustable clock rate
400 * @fixed_accuracy: non-adjustable clock accuracy
401 */
402 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, parent_hw, flags, fixed_rate, fixed_accuracy) \
403 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw)NULL, NULL, (flags), (fixed_rate), \
404 (fixed_accuracy), 0)
405 /**
406 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
407 * clock with the clock framework
408 * @dev: device that is registering this clock
409 * @name: name of this clock
410 * @parent_name: name of clock's parent
411 * @flags: framework-specific flags
412 * @fixed_rate: non-adjustable clock rate
413 * @fixed_accuracy: non-adjustable clock accuracy
414 */
415 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, parent_data, flags, fixed_rate, \
416 fixed_accuracy) \
417 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, (parent_data), NULL, (flags), (fixed_rate), \
418 (fixed_accuracy), 0)
419
420 void clk_unregister_fixed_rate(struct clk *clk);
421 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
422
423 void of_fixed_clk_setup(struct device_node *np);
424
425 /**
426 * struct clk_gate - gating clock
427 *
428 * @hw: handle between common and hardware-specific interfaces
429 * @reg: register controlling gate
430 * @bit_idx: single bit controlling gate
431 * @flags: hardware-specific flags
432 * @lock: register lock
433 *
434 * Clock which can gate its output. Implements .enable & .disable
435 *
436 * Flags:
437 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
438 * enable the clock. Setting this flag does the opposite: setting the bit
439 * disable the clock and clearing it enables the clock
440 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
441 * of this register, and mask of gate bits are in higher 16-bit of this
442 * register. While setting the gate bits, higher 16-bit should also be
443 * updated to indicate changing gate bits.
444 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
445 * the gate register. Setting this flag makes the register accesses big
446 * endian.
447 */
448 struct clk_gate {
449 struct clk_hw hw;
450 void __iomem *reg;
451 u8 bit_idx;
452 u8 flags;
453 spinlock_t *lock;
454 };
455
456 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
457
458 #define CLK_GATE_SET_TO_DISABLE BIT(0)
459 #define CLK_GATE_HIWORD_MASK BIT(1)
460 #define CLK_GATE_BIG_ENDIAN BIT(2)
461
462 extern const struct clk_ops clk_gate_ops;
463 struct clk_hw *__clk_hw_register_gate(struct device *dev, struct device_node *np, const char *name,
464 const char *parent_name, const struct clk_hw *parent_hw,
465 const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg,
466 u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock);
467 struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags,
468 void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock);
469 /**
470 * clk_hw_register_gate - register a gate clock with the clock framework
471 * @dev: device that is registering this clock
472 * @name: name of this clock
473 * @parent_name: name of this clock's parent
474 * @flags: framework-specific flags for this clock
475 * @reg: register address to control gating of this clock
476 * @bit_idx: which bit in the register controls gating of this clock
477 * @clk_gate_flags: gate-specific flags for this clock
478 * @lock: shared register lock for this clock
479 */
480 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, clk_gate_flags, lock) \
481 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (reg), (bit_idx), \
482 (clk_gate_flags), (lock))
483 /**
484 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
485 * framework
486 * @dev: device that is registering this clock
487 * @name: name of this clock
488 * @parent_hw: pointer to parent clk
489 * @flags: framework-specific flags for this clock
490 * @reg: register address to control gating of this clock
491 * @bit_idx: which bit in the register controls gating of this clock
492 * @clk_gate_flags: gate-specific flags for this clock
493 * @lock: shared register lock for this clock
494 */
495 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, bit_idx, clk_gate_flags, lock) \
496 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), NULL, (flags), (reg), (bit_idx), (clk_gate_flags), \
497 (lock))
498 /**
499 * clk_hw_register_gate_parent_data - register a gate clock with the clock
500 * framework
501 * @dev: device that is registering this clock
502 * @name: name of this clock
503 * @parent_data: parent clk data
504 * @flags: framework-specific flags for this clock
505 * @reg: register address to control gating of this clock
506 * @bit_idx: which bit in the register controls gating of this clock
507 * @clk_gate_flags: gate-specific flags for this clock
508 * @lock: shared register lock for this clock
509 */
510 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, bit_idx, clk_gate_flags, lock) \
511 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), (flags), (reg), (bit_idx), \
512 (clk_gate_flags), (lock))
513 void clk_unregister_gate(struct clk *clk);
514 void clk_hw_unregister_gate(struct clk_hw *hw);
515 int clk_gate_is_enabled(struct clk_hw *hw);
516
517 struct clk_div_table {
518 unsigned int val;
519 unsigned int div;
520 };
521
522 /**
523 * struct clk_divider - adjustable divider clock
524 *
525 * @hw: handle between common and hardware-specific interfaces
526 * @reg: register containing the divider
527 * @shift: shift to the divider bit field
528 * @width: width of the divider bit field
529 * @table: array of value/divider pairs, last entry should have div = 0
530 * @lock: register lock
531 *
532 * Clock with an adjustable divider affecting its output frequency. Implements
533 * .recalc_rate, .set_rate and .round_rate
534 *
535 * Flags:
536 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
537 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
538 * the raw value read from the register, with the value of zero considered
539 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
540 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
541 * the hardware register
542 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
543 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
544 * Some hardware implementations gracefully handle this case and allow a
545 * zero divisor by not modifying their input clock
546 * (divide by one / bypass).
547 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
548 * of this register, and mask of divider bits are in higher 16-bit of this
549 * register. While setting the divider bits, higher 16-bit should also be
550 * updated to indicate changing divider bits.
551 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
552 * to the closest integer instead of the up one.
553 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
554 * not be changed by the clock framework.
555 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
556 * except when the value read from the register is zero, the divisor is
557 * 2^width of the field.
558 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
559 * for the divider register. Setting this flag makes the register accesses
560 * big endian.
561 */
562 struct clk_divider {
563 struct clk_hw hw;
564 void __iomem *reg;
565 u8 shift;
566 u8 width;
567 u8 flags;
568 unsigned long max_prate;
569 const struct clk_div_table *table;
570 spinlock_t *lock;
571 };
572
573 #define clk_div_mask(width) ((1 << (width)) - 1)
574 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
575
576 #define CLK_DIVIDER_ONE_BASED BIT(0)
577 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
578 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
579 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
580 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
581 #define CLK_DIVIDER_READ_ONLY BIT(5)
582 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
583 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
584
585 extern const struct clk_ops clk_divider_ops;
586 extern const struct clk_ops clk_divider_ro_ops;
587
588 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val,
589 const struct clk_div_table *table, unsigned long flags, unsigned long width);
590 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
591 const struct clk_div_table *table, u8 width, unsigned long flags);
592 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent, unsigned long rate, unsigned long *prate,
593 const struct clk_div_table *table, u8 width, unsigned long flags, unsigned int val);
594 int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width,
595 unsigned long flags);
596
597 struct clk_hw *__clk_hw_register_divider(struct device *dev, struct device_node *np, const char *name,
598 const char *parent_name, const struct clk_hw *parent_hw,
599 const struct clk_parent_data *parent_data, unsigned long flags,
600 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
601 const struct clk_div_table *table, spinlock_t *lock);
602 struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name,
603 unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
604 const struct clk_div_table *table, spinlock_t *lock);
605 /**
606 * clk_register_divider - register a divider clock with the clock framework
607 * @dev: device registering this clock
608 * @name: name of this clock
609 * @parent_name: name of clock's parent
610 * @flags: framework-specific flags
611 * @reg: register address to adjust divider
612 * @shift: number of bits to shift the bitfield
613 * @width: width of the bitfield
614 * @clk_divider_flags: divider-specific flags for this clock
615 * @lock: shared register lock for this clock
616 */
617 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, lock) \
618 clk_register_divider_table((dev), (name), (parent_name), (flags), (reg), (shift), (width), (clk_divider_flags), \
619 NULL, (lock))
620 /**
621 * clk_hw_register_divider - register a divider clock with the clock framework
622 * @dev: device registering this clock
623 * @name: name of this clock
624 * @parent_name: name of clock's parent
625 * @flags: framework-specific flags
626 * @reg: register address to adjust divider
627 * @shift: number of bits to shift the bitfield
628 * @width: width of the bitfield
629 * @clk_divider_flags: divider-specific flags for this clock
630 * @lock: shared register lock for this clock
631 */
632 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, lock) \
633 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (reg), (shift), (width), \
634 (clk_divider_flags), NULL, (lock))
635 /**
636 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
637 * framework
638 * @dev: device registering this clock
639 * @name: name of this clock
640 * @parent_hw: pointer to parent clk
641 * @flags: framework-specific flags
642 * @reg: register address to adjust divider
643 * @shift: number of bits to shift the bitfield
644 * @width: width of the bitfield
645 * @clk_divider_flags: divider-specific flags for this clock
646 * @lock: shared register lock for this clock
647 */
648 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, shift, width, clk_divider_flags, lock) \
649 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), NULL, (flags), (reg), (shift), (width), \
650 (clk_divider_flags), NULL, (lock))
651 /**
652 * clk_hw_register_divider_parent_data - register a divider clock with the clock
653 * framework
654 * @dev: device registering this clock
655 * @name: name of this clock
656 * @parent_data: parent clk data
657 * @flags: framework-specific flags
658 * @reg: register address to adjust divider
659 * @shift: number of bits to shift the bitfield
660 * @width: width of the bitfield
661 * @clk_divider_flags: divider-specific flags for this clock
662 * @lock: shared register lock for this clock
663 */
664 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, reg, shift, width, clk_divider_flags, lock) \
665 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, (parent_data), (flags), (reg), (shift), (width), \
666 (clk_divider_flags), NULL, (lock))
667 /**
668 * clk_hw_register_divider_table - register a table based divider clock with
669 * the clock framework
670 * @dev: device registering this clock
671 * @name: name of this clock
672 * @parent_name: name of clock's parent
673 * @flags: framework-specific flags
674 * @reg: register address to adjust divider
675 * @shift: number of bits to shift the bitfield
676 * @width: width of the bitfield
677 * @clk_divider_flags: divider-specific flags for this clock
678 * @table: array of divider/value pairs ending with a div set to 0
679 * @lock: shared register lock for this clock
680 */
681 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, table, \
682 lock) \
683 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (reg), (shift), (width), \
684 (clk_divider_flags), (table), (lock))
685 /**
686 * clk_hw_register_divider_table_parent_hw - register a table based divider
687 * clock with the clock framework
688 * @dev: device registering this clock
689 * @name: name of this clock
690 * @parent_hw: pointer to parent clk
691 * @flags: framework-specific flags
692 * @reg: register address to adjust divider
693 * @shift: number of bits to shift the bitfield
694 * @width: width of the bitfield
695 * @clk_divider_flags: divider-specific flags for this clock
696 * @table: array of divider/value pairs ending with a div set to 0
697 * @lock: shared register lock for this clock
698 */
699 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, reg, shift, width, clk_divider_flags, \
700 table, lock) \
701 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), NULL, (flags), (reg), (shift), (width), \
702 (clk_divider_flags), (table), (lock))
703 /**
704 * clk_hw_register_divider_table_parent_data - register a table based divider
705 * clock with the clock framework
706 * @dev: device registering this clock
707 * @name: name of this clock
708 * @parent_data: parent clk data
709 * @flags: framework-specific flags
710 * @reg: register address to adjust divider
711 * @shift: number of bits to shift the bitfield
712 * @width: width of the bitfield
713 * @clk_divider_flags: divider-specific flags for this clock
714 * @table: array of divider/value pairs ending with a div set to 0
715 * @lock: shared register lock for this clock
716 */
717 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, flags, reg, shift, width, clk_divider_flags, \
718 table, lock) \
719 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, (parent_data), (flags), (reg), (shift), (width), \
720 (clk_divider_flags), (table), (lock))
721
722 void clk_unregister_divider(struct clk *clk);
723 void clk_hw_unregister_divider(struct clk_hw *hw);
724
725 /**
726 * struct clk_mux - multiplexer clock
727 *
728 * @hw: handle between common and hardware-specific interfaces
729 * @reg: register controlling multiplexer
730 * @table: array of register values corresponding to the parent index
731 * @shift: shift to multiplexer bit field
732 * @mask: mask of mutliplexer bit field
733 * @flags: hardware-specific flags
734 * @lock: register lock
735 *
736 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
737 * and .recalc_rate
738 *
739 * Flags:
740 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
741 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
742 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
743 * register, and mask of mux bits are in higher 16-bit of this register.
744 * While setting the mux bits, higher 16-bit should also be updated to
745 * indicate changing mux bits.
746 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
747 * .get_parent clk_op.
748 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
749 * frequency.
750 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
751 * the mux register. Setting this flag makes the register accesses big
752 * endian.
753 */
754 struct clk_mux {
755 struct clk_hw hw;
756 void __iomem *reg;
757 u32 *table;
758 u32 mask;
759 u8 shift;
760 u8 flags;
761 spinlock_t *lock;
762 };
763
764 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
765
766 #define CLK_MUX_INDEX_ONE BIT(0)
767 #define CLK_MUX_INDEX_BIT BIT(1)
768 #define CLK_MUX_HIWORD_MASK BIT(2)
769 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
770 #define CLK_MUX_ROUND_CLOSEST BIT(4)
771 #define CLK_MUX_BIG_ENDIAN BIT(5)
772
773 extern const struct clk_ops clk_mux_ops;
774 extern const struct clk_ops clk_mux_ro_ops;
775
776 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np, const char *name, u8 num_parents,
777 const char *const *parent_names, const struct clk_hw **parent_hws,
778 const struct clk_parent_data *parent_data, unsigned long flags, void __iomem *reg,
779 u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock);
780 struct clk *clk_register_mux_table(struct device *dev, const char *name, const char *const *parent_names,
781 u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
782 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
783
784 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
785 clk_register_mux_table((dev), (name), (parent_names), (num_parents), (flags), (reg), (shift), BIT((width)) - 1, \
786 (clk_mux_flags), NULL, (lock))
787 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, table, \
788 lock) \
789 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_names), NULL, NULL, (flags), (reg), (shift), \
790 (mask), (clk_mux_flags), (table), (lock))
791 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
792 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_names), NULL, NULL, (flags), (reg), (shift), \
793 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
794 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
795 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, (parent_hws), NULL, (flags), (reg), (shift), \
796 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
797 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, flags, reg, shift, width, clk_mux_flags, \
798 lock) \
799 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, (parent_data), (flags), (reg), (shift), \
800 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
801
802 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags, unsigned int val);
803 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
804
805 void clk_unregister_mux(struct clk *clk);
806 void clk_hw_unregister_mux(struct clk_hw *hw);
807
808 void of_fixed_factor_clk_setup(struct device_node *node);
809
810 /**
811 * struct clk_fixed_factor - fixed multiplier and divider clock
812 *
813 * @hw: handle between common and hardware-specific interfaces
814 * @mult: multiplier
815 * @div: divider
816 *
817 * Clock with a fixed multiplier and divider. The output frequency is the
818 * parent clock rate divided by div and multiplied by mult.
819 * Implements .recalc_rate, .set_rate and .round_rate
820 */
821
822 struct clk_fixed_factor {
823 struct clk_hw hw;
824 unsigned int mult;
825 unsigned int div;
826 };
827
828 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
829
830 extern const struct clk_ops clk_fixed_factor_ops;
831 struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name,
832 unsigned long flags, unsigned int mult, unsigned int div);
833 void clk_unregister_fixed_factor(struct clk *clk);
834 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name,
835 unsigned long flags, unsigned int mult, unsigned int div);
836 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
837
838 /**
839 * struct clk_fractional_divider - adjustable fractional divider clock
840 *
841 * @hw: handle between common and hardware-specific interfaces
842 * @reg: register containing the divider
843 * @mshift: shift to the numerator bit field
844 * @mwidth: width of the numerator bit field
845 * @nshift: shift to the denominator bit field
846 * @nwidth: width of the denominator bit field
847 * @lock: register lock
848 *
849 * Clock with adjustable fractional divider affecting its output frequency.
850 *
851 * Flags:
852 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
853 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
854 * is set then the numerator and denominator are both the value read
855 * plus one.
856 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
857 * used for the divider register. Setting this flag makes the register
858 * accesses big endian.
859 * CLK_FRAC_DIVIDER_NO_LIMIT - not need to follow the 20 times limit on
860 * fractional divider
861 */
862 struct clk_fractional_divider {
863 struct clk_hw hw;
864 void __iomem *reg;
865 u8 mshift;
866 u8 mwidth;
867 u32 mmask;
868 u8 nshift;
869 u8 nwidth;
870 u32 nmask;
871 u8 flags;
872 unsigned long max_prate;
873 void (*approximation)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate, unsigned long *m,
874 unsigned long *n);
875 spinlock_t *lock;
876 };
877
878 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
879
880 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
881 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
882 #define CLK_FRAC_DIVIDER_NO_LIMIT BIT(2)
883
884 extern const struct clk_ops clk_fractional_divider_ops;
885 struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name,
886 unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift,
887 u8 nwidth, u8 clk_divider_flags, spinlock_t *lock);
888 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev, const char *name, const char *parent_name,
889 unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth,
890 u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock);
891 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
892
893 /**
894 * struct clk_multiplier - adjustable multiplier clock
895 *
896 * @hw: handle between common and hardware-specific interfaces
897 * @reg: register containing the multiplier
898 * @shift: shift to the multiplier bit field
899 * @width: width of the multiplier bit field
900 * @lock: register lock
901 *
902 * Clock with an adjustable multiplier affecting its output frequency.
903 * Implements .recalc_rate, .set_rate and .round_rate
904 *
905 * Flags:
906 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
907 * from the register, with 0 being a valid value effectively
908 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
909 * set, then a null multiplier will be considered as a bypass,
910 * leaving the parent rate unmodified.
911 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
912 * rounded to the closest integer instead of the down one.
913 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
914 * used for the multiplier register. Setting this flag makes the register
915 * accesses big endian.
916 */
917 struct clk_multiplier {
918 struct clk_hw hw;
919 void __iomem *reg;
920 u8 shift;
921 u8 width;
922 u8 flags;
923 spinlock_t *lock;
924 };
925
926 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
927
928 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
929 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
930 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
931
932 extern const struct clk_ops clk_multiplier_ops;
933
934 /***
935 * struct clk_composite - aggregate clock of mux, divider and gate clocks
936 *
937 * @hw: handle between common and hardware-specific interfaces
938 * @mux_hw: handle between composite and hardware-specific mux clock
939 * @rate_hw: handle between composite and hardware-specific rate clock
940 * @gate_hw: handle between composite and hardware-specific gate clock
941 * @brother_hw: a member of clk_composite who has the common parent clocks
942 * with another clk_composite, and it's also a handle between
943 * common and hardware-specific interfaces
944 * @mux_ops: clock ops for mux
945 * @rate_ops: clock ops for rate
946 * @gate_ops: clock ops for gate
947 */
948 struct clk_composite {
949 struct clk_hw hw;
950 struct clk_ops ops;
951
952 struct clk_hw *mux_hw;
953 struct clk_hw *rate_hw;
954 struct clk_hw *gate_hw;
955 struct clk_hw *brother_hw;
956
957 const struct clk_ops *mux_ops;
958 const struct clk_ops *rate_ops;
959 const struct clk_ops *gate_ops;
960 };
961
962 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
963
964 struct clk *clk_register_composite(struct device *dev, const char *name, const char *const *parent_names,
965 int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
966 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw,
967 const struct clk_ops *gate_ops, unsigned long flags);
968 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
969 const struct clk_parent_data *parent_data, int num_parents,
970 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, struct clk_hw *rate_hw,
971 const struct clk_ops *rate_ops, struct clk_hw *gate_hw,
972 const struct clk_ops *gate_ops, unsigned long flags);
973 void clk_unregister_composite(struct clk *clk);
974 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name, const char *const *parent_names,
975 int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
976 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, struct clk_hw *gate_hw,
977 const struct clk_ops *gate_ops, unsigned long flags);
978 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev, const char *name,
979 const struct clk_parent_data *parent_data, int num_parents,
980 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
981 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
982 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
983 unsigned long flags);
984 void clk_hw_unregister_composite(struct clk_hw *hw);
985
986 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
987 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
988
989 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
990 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
991 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
992
993 void clk_unregister(struct clk *clk);
994 void devm_clk_unregister(struct device *dev, struct clk *clk);
995
996 void clk_hw_unregister(struct clk_hw *hw);
997 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
998
999 /* helper functions */
1000 const char *__clk_get_name(const struct clk *clk);
1001 const char *clk_hw_get_name(const struct clk_hw *hw);
1002 #ifdef CONFIG_COMMON_CLK
1003 struct clk_hw *__clk_get_hw(struct clk *clk);
1004 #else
__clk_get_hw(struct clk * clk)1005 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1006 {
1007 return (struct clk_hw *)clk;
1008 }
1009 #endif
1010 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1011 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1012 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index);
1013 int clk_hw_get_parent_index(struct clk_hw *hw);
1014 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1015 unsigned int __clk_get_enable_count(struct clk *clk);
1016 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1017 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1018 #define clk_hw_can_set_rate_parent(hw) (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1019
1020 bool clk_hw_is_prepared(const struct clk_hw *hw);
1021 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1022 bool clk_hw_is_enabled(const struct clk_hw *hw);
1023 bool __clk_is_enabled(struct clk *clk);
1024 struct clk *__clk_lookup(const char *name);
1025 int __clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req);
1026 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1027 int __clk_mux_determine_rate_closest(struct clk_hw *hw, struct clk_rate_request *req);
1028 int clk_mux_determine_rate_flags(struct clk_hw *hw, struct clk_rate_request *req, unsigned long flags);
1029 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1030 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate);
1031
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1032 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1033 {
1034 dst->clk = src->clk;
1035 dst->core = src->core;
1036 }
1037
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1038 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate,
1039 const struct clk_div_table *table, u8 width, unsigned long flags)
1040 {
1041 return divider_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags);
1042 }
1043
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1044 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate,
1045 const struct clk_div_table *table, u8 width, unsigned long flags,
1046 unsigned int val)
1047 {
1048 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw), rate, prate, table, width, flags, val);
1049 }
1050
1051 /*
1052 * clock api without lock protection
1053 */
1054 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1055
1056 struct clk_onecell_data {
1057 struct clk **clks;
1058 unsigned int clk_num;
1059 };
1060
1061 struct clk_hw_onecell_data {
1062 unsigned int num;
1063 struct clk_hw *hws[];
1064 };
1065
1066 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1067
1068 /*
1069 * Use this macro when you have a driver that requires two initialization
1070 * routines, one at of_clk_init(), and one at platform device probe
1071 */
1072 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1073 static void __init name##_of_clk_init_driver(struct device_node *np) \
1074 { \
1075 of_node_clear_flag(np, OF_POPULATED); \
1076 fn(np); \
1077 } \
1078 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1079
1080 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1081 (&(struct clk_init_data) { \
1082 .flags = (_flags), \
1083 .name = (_name), \
1084 .parent_names = (const char *[]) {_parent}, \
1085 .num_parents = 1, \
1086 .ops = (_ops), \
1087 })
1088
1089 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1090 (&(struct clk_init_data) { \
1091 .flags = (_flags), \
1092 .name = (_name), \
1093 .parent_hws = (const struct clk_hw *[]) {_parent}, \
1094 .num_parents = 1, \
1095 .ops = (_ops), \
1096 })
1097
1098 /*
1099 * This macro is intended for drivers to be able to share the otherwise
1100 * individual struct clk_hw[] compound literals created by the compiler
1101 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1102 */
1103 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1104 (&(struct clk_init_data) { \
1105 .flags = (_flags), \
1106 .name = (_name), \
1107 .parent_hws = (_parent), \
1108 .num_parents = 1, \
1109 .ops = (_ops), \
1110 })
1111
1112 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1113 (&(struct clk_init_data) { \
1114 .flags = (_flags), \
1115 .name = (_name), \
1116 .parent_data = \
1117 (const struct clk_parent_data[]) { \
1118 {.fw_name = _parent}, \
1119 }, \
1120 .num_parents = 1, \
1121 .ops = (_ops), \
1122 })
1123
1124 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1125 (&(struct clk_init_data) { \
1126 .flags = (_flags), \
1127 .name = (_name), \
1128 .parent_names = (_parents), \
1129 .num_parents = ARRAY_SIZE(_parents), \
1130 .ops = (_ops), \
1131 })
1132
1133 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1134 (&(struct clk_init_data) { \
1135 .flags = (_flags), \
1136 .name = (_name), \
1137 .parent_hws = (_parents), \
1138 .num_parents = ARRAY_SIZE(_parents), \
1139 .ops = (_ops), \
1140 })
1141
1142 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1143 (&(struct clk_init_data) { \
1144 .flags = (_flags), \
1145 .name = (_name), \
1146 .parent_data = (_parents), \
1147 .num_parents = ARRAY_SIZE(_parents), \
1148 .ops = (_ops), \
1149 })
1150
1151 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1152 (&(struct clk_init_data) { \
1153 .flags = (_flags), \
1154 .name = (_name), \
1155 .parent_names = NULL, \
1156 .num_parents = 0, \
1157 .ops = (_ops), \
1158 })
1159
1160 #define CLK_FIXED_FACTOR(_struct, _name, _parent, _div, _mult, _flags) \
1161 struct clk_fixed_factor _struct = { \
1162 .div = (_div), \
1163 .mult = (_mult), \
1164 .hw.init = CLK_HW_INIT(_name, _parent, &clk_fixed_factor_ops, _flags), \
1165 }
1166
1167 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, _div, _mult, _flags) \
1168 struct clk_fixed_factor _struct = { \
1169 .div = (_div), \
1170 .mult = _mult, \
1171 .hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_fixed_factor_ops, _flags), \
1172 }
1173
1174 /*
1175 * This macro allows the driver to reuse the _parent array for multiple
1176 * fixed factor clk declarations.
1177 */
1178 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, _div, _mult, _flags) \
1179 struct clk_fixed_factor _struct = { \
1180 .div = (_div), \
1181 .mult = (_mult), \
1182 .hw.init = CLK_HW_INIT_HWS(_name, _parent, &clk_fixed_factor_ops, _flags), \
1183 }
1184
1185 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, _div, _mult, _flags) \
1186 struct clk_fixed_factor _struct = { \
1187 .div = (_div), \
1188 .mult = (_mult), \
1189 .hw.init = CLK_HW_INIT_FW_NAME(_name, _parent, &clk_fixed_factor_ops, _flags), \
1190 }
1191
1192 #ifdef CONFIG_OF
1193 int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data),
1194 void *data);
1195 int of_clk_add_hw_provider(struct device_node *np, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data),
1196 void *data);
1197 int devm_of_clk_add_hw_provider(struct device *dev, struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data),
1198 void *data);
1199 void of_clk_del_provider(struct device_node *np);
1200 void devm_of_clk_del_provider(struct device *dev);
1201 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data);
1202 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data);
1203 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1204 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data);
1205 int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size);
1206 int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags);
1207
1208 #else /* !CONFIG_OF */
1209
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1210 static inline int of_clk_add_provider(struct device_node *np,
1211 struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data)
1212 {
1213 return 0;
1214 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1215 static inline int of_clk_add_hw_provider(struct device_node *np,
1216 struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data), void *data)
1217 {
1218 return 0;
1219 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1220 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1221 struct clk_hw *(*get)(struct of_phandle_args *clkspec, void *data),
1222 void *data)
1223 {
1224 return 0;
1225 }
of_clk_del_provider(struct device_node * np)1226 static inline void of_clk_del_provider(struct device_node *np)
1227 {
1228 }
devm_of_clk_del_provider(struct device * dev)1229 static inline void devm_of_clk_del_provider(struct device *dev)
1230 {
1231 }
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1232 static inline struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data)
1233 {
1234 return ERR_PTR(-ENOENT);
1235 }
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1236 static inline struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1237 {
1238 return ERR_PTR(-ENOENT);
1239 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1240 static inline struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
1241 {
1242 return ERR_PTR(-ENOENT);
1243 }
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1244 static inline struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1245 {
1246 return ERR_PTR(-ENOENT);
1247 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1248 static inline int of_clk_parent_fill(struct device_node *np, const char **parents, unsigned int size)
1249 {
1250 return 0;
1251 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1252 static inline int of_clk_detect_critical(struct device_node *np, int index, unsigned long *flags)
1253 {
1254 return 0;
1255 }
1256 #endif /* CONFIG_OF */
1257
1258 void clk_gate_restore_context(struct clk_hw *hw);
1259
1260 #endif /* CLK_PROVIDER_H */
1261