1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __INC_PHYDM_BEAMFORMING_H 27 #define __INC_PHYDM_BEAMFORMING_H 28 29 /*@Beamforming Related*/ 30 #include "txbf/halcomtxbf.h" 31 #include "txbf/haltxbfjaguar.h" 32 #include "txbf/haltxbf8192e.h" 33 #include "txbf/haltxbf8814a.h" 34 #include "txbf/haltxbf8822b.h" 35 #include "txbf/haltxbfinterface.h" 36 37 #ifdef PHYDM_BEAMFORMING_SUPPORT 38 39 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 40 41 #define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) 42 #define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) 43 44 #endif 45 46 #define MAX_BEAMFORMEE_SU 2 47 #define MAX_BEAMFORMER_SU 2 48 #if ((RTL8822B_SUPPORT == 1) || (RTL8812F_SUPPORT == 1)) 49 #define MAX_BEAMFORMEE_MU 6 50 #define MAX_BEAMFORMER_MU 1 51 #else 52 #define MAX_BEAMFORMEE_MU 0 53 #define MAX_BEAMFORMER_MU 0 54 #endif 55 56 #define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) 57 #define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) 58 59 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 60 /*@for different naming between WIN and CE*/ 61 #define BEACON_QUEUE BCN_QUEUE_INX 62 #define NORMAL_QUEUE MGT_QUEUE_INX 63 #define RT_DISABLE_FUNC RTW_DISABLE_FUNC 64 #define RT_ENABLE_FUNC RTW_ENABLE_FUNC 65 #endif 66 67 enum beamforming_entry_state { 68 BEAMFORMING_ENTRY_STATE_UNINITIALIZE, 69 BEAMFORMING_ENTRY_STATE_INITIALIZEING, 70 BEAMFORMING_ENTRY_STATE_INITIALIZED, 71 BEAMFORMING_ENTRY_STATE_PROGRESSING, 72 BEAMFORMING_ENTRY_STATE_PROGRESSED 73 }; 74 75 enum beamforming_notify_state { 76 BEAMFORMING_NOTIFY_NONE, 77 BEAMFORMING_NOTIFY_ADD, 78 BEAMFORMING_NOTIFY_DELETE, 79 BEAMFORMEE_NOTIFY_ADD_SU, 80 BEAMFORMEE_NOTIFY_DELETE_SU, 81 BEAMFORMEE_NOTIFY_ADD_MU, 82 BEAMFORMEE_NOTIFY_DELETE_MU, 83 BEAMFORMING_NOTIFY_RESET 84 }; 85 86 enum beamforming_cap { 87 BEAMFORMING_CAP_NONE = 0x0, 88 BEAMFORMER_CAP_HT_EXPLICIT = BIT(1), 89 BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2), 90 BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er & peer ee */ 91 BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */ 92 BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er & peer ee */ 93 BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */ 94 BEAMFORMER_CAP = BIT(9), 95 BEAMFORMEE_CAP = BIT(10), 96 }; 97 98 enum sounding_mode { 99 SOUNDING_SW_VHT_TIMER = 0x0, 100 SOUNDING_SW_HT_TIMER = 0x1, 101 sounding_stop_all_timer = 0x2, 102 SOUNDING_HW_VHT_TIMER = 0x3, 103 SOUNDING_HW_HT_TIMER = 0x4, 104 SOUNDING_STOP_OID_TIMER = 0x5, 105 SOUNDING_AUTO_VHT_TIMER = 0x6, 106 SOUNDING_AUTO_HT_TIMER = 0x7, 107 SOUNDING_FW_VHT_TIMER = 0x8, 108 SOUNDING_FW_HT_TIMER = 0x9, 109 }; 110 111 struct _RT_BEAMFORM_STAINFO { 112 u8 *ra; 113 u16 aid; 114 u16 mac_id; 115 u8 my_mac_addr[6]; 116 /*WIRELESS_MODE wireless_mode;*/ 117 enum channel_width bw; 118 enum beamforming_cap beamform_cap; 119 u8 ht_beamform_cap; 120 u16 vht_beamform_cap; 121 u8 cur_beamform; 122 u16 cur_beamform_vht; 123 }; 124 125 struct _RT_BEAMFORMEE_ENTRY { 126 boolean is_used; 127 boolean is_txbf; 128 boolean is_sound; 129 u16 aid; /*Used to construct AID field of NDPA packet.*/ 130 u16 mac_id; /*Used to Set Reg42C in IBSS mode. */ 131 u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ 132 u8 g_id; /*Used to fill Tx DESC*/ 133 u8 my_mac_addr[6]; 134 u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ 135 enum channel_width sound_bw; /*Sounding band_width*/ 136 u16 sound_period; 137 enum beamforming_cap beamform_entry_cap; 138 enum beamforming_entry_state beamform_entry_state; 139 boolean is_beamforming_in_progress; 140 /*@u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/ 141 /*@u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ 142 /*@u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ 143 u16 log_status_fail_cnt : 5; /* @0~21 */ 144 u16 default_csi_cnt : 5; /* @0~21 */ 145 u8 csi_matrix[327]; 146 u16 csi_matrix_len; 147 u8 num_of_sounding_dim; 148 u8 comp_steering_num_of_bfer; 149 u8 su_reg_index; 150 /*@For MU-MIMO*/ 151 boolean is_mu_sta; 152 u8 mu_reg_index; 153 u8 gid_valid[8]; 154 u8 user_position[16]; 155 }; 156 157 struct _RT_BEAMFORMER_ENTRY { 158 boolean is_used; 159 /*P_AID of BFer entry is probably not used*/ 160 u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ 161 u8 g_id; 162 u8 my_mac_addr[6]; 163 u8 mac_addr[6]; 164 enum beamforming_cap beamform_entry_cap; 165 u8 num_of_sounding_dim; 166 u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/ 167 u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/ 168 u8 log_seq; /*@Modified by Jeffery @2014-10-29*/ 169 u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/ 170 u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/ 171 u8 su_reg_index; 172 /*@For MU-MIMO*/ 173 boolean is_mu_ap; 174 u8 gid_valid[8]; 175 u8 user_position[16]; 176 u16 aid; 177 }; 178 179 struct _RT_SOUNDING_INFO { 180 u8 sound_idx; 181 enum channel_width sound_bw; 182 enum sounding_mode sound_mode; 183 u16 sound_period; 184 }; 185 186 struct _RT_BEAMFORMING_OID_INFO { 187 u8 sound_oid_idx; 188 enum channel_width sound_oid_bw; 189 enum sounding_mode sound_oid_mode; 190 u16 sound_oid_period; 191 }; 192 193 struct _RT_BEAMFORMING_INFO { 194 enum beamforming_cap beamform_cap; 195 struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM]; 196 struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM]; 197 struct _RT_BEAMFORM_STAINFO beamform_sta_info; 198 u8 beamformee_cur_idx; 199 struct phydm_timer_list beamforming_timer; 200 struct phydm_timer_list mu_timer; 201 struct _RT_SOUNDING_INFO sounding_info; 202 struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info; 203 struct _HAL_TXBF_INFO txbf_info; 204 u8 sounding_sequence; 205 u8 beamformee_su_cnt; 206 u8 beamformer_su_cnt; 207 u32 beamformee_su_reg_maping; 208 u32 beamformer_su_reg_maping; 209 /*@For MU-MINO*/ 210 u8 beamformee_mu_cnt; 211 u8 beamformer_mu_cnt; 212 u32 beamformee_mu_reg_maping; 213 u8 mu_ap_index; 214 boolean is_mu_sounding; 215 u8 first_mu_bfee_index; 216 boolean is_mu_sounding_in_progress; 217 boolean dbg_disable_mu_tx; 218 boolean apply_v_matrix; 219 boolean snding3ss; 220 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 221 void *source_adapter; 222 #endif 223 /* @Control register */ 224 u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */ 225 u8 tx_bf_data_rate; 226 u8 last_usb_hub; 227 }; 228 229 void phydm_get_txbf_device_num( 230 void *dm_void, 231 u8 macid); 232 233 struct _RT_NDPA_STA_INFO { 234 u16 aid : 12; 235 u16 feedback_type : 1; 236 u16 nc_index : 3; 237 }; 238 239 enum phydm_acting_type { 240 phydm_acting_as_ibss = 0, 241 phydm_acting_as_ap = 1 242 }; 243 244 enum beamforming_cap 245 phydm_beamforming_get_entry_beam_cap_by_mac_id( 246 void *dm_void, 247 u8 mac_id); 248 249 struct _RT_BEAMFORMEE_ENTRY * 250 phydm_beamforming_get_bfee_entry_by_addr( 251 void *dm_void, 252 u8 *RA, 253 u8 *idx); 254 255 struct _RT_BEAMFORMER_ENTRY * 256 phydm_beamforming_get_bfer_entry_by_addr( 257 void *dm_void, 258 u8 *TA, 259 u8 *idx); 260 261 void phydm_beamforming_notify( 262 void *dm_void); 263 264 boolean 265 phydm_acting_determine( 266 void *dm_void, 267 enum phydm_acting_type type); 268 269 void beamforming_enter(void *dm_void, u16 sta_idx, u8 *my_mac_addr); 270 271 void beamforming_leave( 272 void *dm_void, 273 u8 *RA); 274 275 boolean 276 beamforming_start_fw( 277 void *dm_void, 278 u8 idx); 279 280 void beamforming_check_sounding_success( 281 void *dm_void, 282 boolean status); 283 284 void phydm_beamforming_end_sw( 285 void *dm_void, 286 boolean status); 287 288 void beamforming_timer_callback( 289 void *dm_void); 290 291 void phydm_beamforming_init( 292 void *dm_void); 293 294 enum beamforming_cap 295 phydm_beamforming_get_beam_cap( 296 void *dm_void, 297 struct _RT_BEAMFORMING_INFO *beam_info); 298 299 enum beamforming_cap 300 phydm_get_beamform_cap( 301 void *dm_void); 302 303 boolean 304 beamforming_control_v1( 305 void *dm_void, 306 u8 *RA, 307 u8 AID, 308 u8 mode, 309 enum channel_width BW, 310 u8 rate); 311 312 boolean 313 phydm_beamforming_control_v2( 314 void *dm_void, 315 u8 idx, 316 u8 mode, 317 enum channel_width BW, 318 u16 period); 319 320 void phydm_beamforming_watchdog( 321 void *dm_void); 322 323 void beamforming_sw_timer_callback( 324 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 325 struct phydm_timer_list *timer 326 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) 327 void *function_context 328 #endif 329 ); 330 331 boolean 332 beamforming_send_ht_ndpa_packet( 333 void *dm_void, 334 u8 *RA, 335 enum channel_width BW, 336 u8 q_idx); 337 338 boolean 339 beamforming_send_vht_ndpa_packet( 340 void *dm_void, 341 u8 *RA, 342 u16 AID, 343 enum channel_width BW, 344 u8 q_idx); 345 346 #else 347 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP)) 348 #define beamforming_gid_paid(adapter, tcb) 349 #define phydm_acting_determine(dm, type) false 350 #define beamforming_enter(dm, sta_idx, my_mac_addr) 351 #define beamforming_leave(dm, RA) 352 #define beamforming_end_fw(dm) 353 #define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true 354 #define beamforming_control_v2(dm, idx, mode, BW, period) true 355 #define phydm_beamforming_end_sw(dm, _status) 356 #define beamforming_timer_callback(dm) 357 #define phydm_beamforming_init(dm) 358 #define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false 359 #define beamforming_watchdog(dm) 360 #define phydm_beamforming_watchdog(dm) 361 #endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/ 362 #endif /*@#ifdef PHYDM_BEAMFORMING_SUPPORT*/ 363 #endif 364