1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_PCNT_STRUCT_H_ 15 #define _SOC_PCNT_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct pcnt_dev_s { 24 struct{ 25 union { 26 struct { 27 uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/ 28 uint32_t filter_en: 1; /*This is the enable bit for filtering input signals for unit0.*/ 29 uint32_t thr_zero_en: 1; /*This is the enable bit for comparing unit0's count with 0 value.*/ 30 uint32_t thr_h_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_h_lim value.*/ 31 uint32_t thr_l_lim_en: 1; /*This is the enable bit for comparing unit0's count with thr_l_lim value.*/ 32 uint32_t thr_thres0_en: 1; /*This is the enable bit for comparing unit0's count with thres0 value.*/ 33 uint32_t thr_thres1_en: 1; /*This is the enable bit for comparing unit0's count with thres1 value .*/ 34 uint32_t ch0_neg_mode: 2; /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ 35 uint32_t ch0_pos_mode: 2; /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ 36 uint32_t ch0_hctrl_mode: 2; /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ 37 uint32_t ch0_lctrl_mode: 2; /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ 38 uint32_t ch1_neg_mode: 2; /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden*/ 39 uint32_t ch1_pos_mode: 2; /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden*/ 40 uint32_t ch1_hctrl_mode: 2; /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ 41 uint32_t ch1_lctrl_mode: 2; /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1：decrease when control signal is high others:forbidden*/ 42 }; 43 uint32_t val; 44 } conf0; 45 union { 46 struct { 47 uint32_t cnt_thres0:16; /*This register is used to configure thres0 value for unit0.*/ 48 uint32_t cnt_thres1:16; /*This register is used to configure thres1 value for unit0.*/ 49 }; 50 uint32_t val; 51 } conf1; 52 union { 53 struct { 54 uint32_t cnt_h_lim:16; /*This register is used to configure thr_h_lim value for unit0.*/ 55 uint32_t cnt_l_lim:16; /*This register is used to configure thr_l_lim value for unit0.*/ 56 }; 57 uint32_t val; 58 } conf2; 59 } conf_unit[8]; 60 union { 61 struct { 62 uint32_t cnt_val : 16; /*This register stores the current pulse count value for unit0.*/ 63 uint32_t reserved16: 16; 64 }; 65 uint32_t val; 66 } cnt_unit[8]; 67 union { 68 struct { 69 uint32_t cnt_thr_event_u0: 1; /*This is the interrupt raw bit for channel0 event.*/ 70 uint32_t cnt_thr_event_u1: 1; /*This is the interrupt raw bit for channel1 event.*/ 71 uint32_t cnt_thr_event_u2: 1; /*This is the interrupt raw bit for channel2 event.*/ 72 uint32_t cnt_thr_event_u3: 1; /*This is the interrupt raw bit for channel3 event.*/ 73 uint32_t cnt_thr_event_u4: 1; /*This is the interrupt raw bit for channel4 event.*/ 74 uint32_t cnt_thr_event_u5: 1; /*This is the interrupt raw bit for channel5 event.*/ 75 uint32_t cnt_thr_event_u6: 1; /*This is the interrupt raw bit for channel6 event.*/ 76 uint32_t cnt_thr_event_u7: 1; /*This is the interrupt raw bit for channel7 event.*/ 77 uint32_t reserved8: 24; 78 }; 79 uint32_t val; 80 } int_raw; 81 union { 82 struct { 83 uint32_t cnt_thr_event_u0: 1; /*This is the interrupt status bit for channel0 event.*/ 84 uint32_t cnt_thr_event_u1: 1; /*This is the interrupt status bit for channel1 event.*/ 85 uint32_t cnt_thr_event_u2: 1; /*This is the interrupt status bit for channel2 event.*/ 86 uint32_t cnt_thr_event_u3: 1; /*This is the interrupt status bit for channel3 event.*/ 87 uint32_t cnt_thr_event_u4: 1; /*This is the interrupt status bit for channel4 event.*/ 88 uint32_t cnt_thr_event_u5: 1; /*This is the interrupt status bit for channel5 event.*/ 89 uint32_t cnt_thr_event_u6: 1; /*This is the interrupt status bit for channel6 event.*/ 90 uint32_t cnt_thr_event_u7: 1; /*This is the interrupt status bit for channel7 event.*/ 91 uint32_t reserved8: 24; 92 }; 93 uint32_t val; 94 } int_st; 95 union { 96 struct { 97 uint32_t cnt_thr_event_u0: 1; /*This is the interrupt enable bit for channel0 event.*/ 98 uint32_t cnt_thr_event_u1: 1; /*This is the interrupt enable bit for channel1 event.*/ 99 uint32_t cnt_thr_event_u2: 1; /*This is the interrupt enable bit for channel2 event.*/ 100 uint32_t cnt_thr_event_u3: 1; /*This is the interrupt enable bit for channel3 event.*/ 101 uint32_t cnt_thr_event_u4: 1; /*This is the interrupt enable bit for channel4 event.*/ 102 uint32_t cnt_thr_event_u5: 1; /*This is the interrupt enable bit for channel5 event.*/ 103 uint32_t cnt_thr_event_u6: 1; /*This is the interrupt enable bit for channel6 event.*/ 104 uint32_t cnt_thr_event_u7: 1; /*This is the interrupt enable bit for channel7 event.*/ 105 uint32_t reserved8: 24; 106 }; 107 uint32_t val; 108 } int_ena; 109 union { 110 struct { 111 uint32_t cnt_thr_event_u0: 1; /*Set this bit to clear channel0 event interrupt.*/ 112 uint32_t cnt_thr_event_u1: 1; /*Set this bit to clear channel1 event interrupt.*/ 113 uint32_t cnt_thr_event_u2: 1; /*Set this bit to clear channel2 event interrupt.*/ 114 uint32_t cnt_thr_event_u3: 1; /*Set this bit to clear channel3 event interrupt.*/ 115 uint32_t cnt_thr_event_u4: 1; /*Set this bit to clear channel4 event interrupt.*/ 116 uint32_t cnt_thr_event_u5: 1; /*Set this bit to clear channel5 event interrupt.*/ 117 uint32_t cnt_thr_event_u6: 1; /*Set this bit to clear channel6 event interrupt.*/ 118 uint32_t cnt_thr_event_u7: 1; /*Set this bit to clear channel7 event interrupt.*/ 119 uint32_t reserved8: 24; 120 }; 121 uint32_t val; 122 } int_clr; 123 union { 124 struct { 125 uint32_t cnt_mode:2; /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/ 126 uint32_t thres1_lat:1; /* counter value equals to thresh1*/ 127 uint32_t thres0_lat:1; /* counter value equals to thresh0*/ 128 uint32_t l_lim_lat:1; /* counter value reaches h_lim*/ 129 uint32_t h_lim_lat:1; /* counter value reaches l_lim*/ 130 uint32_t zero_lat:1; /* counter value equals zero*/ 131 uint32_t reserved7:25; 132 }; 133 uint32_t val; 134 } status_unit[8]; 135 union { 136 struct { 137 uint32_t cnt_rst_u0: 1; /*Set this bit to clear unit0's counter.*/ 138 uint32_t cnt_pause_u0: 1; /*Set this bit to pause unit0's counter.*/ 139 uint32_t cnt_rst_u1: 1; /*Set this bit to clear unit1's counter.*/ 140 uint32_t cnt_pause_u1: 1; /*Set this bit to pause unit1's counter.*/ 141 uint32_t cnt_rst_u2: 1; /*Set this bit to clear unit2's counter.*/ 142 uint32_t cnt_pause_u2: 1; /*Set this bit to pause unit2's counter.*/ 143 uint32_t cnt_rst_u3: 1; /*Set this bit to clear unit3's counter.*/ 144 uint32_t cnt_pause_u3: 1; /*Set this bit to pause unit3's counter.*/ 145 uint32_t cnt_rst_u4: 1; /*Set this bit to clear unit4's counter.*/ 146 uint32_t cnt_pause_u4: 1; /*Set this bit to pause unit4's counter.*/ 147 uint32_t cnt_rst_u5: 1; /*Set this bit to clear unit5's counter.*/ 148 uint32_t cnt_pause_u5: 1; /*Set this bit to pause unit5's counter.*/ 149 uint32_t cnt_rst_u6: 1; /*Set this bit to clear unit6's counter.*/ 150 uint32_t cnt_pause_u6: 1; /*Set this bit to pause unit6's counter.*/ 151 uint32_t cnt_rst_u7: 1; /*Set this bit to clear unit7's counter.*/ 152 uint32_t cnt_pause_u7: 1; /*Set this bit to pause unit7's counter.*/ 153 uint32_t clk_en: 1; 154 uint32_t reserved17: 15; 155 }; 156 uint32_t val; 157 } ctrl; 158 uint32_t reserved_b4; 159 uint32_t reserved_b8; 160 uint32_t reserved_bc; 161 uint32_t reserved_c0; 162 uint32_t reserved_c4; 163 uint32_t reserved_c8; 164 uint32_t reserved_cc; 165 uint32_t reserved_d0; 166 uint32_t reserved_d4; 167 uint32_t reserved_d8; 168 uint32_t reserved_dc; 169 uint32_t reserved_e0; 170 uint32_t reserved_e4; 171 uint32_t reserved_e8; 172 uint32_t reserved_ec; 173 uint32_t reserved_f0; 174 uint32_t reserved_f4; 175 uint32_t reserved_f8; 176 uint32_t date; /**/ 177 } pcnt_dev_t; 178 extern pcnt_dev_t PCNT; 179 180 #ifdef __cplusplus 181 } 182 #endif 183 184 #endif /* _SOC_PCNT_STRUCT_H_ */ 185