1 /**********************************************************
2 * Copyright 2011 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_format.h"
28 #include "util/u_debug.h"
29 #include "util/format/u_format.h"
30 #include "util/u_memory.h"
31
32 #include "svga_winsys.h"
33 #include "svga_screen.h"
34 #include "svga_format.h"
35
36
37 /** Describes mapping from gallium formats to SVGA vertex/pixel formats */
38 struct vgpu10_format_entry
39 {
40 SVGA3dSurfaceFormat vertex_format;
41 SVGA3dSurfaceFormat pixel_format;
42 SVGA3dSurfaceFormat view_format; /* view format for texture buffer */
43 unsigned flags;
44 };
45
46 struct format_compat_entry
47 {
48 enum pipe_format pformat;
49 const SVGA3dSurfaceFormat *compat_format;
50 };
51
52
53 /**
54 * Table mapping Gallium formats to SVGA3d vertex/pixel formats.
55 * Note: the table is ordered according to PIPE_FORMAT_x order.
56 */
57 static const struct vgpu10_format_entry format_conversion_table[] =
58 {
59 /* Gallium format SVGA3D vertex format SVGA3D pixel format SVGA3D texbuf view format Flags */
60 [ PIPE_FORMAT_B8G8R8A8_UNORM ] = { SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, SVGA3D_B8G8R8A8_UNORM, TF_GEN_MIPS },
61 [ PIPE_FORMAT_B8G8R8X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM, SVGA3D_B8G8R8X8_UNORM, TF_GEN_MIPS },
62 [ PIPE_FORMAT_B5G5R5A1_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B5G5R5A1_UNORM, SVGA3D_B5G5R5A1_UNORM, TF_GEN_MIPS },
63 [ PIPE_FORMAT_B5G6R5_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B5G6R5_UNORM, SVGA3D_B5G6R5_UNORM, TF_GEN_MIPS },
64 [ PIPE_FORMAT_R10G10B10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, SVGA3D_R10G10B10A2_UNORM, TF_GEN_MIPS | TF_UAV },
65 [ PIPE_FORMAT_L8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXX1 },
66 [ PIPE_FORMAT_A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_A8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_000X | TF_UAV },
67 [ PIPE_FORMAT_I8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UNORM, TF_XXXX },
68 [ PIPE_FORMAT_L8A8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UNORM, TF_XXXY },
69 [ PIPE_FORMAT_L16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXX1 },
70 [ PIPE_FORMAT_Z16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D16_UNORM, SVGA3D_D16_UNORM, 0 },
71 [ PIPE_FORMAT_Z32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT, SVGA3D_D32_FLOAT, 0 },
72 [ PIPE_FORMAT_Z24_UNORM_S8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
73 [ PIPE_FORMAT_Z24X8_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D24_UNORM_S8_UINT, SVGA3D_D24_UNORM_S8_UINT, 0 },
74 [ PIPE_FORMAT_R32_FLOAT ] = { SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, SVGA3D_R32_FLOAT, TF_GEN_MIPS | TF_UAV },
75 [ PIPE_FORMAT_R32G32_FLOAT ] = { SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, SVGA3D_R32G32_FLOAT, TF_GEN_MIPS | TF_UAV },
76 [ PIPE_FORMAT_R32G32B32_FLOAT ] = { SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, SVGA3D_R32G32B32_FLOAT, TF_GEN_MIPS },
77 [ PIPE_FORMAT_R32G32B32A32_FLOAT ] = { SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, SVGA3D_R32G32B32A32_FLOAT, TF_GEN_MIPS | TF_UAV },
78 [ PIPE_FORMAT_R32_USCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
79 [ PIPE_FORMAT_R32G32_USCALED ] = { SVGA3D_R32G32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
80 [ PIPE_FORMAT_R32G32B32_USCALED ] = { SVGA3D_R32G32B32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
81 [ PIPE_FORMAT_R32G32B32A32_USCALED ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
82 [ PIPE_FORMAT_R32_SSCALED ] = { SVGA3D_R32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
83 [ PIPE_FORMAT_R32G32_SSCALED ] = { SVGA3D_R32G32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
84 [ PIPE_FORMAT_R32G32B32_SSCALED ] = { SVGA3D_R32G32B32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
85 [ PIPE_FORMAT_R32G32B32A32_SSCALED ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
86 [ PIPE_FORMAT_R16_UNORM ] = { SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, SVGA3D_R16_UNORM, TF_GEN_MIPS | TF_UAV },
87 [ PIPE_FORMAT_R16G16_UNORM ] = { SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, SVGA3D_R16G16_UNORM, TF_GEN_MIPS | TF_UAV },
88 [ PIPE_FORMAT_R16G16B16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
89 [ PIPE_FORMAT_R16G16B16A16_UNORM ] = { SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, SVGA3D_R16G16B16A16_UNORM, TF_GEN_MIPS | TF_UAV },
90 [ PIPE_FORMAT_R16_USCALED ] = { SVGA3D_R16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
91 [ PIPE_FORMAT_R16G16_USCALED ] = { SVGA3D_R16G16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
92 [ PIPE_FORMAT_R16G16B16_USCALED ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
93 [ PIPE_FORMAT_R16G16B16A16_USCALED ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
94 [ PIPE_FORMAT_R16_SNORM ] = { SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, SVGA3D_R16_SNORM, TF_UAV },
95 [ PIPE_FORMAT_R16G16_SNORM ] = { SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, SVGA3D_R16G16_SNORM, TF_UAV },
96 [ PIPE_FORMAT_R16G16B16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
97 [ PIPE_FORMAT_R16G16B16A16_SNORM ] = { SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, SVGA3D_R16G16B16A16_SNORM, TF_UAV },
98 [ PIPE_FORMAT_R16_SSCALED ] = { SVGA3D_R16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
99 [ PIPE_FORMAT_R16G16_SSCALED ] = { SVGA3D_R16G16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
100 [ PIPE_FORMAT_R16G16B16_SSCALED ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
101 [ PIPE_FORMAT_R16G16B16A16_SSCALED ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
102 [ PIPE_FORMAT_R8_UNORM ] = { SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, SVGA3D_R8_UNORM, TF_GEN_MIPS | TF_UAV },
103 [ PIPE_FORMAT_R8G8_UNORM ] = { SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, SVGA3D_R8G8_UNORM, TF_GEN_MIPS | TF_UAV },
104 [ PIPE_FORMAT_R8G8B8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
105 [ PIPE_FORMAT_R8G8B8A8_UNORM ] = { SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, SVGA3D_R8G8B8A8_UNORM, TF_GEN_MIPS | TF_UAV },
106 [ PIPE_FORMAT_R8_USCALED ] = { SVGA3D_R8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
107 [ PIPE_FORMAT_R8G8_USCALED ] = { SVGA3D_R8G8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
108 [ PIPE_FORMAT_R8G8B8_USCALED ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_U_TO_F_CAST },
109 [ PIPE_FORMAT_R8G8B8A8_USCALED ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_U_TO_F_CAST },
110 [ PIPE_FORMAT_R8_SNORM ] = { SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, SVGA3D_R8_SNORM, TF_UAV },
111 [ PIPE_FORMAT_R8G8_SNORM ] = { SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, SVGA3D_R8G8_SNORM, TF_UAV },
112 [ PIPE_FORMAT_R8G8B8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
113 [ PIPE_FORMAT_R8G8B8A8_SNORM ] = { SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, SVGA3D_R8G8B8A8_SNORM, TF_UAV },
114 [ PIPE_FORMAT_R8_SSCALED ] = { SVGA3D_R8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
115 [ PIPE_FORMAT_R8G8_SSCALED ] = { SVGA3D_R8G8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
116 [ PIPE_FORMAT_R8G8B8_SSCALED ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 | VF_I_TO_F_CAST },
117 [ PIPE_FORMAT_R8G8B8A8_SSCALED ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_I_TO_F_CAST },
118 [ PIPE_FORMAT_R16_FLOAT ] = { SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, SVGA3D_R16_FLOAT, TF_GEN_MIPS | TF_UAV },
119 [ PIPE_FORMAT_R16G16_FLOAT ] = { SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, SVGA3D_R16G16_FLOAT, TF_GEN_MIPS | TF_UAV },
120 [ PIPE_FORMAT_R16G16B16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
121 [ PIPE_FORMAT_R16G16B16A16_FLOAT ] = { SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, SVGA3D_R16G16B16A16_FLOAT, TF_GEN_MIPS | TF_UAV },
122 [ PIPE_FORMAT_B8G8R8A8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
123 [ PIPE_FORMAT_B8G8R8X8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
124 [ PIPE_FORMAT_R8G8B8A8_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_GEN_MIPS },
125 [ PIPE_FORMAT_DXT1_RGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
126 [ PIPE_FORMAT_DXT1_RGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM, SVGA3D_FORMAT_INVALID, 0 },
127 [ PIPE_FORMAT_DXT3_RGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM, SVGA3D_FORMAT_INVALID, 0 },
128 [ PIPE_FORMAT_DXT5_RGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM, SVGA3D_FORMAT_INVALID, 0 },
129 [ PIPE_FORMAT_DXT1_SRGB ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
130 [ PIPE_FORMAT_DXT1_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC1_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
131 [ PIPE_FORMAT_DXT3_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC2_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
132 [ PIPE_FORMAT_DXT5_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC3_UNORM_SRGB, SVGA3D_FORMAT_INVALID, 0 },
133 [ PIPE_FORMAT_RGTC1_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC4_UNORM, SVGA3D_FORMAT_INVALID, 0 },
134 [ PIPE_FORMAT_RGTC1_SNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC4_SNORM, SVGA3D_FORMAT_INVALID, 0 },
135 [ PIPE_FORMAT_RGTC2_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC5_UNORM, SVGA3D_FORMAT_INVALID, 0 },
136 [ PIPE_FORMAT_RGTC2_SNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC5_SNORM, SVGA3D_FORMAT_INVALID, 0 },
137 [ PIPE_FORMAT_R10G10B10A2_USCALED ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_USCALED },
138 [ PIPE_FORMAT_R11G11B10_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R11G11B10_FLOAT, SVGA3D_R11G11B10_FLOAT, TF_GEN_MIPS | TF_UAV },
139 [ PIPE_FORMAT_R9G9B9E5_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3D_FORMAT_INVALID, 0 },
140 [ PIPE_FORMAT_Z32_FLOAT_S8X24_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
141 [ PIPE_FORMAT_B10G10R10A2_UNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA },
142 [ PIPE_FORMAT_L16A16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UNORM, TF_XXXY },
143 [ PIPE_FORMAT_A16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_000X },
144 [ PIPE_FORMAT_I16_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UNORM, TF_XXXX },
145 [ PIPE_FORMAT_A16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_000X },
146 [ PIPE_FORMAT_L16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXX1 },
147 [ PIPE_FORMAT_L16A16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_FLOAT, TF_XXXY },
148 [ PIPE_FORMAT_I16_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_FLOAT, TF_XXXX },
149 [ PIPE_FORMAT_A32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_000X },
150 [ PIPE_FORMAT_L32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXX1 },
151 [ PIPE_FORMAT_L32A32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_FLOAT, TF_XXXY },
152 [ PIPE_FORMAT_I32_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_FLOAT, TF_XXXX },
153 [ PIPE_FORMAT_R10G10B10A2_SSCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SSCALED },
154 [ PIPE_FORMAT_R10G10B10A2_SNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_PUINT_TO_SNORM },
155 [ PIPE_FORMAT_B10G10R10A2_USCALED ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_USCALED },
156 [ PIPE_FORMAT_B10G10R10A2_SSCALED ] = { SVGA3D_R32_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SSCALED },
157 [ PIPE_FORMAT_B10G10R10A2_SNORM ] = { SVGA3D_R10G10B10A2_UNORM, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_BGRA | VF_PUINT_TO_SNORM },
158 [ PIPE_FORMAT_R8_UINT ] = { SVGA3D_R8_UINT, SVGA3D_R8_UINT, SVGA3D_R8_UINT, TF_UAV },
159 [ PIPE_FORMAT_R8G8_UINT ] = { SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, SVGA3D_R8G8_UINT, TF_UAV },
160 [ PIPE_FORMAT_R8G8B8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
161 [ PIPE_FORMAT_R8G8B8A8_UINT ] = { SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, SVGA3D_R8G8B8A8_UINT, TF_UAV },
162 [ PIPE_FORMAT_R8_SINT ] = { SVGA3D_R8_SINT, SVGA3D_R8_SINT, SVGA3D_R8_SINT, TF_UAV },
163 [ PIPE_FORMAT_R8G8_SINT ] = { SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, SVGA3D_R8G8_SINT, TF_UAV },
164 [ PIPE_FORMAT_R8G8B8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
165 [ PIPE_FORMAT_R8G8B8A8_SINT ] = { SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, SVGA3D_R8G8B8A8_SINT, TF_UAV },
166 [ PIPE_FORMAT_R16_UINT ] = { SVGA3D_R16_UINT, SVGA3D_R16_UINT, SVGA3D_R16_UINT, TF_UAV },
167 [ PIPE_FORMAT_R16G16_UINT ] = { SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, SVGA3D_R16G16_UINT, TF_UAV },
168 [ PIPE_FORMAT_R16G16B16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
169 [ PIPE_FORMAT_R16G16B16A16_UINT ] = { SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, SVGA3D_R16G16B16A16_UINT, TF_UAV },
170 [ PIPE_FORMAT_R16_SINT ] = { SVGA3D_R16_SINT, SVGA3D_R16_SINT, SVGA3D_R16_SINT, TF_UAV },
171 [ PIPE_FORMAT_R16G16_SINT ] = { SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, SVGA3D_R16G16_SINT, TF_UAV },
172 [ PIPE_FORMAT_R16G16B16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, VF_W_TO_1 },
173 [ PIPE_FORMAT_R16G16B16A16_SINT ] = { SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, SVGA3D_R16G16B16A16_SINT, TF_UAV },
174 [ PIPE_FORMAT_R32_UINT ] = { SVGA3D_R32_UINT, SVGA3D_R32_UINT, SVGA3D_R32_UINT, TF_UAV },
175 [ PIPE_FORMAT_R32G32_UINT ] = { SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, SVGA3D_R32G32_UINT, TF_UAV },
176 [ PIPE_FORMAT_R32G32B32_UINT ] = { SVGA3D_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, SVGA3D_R32G32B32_UINT, 0 },
177 [ PIPE_FORMAT_R32G32B32A32_UINT ] = { SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, SVGA3D_R32G32B32A32_UINT, TF_UAV },
178 [ PIPE_FORMAT_R32_SINT ] = { SVGA3D_R32_SINT, SVGA3D_R32_SINT, SVGA3D_R32_SINT, TF_UAV },
179 [ PIPE_FORMAT_R32G32_SINT ] = { SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, SVGA3D_R32G32_SINT, TF_UAV },
180 [ PIPE_FORMAT_R32G32B32_SINT ] = { SVGA3D_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, SVGA3D_R32G32B32_SINT, 0 },
181 [ PIPE_FORMAT_R32G32B32A32_SINT ] = { SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, SVGA3D_R32G32B32A32_SINT, TF_UAV },
182 [ PIPE_FORMAT_A8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_000X },
183 [ PIPE_FORMAT_I8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXXX },
184 [ PIPE_FORMAT_L8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_UINT, TF_XXX1 },
185 [ PIPE_FORMAT_L8A8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_UINT, TF_XXXY },
186 [ PIPE_FORMAT_A8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_000X },
187 [ PIPE_FORMAT_I8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXXX },
188 [ PIPE_FORMAT_L8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8_SINT, TF_XXX1 },
189 [ PIPE_FORMAT_L8A8_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R8G8_SINT, TF_XXXY },
190 [ PIPE_FORMAT_A16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_000X },
191 [ PIPE_FORMAT_I16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXXX },
192 [ PIPE_FORMAT_L16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_UINT, TF_XXX1 },
193 [ PIPE_FORMAT_L16A16_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_UINT, TF_XXXY },
194 [ PIPE_FORMAT_A16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_000X },
195 [ PIPE_FORMAT_I16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXXX },
196 [ PIPE_FORMAT_L16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16_SINT, TF_XXX1 },
197 [ PIPE_FORMAT_L16A16_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R16G16_SINT, TF_XXXY },
198 [ PIPE_FORMAT_A32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_000X },
199 [ PIPE_FORMAT_I32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXXX },
200 [ PIPE_FORMAT_L32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_UINT, TF_XXX1 },
201 [ PIPE_FORMAT_L32A32_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_UINT, TF_XXXY },
202 [ PIPE_FORMAT_A32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_000X },
203 [ PIPE_FORMAT_I32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXXX },
204 [ PIPE_FORMAT_L32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32_SINT, TF_XXX1 },
205 [ PIPE_FORMAT_L32A32_SINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_R32G32_SINT, TF_XXXY },
206 [ PIPE_FORMAT_R10G10B10A2_UINT ] = { SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, SVGA3D_R10G10B10A2_UINT, TF_UAV },
207 [ PIPE_FORMAT_BPTC_RGBA_UNORM ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC7_UNORM, SVGA3D_FORMAT_INVALID, TF_SM5 },
208 [ PIPE_FORMAT_BPTC_SRGBA ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC7_UNORM_SRGB, SVGA3D_FORMAT_INVALID, TF_SM5 },
209 [ PIPE_FORMAT_BPTC_RGB_FLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC6H_SF16, SVGA3D_FORMAT_INVALID, TF_SM5 },
210 [ PIPE_FORMAT_BPTC_RGB_UFLOAT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_BC6H_UF16, SVGA3D_FORMAT_INVALID, TF_SM5 },
211 [ PIPE_FORMAT_X24S8_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_X24_G8_UINT, SVGA3D_FORMAT_INVALID, 0 },
212 [ PIPE_FORMAT_X32_S8X24_UINT ] = { SVGA3D_FORMAT_INVALID, SVGA3D_X32_G8X24_UINT, SVGA3D_FORMAT_INVALID, 0 },
213 /* Must specify following entry to give the sense of size of format_conversion_table[] */
214 [ PIPE_FORMAT_COUNT ] = {SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, SVGA3D_FORMAT_INVALID, 0 },
215 };
216
217
218 static const struct vgpu10_format_entry *
svga_format_entry(enum pipe_format format)219 svga_format_entry(enum pipe_format format)
220 {
221 /* Sparse filling of the table requires this. */
222 STATIC_ASSERT(SVGA3D_FORMAT_INVALID == 0);
223 assert(format < ARRAY_SIZE(format_conversion_table));
224 if (format >= ARRAY_SIZE(format_conversion_table))
225 return &format_conversion_table[PIPE_FORMAT_NONE];
226 else
227 return &format_conversion_table[format];
228 }
229
230 /**
231 * Translate a gallium vertex format to a vgpu10 vertex format.
232 * Also, return any special vertex format flags.
233 */
234 void
svga_translate_vertex_format_vgpu10(enum pipe_format format,SVGA3dSurfaceFormat * svga_format,unsigned * vf_flags)235 svga_translate_vertex_format_vgpu10(enum pipe_format format,
236 SVGA3dSurfaceFormat *svga_format,
237 unsigned *vf_flags)
238 {
239 const struct vgpu10_format_entry *entry = svga_format_entry(format);
240
241 *svga_format = entry->vertex_format;
242 *vf_flags = entry->flags;
243 }
244
245
246 /**
247 * Translate a gallium pixel format to a vgpu10 format
248 * to be used in a shader resource view for a texture buffer.
249 * Also return any special texture format flags such as
250 * any special swizzle mask.
251 */
252 void
svga_translate_texture_buffer_view_format(enum pipe_format format,SVGA3dSurfaceFormat * svga_format,unsigned * tf_flags)253 svga_translate_texture_buffer_view_format(enum pipe_format format,
254 SVGA3dSurfaceFormat *svga_format,
255 unsigned *tf_flags)
256 {
257 const struct vgpu10_format_entry *entry = svga_format_entry(format);
258
259 *svga_format = entry->view_format;
260 *tf_flags = entry->flags;
261 }
262
263
264 /**
265 * Translate a gallium scanout format to a svga format valid
266 * for screen target surface.
267 */
268 static SVGA3dSurfaceFormat
svga_translate_screen_target_format_vgpu10(enum pipe_format format)269 svga_translate_screen_target_format_vgpu10(enum pipe_format format)
270 {
271 switch (format) {
272 case PIPE_FORMAT_B8G8R8A8_UNORM:
273 return SVGA3D_B8G8R8A8_UNORM;
274 case PIPE_FORMAT_B8G8R8X8_UNORM:
275 return SVGA3D_B8G8R8X8_UNORM;
276 case PIPE_FORMAT_B5G6R5_UNORM:
277 return SVGA3D_R5G6B5;
278 case PIPE_FORMAT_B5G5R5A1_UNORM:
279 return SVGA3D_A1R5G5B5;
280 default:
281 debug_printf("Invalid format %s specified for screen target\n",
282 svga_format_name(format));
283 return SVGA3D_FORMAT_INVALID;
284 }
285 }
286
287 /*
288 * Translate from gallium format to SVGA3D format.
289 */
290 SVGA3dSurfaceFormat
svga_translate_format(const struct svga_screen * ss,enum pipe_format format,unsigned bind)291 svga_translate_format(const struct svga_screen *ss,
292 enum pipe_format format,
293 unsigned bind)
294 {
295 const struct vgpu10_format_entry *entry = svga_format_entry(format);
296
297 if (ss->sws->have_vgpu10) {
298 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) {
299 return entry->vertex_format;
300 }
301 else if (bind & PIPE_BIND_SCANOUT) {
302 return svga_translate_screen_target_format_vgpu10(format);
303 }
304 else if (bind & PIPE_BIND_SHADER_IMAGE) {
305 if (format_conversion_table[format].flags & TF_UAV)
306 return format_conversion_table[format].pixel_format;
307 else
308 return SVGA3D_FORMAT_INVALID;
309 }
310 else {
311 if ((format_conversion_table[format].flags & TF_SM5) &&
312 !ss->sws->have_sm5)
313 return SVGA3D_FORMAT_INVALID;
314 else
315 return entry->pixel_format;
316 }
317 }
318
319 switch(format) {
320 case PIPE_FORMAT_B8G8R8A8_UNORM:
321 return SVGA3D_A8R8G8B8;
322 case PIPE_FORMAT_B8G8R8X8_UNORM:
323 return SVGA3D_X8R8G8B8;
324
325 /* sRGB required for GL2.1 */
326 case PIPE_FORMAT_B8G8R8A8_SRGB:
327 return SVGA3D_A8R8G8B8;
328 case PIPE_FORMAT_DXT1_SRGB:
329 case PIPE_FORMAT_DXT1_SRGBA:
330 return SVGA3D_DXT1;
331 case PIPE_FORMAT_DXT3_SRGBA:
332 return SVGA3D_DXT3;
333 case PIPE_FORMAT_DXT5_SRGBA:
334 return SVGA3D_DXT5;
335
336 case PIPE_FORMAT_B5G6R5_UNORM:
337 return SVGA3D_R5G6B5;
338 case PIPE_FORMAT_B5G5R5A1_UNORM:
339 return SVGA3D_A1R5G5B5;
340 case PIPE_FORMAT_B4G4R4A4_UNORM:
341 return SVGA3D_A4R4G4B4;
342
343 case PIPE_FORMAT_R16G16B16A16_UNORM:
344 return SVGA3D_A16B16G16R16;
345
346 case PIPE_FORMAT_Z16_UNORM:
347 assert(!ss->sws->have_vgpu10);
348 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.z16 : SVGA3D_Z_D16;
349 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
350 assert(!ss->sws->have_vgpu10);
351 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.s8z24 : SVGA3D_Z_D24S8;
352 case PIPE_FORMAT_X8Z24_UNORM:
353 assert(!ss->sws->have_vgpu10);
354 return bind & PIPE_BIND_SAMPLER_VIEW ? ss->depth.x8z24 : SVGA3D_Z_D24X8;
355
356 case PIPE_FORMAT_A8_UNORM:
357 return SVGA3D_ALPHA8;
358 case PIPE_FORMAT_L8_UNORM:
359 return SVGA3D_LUMINANCE8;
360
361 case PIPE_FORMAT_DXT1_RGB:
362 case PIPE_FORMAT_DXT1_RGBA:
363 return SVGA3D_DXT1;
364 case PIPE_FORMAT_DXT3_RGBA:
365 return SVGA3D_DXT3;
366 case PIPE_FORMAT_DXT5_RGBA:
367 return SVGA3D_DXT5;
368
369 /* Float formats (only 1, 2 and 4-component formats supported) */
370 case PIPE_FORMAT_R32_FLOAT:
371 return SVGA3D_R_S23E8;
372 case PIPE_FORMAT_R32G32_FLOAT:
373 return SVGA3D_RG_S23E8;
374 case PIPE_FORMAT_R32G32B32A32_FLOAT:
375 return SVGA3D_ARGB_S23E8;
376 case PIPE_FORMAT_R16_FLOAT:
377 return SVGA3D_R_S10E5;
378 case PIPE_FORMAT_R16G16_FLOAT:
379 return SVGA3D_RG_S10E5;
380 case PIPE_FORMAT_R16G16B16A16_FLOAT:
381 return SVGA3D_ARGB_S10E5;
382
383 case PIPE_FORMAT_Z32_UNORM:
384 /* SVGA3D_Z_D32 is not yet unsupported */
385 FALLTHROUGH;
386 default:
387 return SVGA3D_FORMAT_INVALID;
388 }
389 }
390
391
392 /*
393 * Format capability description entry.
394 */
395 struct format_cap {
396 const char *name;
397
398 SVGA3dSurfaceFormat format;
399
400 /*
401 * Capability index corresponding to the format.
402 */
403 SVGA3dDevCapIndex devcap;
404
405 /* size of each pixel/block */
406 unsigned block_width, block_height, block_bytes;
407
408 /*
409 * Mask of supported SVGA3dFormatOp operations, to be inferred when the
410 * capability is not explicitly present.
411 */
412 uint32 defaultOperations;
413 };
414
415
416 /*
417 * Format capability description table.
418 *
419 * Ordered by increasing SVGA3dSurfaceFormat value, but with gaps.
420 */
421 static const struct format_cap format_cap_table[] = {
422 {
423 "SVGA3D_FORMAT_INVALID",
424 SVGA3D_FORMAT_INVALID, 0, 0, 0, 0, 0
425 },
426 {
427 "SVGA3D_X8R8G8B8",
428 SVGA3D_X8R8G8B8,
429 SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8,
430 1, 1, 4,
431 SVGA3DFORMAT_OP_TEXTURE |
432 SVGA3DFORMAT_OP_CUBETEXTURE |
433 SVGA3DFORMAT_OP_VOLUMETEXTURE |
434 SVGA3DFORMAT_OP_DISPLAYMODE |
435 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
436 },
437 {
438 "SVGA3D_A8R8G8B8",
439 SVGA3D_A8R8G8B8,
440 SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8,
441 1, 1, 4,
442 SVGA3DFORMAT_OP_TEXTURE |
443 SVGA3DFORMAT_OP_CUBETEXTURE |
444 SVGA3DFORMAT_OP_VOLUMETEXTURE |
445 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
446 },
447 {
448 "SVGA3D_R5G6B5",
449 SVGA3D_R5G6B5,
450 SVGA3D_DEVCAP_SURFACEFMT_R5G6B5,
451 1, 1, 2,
452 SVGA3DFORMAT_OP_TEXTURE |
453 SVGA3DFORMAT_OP_CUBETEXTURE |
454 SVGA3DFORMAT_OP_VOLUMETEXTURE |
455 SVGA3DFORMAT_OP_DISPLAYMODE |
456 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
457 },
458 {
459 "SVGA3D_X1R5G5B5",
460 SVGA3D_X1R5G5B5,
461 SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5,
462 1, 1, 2,
463 SVGA3DFORMAT_OP_TEXTURE |
464 SVGA3DFORMAT_OP_CUBETEXTURE |
465 SVGA3DFORMAT_OP_VOLUMETEXTURE |
466 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
467 },
468 {
469 "SVGA3D_A1R5G5B5",
470 SVGA3D_A1R5G5B5,
471 SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5,
472 1, 1, 2,
473 SVGA3DFORMAT_OP_TEXTURE |
474 SVGA3DFORMAT_OP_CUBETEXTURE |
475 SVGA3DFORMAT_OP_VOLUMETEXTURE |
476 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
477 },
478 {
479 "SVGA3D_A4R4G4B4",
480 SVGA3D_A4R4G4B4,
481 SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4,
482 1, 1, 2,
483 SVGA3DFORMAT_OP_TEXTURE |
484 SVGA3DFORMAT_OP_CUBETEXTURE |
485 SVGA3DFORMAT_OP_VOLUMETEXTURE |
486 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
487 },
488 {
489 /*
490 * SVGA3D_Z_D32 is not yet supported, and has no corresponding
491 * SVGA3D_DEVCAP_xxx.
492 */
493 "SVGA3D_Z_D32",
494 SVGA3D_Z_D32, 0, 0, 0, 0, 0
495 },
496 {
497 "SVGA3D_Z_D16",
498 SVGA3D_Z_D16,
499 SVGA3D_DEVCAP_SURFACEFMT_Z_D16,
500 1, 1, 2,
501 SVGA3DFORMAT_OP_ZSTENCIL
502 },
503 {
504 "SVGA3D_Z_D24S8",
505 SVGA3D_Z_D24S8,
506 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8,
507 1, 1, 4,
508 SVGA3DFORMAT_OP_ZSTENCIL
509 },
510 {
511 "SVGA3D_Z_D15S1",
512 SVGA3D_Z_D15S1,
513 SVGA3D_DEVCAP_MAX,
514 1, 1, 2,
515 SVGA3DFORMAT_OP_ZSTENCIL
516 },
517 {
518 "SVGA3D_LUMINANCE8",
519 SVGA3D_LUMINANCE8,
520 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8,
521 1, 1, 1,
522 SVGA3DFORMAT_OP_TEXTURE |
523 SVGA3DFORMAT_OP_CUBETEXTURE |
524 SVGA3DFORMAT_OP_VOLUMETEXTURE
525 },
526 {
527 /*
528 * SVGA3D_LUMINANCE4_ALPHA4 is not supported, and has no corresponding
529 * SVGA3D_DEVCAP_xxx.
530 */
531 "SVGA3D_LUMINANCE4_ALPHA4",
532 SVGA3D_LUMINANCE4_ALPHA4, 0, 0, 0, 0, 0
533 },
534 {
535 "SVGA3D_LUMINANCE16",
536 SVGA3D_LUMINANCE16,
537 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16,
538 1, 1, 2,
539 SVGA3DFORMAT_OP_TEXTURE |
540 SVGA3DFORMAT_OP_CUBETEXTURE |
541 SVGA3DFORMAT_OP_VOLUMETEXTURE
542 },
543 {
544 "SVGA3D_LUMINANCE8_ALPHA8",
545 SVGA3D_LUMINANCE8_ALPHA8,
546 SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8,
547 1, 1, 2,
548 SVGA3DFORMAT_OP_TEXTURE |
549 SVGA3DFORMAT_OP_CUBETEXTURE |
550 SVGA3DFORMAT_OP_VOLUMETEXTURE
551 },
552 {
553 "SVGA3D_DXT1",
554 SVGA3D_DXT1,
555 SVGA3D_DEVCAP_SURFACEFMT_DXT1,
556 4, 4, 8,
557 SVGA3DFORMAT_OP_TEXTURE |
558 SVGA3DFORMAT_OP_CUBETEXTURE
559 },
560 {
561 "SVGA3D_DXT2",
562 SVGA3D_DXT2,
563 SVGA3D_DEVCAP_SURFACEFMT_DXT2,
564 4, 4, 8,
565 SVGA3DFORMAT_OP_TEXTURE |
566 SVGA3DFORMAT_OP_CUBETEXTURE
567 },
568 {
569 "SVGA3D_DXT3",
570 SVGA3D_DXT3,
571 SVGA3D_DEVCAP_SURFACEFMT_DXT3,
572 4, 4, 16,
573 SVGA3DFORMAT_OP_TEXTURE |
574 SVGA3DFORMAT_OP_CUBETEXTURE
575 },
576 {
577 "SVGA3D_DXT4",
578 SVGA3D_DXT4,
579 SVGA3D_DEVCAP_SURFACEFMT_DXT4,
580 4, 4, 16,
581 SVGA3DFORMAT_OP_TEXTURE |
582 SVGA3DFORMAT_OP_CUBETEXTURE
583 },
584 {
585 "SVGA3D_DXT5",
586 SVGA3D_DXT5,
587 SVGA3D_DEVCAP_SURFACEFMT_DXT5,
588 4, 4, 8,
589 SVGA3DFORMAT_OP_TEXTURE |
590 SVGA3DFORMAT_OP_CUBETEXTURE
591 },
592 {
593 "SVGA3D_BUMPU8V8",
594 SVGA3D_BUMPU8V8,
595 SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8,
596 1, 1, 2,
597 SVGA3DFORMAT_OP_TEXTURE |
598 SVGA3DFORMAT_OP_CUBETEXTURE |
599 SVGA3DFORMAT_OP_VOLUMETEXTURE
600 },
601 {
602 /*
603 * SVGA3D_BUMPL6V5U5 is unsupported; it has no corresponding
604 * SVGA3D_DEVCAP_xxx.
605 */
606 "SVGA3D_BUMPL6V5U5",
607 SVGA3D_BUMPL6V5U5, 0, 0, 0, 0, 0
608 },
609 {
610 "SVGA3D_BUMPX8L8V8U8",
611 SVGA3D_BUMPX8L8V8U8,
612 SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8,
613 1, 1, 4,
614 SVGA3DFORMAT_OP_TEXTURE |
615 SVGA3DFORMAT_OP_CUBETEXTURE
616 },
617 {
618 "SVGA3D_FORMAT_DEAD1",
619 SVGA3D_FORMAT_DEAD1, 0, 0, 0, 0, 0
620 },
621 {
622 "SVGA3D_ARGB_S10E5",
623 SVGA3D_ARGB_S10E5,
624 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5,
625 1, 1, 2,
626 SVGA3DFORMAT_OP_TEXTURE |
627 SVGA3DFORMAT_OP_CUBETEXTURE |
628 SVGA3DFORMAT_OP_VOLUMETEXTURE |
629 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
630 },
631 {
632 "SVGA3D_ARGB_S23E8",
633 SVGA3D_ARGB_S23E8,
634 SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8,
635 1, 1, 4,
636 SVGA3DFORMAT_OP_TEXTURE |
637 SVGA3DFORMAT_OP_CUBETEXTURE |
638 SVGA3DFORMAT_OP_VOLUMETEXTURE |
639 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
640 },
641 {
642 "SVGA3D_A2R10G10B10",
643 SVGA3D_A2R10G10B10,
644 SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10,
645 1, 1, 4,
646 SVGA3DFORMAT_OP_TEXTURE |
647 SVGA3DFORMAT_OP_CUBETEXTURE |
648 SVGA3DFORMAT_OP_VOLUMETEXTURE |
649 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
650 },
651 {
652 /*
653 * SVGA3D_V8U8 is unsupported; it has no corresponding
654 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPU8V8 should be used instead.
655 */
656 "SVGA3D_V8U8",
657 SVGA3D_V8U8, 0, 0, 0, 0, 0
658 },
659 {
660 "SVGA3D_Q8W8V8U8",
661 SVGA3D_Q8W8V8U8,
662 SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8,
663 1, 1, 4,
664 SVGA3DFORMAT_OP_TEXTURE |
665 SVGA3DFORMAT_OP_CUBETEXTURE
666 },
667 {
668 "SVGA3D_CxV8U8",
669 SVGA3D_CxV8U8,
670 SVGA3D_DEVCAP_SURFACEFMT_CxV8U8,
671 1, 1, 2,
672 SVGA3DFORMAT_OP_TEXTURE
673 },
674 {
675 /*
676 * SVGA3D_X8L8V8U8 is unsupported; it has no corresponding
677 * SVGA3D_DEVCAP_xxx. SVGA3D_BUMPX8L8V8U8 should be used instead.
678 */
679 "SVGA3D_X8L8V8U8",
680 SVGA3D_X8L8V8U8, 0, 0, 0, 0, 0
681 },
682 {
683 "SVGA3D_A2W10V10U10",
684 SVGA3D_A2W10V10U10,
685 SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10,
686 1, 1, 4,
687 SVGA3DFORMAT_OP_TEXTURE
688 },
689 {
690 "SVGA3D_ALPHA8",
691 SVGA3D_ALPHA8,
692 SVGA3D_DEVCAP_SURFACEFMT_ALPHA8,
693 1, 1, 1,
694 SVGA3DFORMAT_OP_TEXTURE |
695 SVGA3DFORMAT_OP_CUBETEXTURE |
696 SVGA3DFORMAT_OP_VOLUMETEXTURE
697 },
698 {
699 "SVGA3D_R_S10E5",
700 SVGA3D_R_S10E5,
701 SVGA3D_DEVCAP_SURFACEFMT_R_S10E5,
702 1, 1, 2,
703 SVGA3DFORMAT_OP_TEXTURE |
704 SVGA3DFORMAT_OP_VOLUMETEXTURE |
705 SVGA3DFORMAT_OP_CUBETEXTURE |
706 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
707 },
708 {
709 "SVGA3D_R_S23E8",
710 SVGA3D_R_S23E8,
711 SVGA3D_DEVCAP_SURFACEFMT_R_S23E8,
712 1, 1, 4,
713 SVGA3DFORMAT_OP_TEXTURE |
714 SVGA3DFORMAT_OP_VOLUMETEXTURE |
715 SVGA3DFORMAT_OP_CUBETEXTURE |
716 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
717 },
718 {
719 "SVGA3D_RG_S10E5",
720 SVGA3D_RG_S10E5,
721 SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5,
722 1, 1, 2,
723 SVGA3DFORMAT_OP_TEXTURE |
724 SVGA3DFORMAT_OP_VOLUMETEXTURE |
725 SVGA3DFORMAT_OP_CUBETEXTURE |
726 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
727 },
728 {
729 "SVGA3D_RG_S23E8",
730 SVGA3D_RG_S23E8,
731 SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8,
732 1, 1, 4,
733 SVGA3DFORMAT_OP_TEXTURE |
734 SVGA3DFORMAT_OP_VOLUMETEXTURE |
735 SVGA3DFORMAT_OP_CUBETEXTURE |
736 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
737 },
738 {
739 /*
740 * SVGA3D_BUFFER is a placeholder format for index/vertex buffers.
741 */
742 "SVGA3D_BUFFER",
743 SVGA3D_BUFFER, 0, 1, 1, 1, 0
744 },
745 {
746 "SVGA3D_Z_D24X8",
747 SVGA3D_Z_D24X8,
748 SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8,
749 1, 1, 4,
750 SVGA3DFORMAT_OP_ZSTENCIL
751 },
752 {
753 "SVGA3D_V16U16",
754 SVGA3D_V16U16,
755 SVGA3D_DEVCAP_SURFACEFMT_V16U16,
756 1, 1, 4,
757 SVGA3DFORMAT_OP_TEXTURE |
758 SVGA3DFORMAT_OP_CUBETEXTURE |
759 SVGA3DFORMAT_OP_VOLUMETEXTURE
760 },
761 {
762 "SVGA3D_G16R16",
763 SVGA3D_G16R16,
764 SVGA3D_DEVCAP_SURFACEFMT_G16R16,
765 1, 1, 4,
766 SVGA3DFORMAT_OP_TEXTURE |
767 SVGA3DFORMAT_OP_CUBETEXTURE |
768 SVGA3DFORMAT_OP_VOLUMETEXTURE |
769 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
770 },
771 {
772 "SVGA3D_A16B16G16R16",
773 SVGA3D_A16B16G16R16,
774 SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16,
775 1, 1, 8,
776 SVGA3DFORMAT_OP_TEXTURE |
777 SVGA3DFORMAT_OP_CUBETEXTURE |
778 SVGA3DFORMAT_OP_VOLUMETEXTURE |
779 SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET
780 },
781 {
782 "SVGA3D_UYVY",
783 SVGA3D_UYVY,
784 SVGA3D_DEVCAP_SURFACEFMT_UYVY,
785 0, 0, 0, 0
786 },
787 {
788 "SVGA3D_YUY2",
789 SVGA3D_YUY2,
790 SVGA3D_DEVCAP_SURFACEFMT_YUY2,
791 0, 0, 0, 0
792 },
793 {
794 "SVGA3D_NV12",
795 SVGA3D_NV12,
796 SVGA3D_DEVCAP_SURFACEFMT_NV12,
797 0, 0, 0, 0
798 },
799 {
800 "SVGA3D_FORMAT_DEAD2",
801 SVGA3D_FORMAT_DEAD2, 0, 0, 0, 0, 0
802 },
803 {
804 "SVGA3D_R32G32B32A32_TYPELESS",
805 SVGA3D_R32G32B32A32_TYPELESS,
806 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS,
807 1, 1, 16, 0
808 },
809 {
810 "SVGA3D_R32G32B32A32_UINT",
811 SVGA3D_R32G32B32A32_UINT,
812 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT,
813 1, 1, 16, 0
814 },
815 {
816 "SVGA3D_R32G32B32A32_SINT",
817 SVGA3D_R32G32B32A32_SINT,
818 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT,
819 1, 1, 16, 0
820 },
821 {
822 "SVGA3D_R32G32B32_TYPELESS",
823 SVGA3D_R32G32B32_TYPELESS,
824 SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS,
825 1, 1, 12, 0
826 },
827 {
828 "SVGA3D_R32G32B32_FLOAT",
829 SVGA3D_R32G32B32_FLOAT,
830 SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT,
831 1, 1, 12, 0
832 },
833 {
834 "SVGA3D_R32G32B32_UINT",
835 SVGA3D_R32G32B32_UINT,
836 SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT,
837 1, 1, 12, 0
838 },
839 {
840 "SVGA3D_R32G32B32_SINT",
841 SVGA3D_R32G32B32_SINT,
842 SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT,
843 1, 1, 12, 0
844 },
845 {
846 "SVGA3D_R16G16B16A16_TYPELESS",
847 SVGA3D_R16G16B16A16_TYPELESS,
848 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS,
849 1, 1, 8, 0
850 },
851 {
852 "SVGA3D_R16G16B16A16_UINT",
853 SVGA3D_R16G16B16A16_UINT,
854 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT,
855 1, 1, 8, 0
856 },
857 {
858 "SVGA3D_R16G16B16A16_SNORM",
859 SVGA3D_R16G16B16A16_SNORM,
860 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM,
861 1, 1, 8, 0
862 },
863 {
864 "SVGA3D_R16G16B16A16_SINT",
865 SVGA3D_R16G16B16A16_SINT,
866 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT,
867 1, 1, 8, 0
868 },
869 {
870 "SVGA3D_R32G32_TYPELESS",
871 SVGA3D_R32G32_TYPELESS,
872 SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS,
873 1, 1, 8, 0
874 },
875 {
876 "SVGA3D_R32G32_UINT",
877 SVGA3D_R32G32_UINT,
878 SVGA3D_DEVCAP_DXFMT_R32G32_UINT,
879 1, 1, 8, 0
880 },
881 {
882 "SVGA3D_R32G32_SINT",
883 SVGA3D_R32G32_SINT,
884 SVGA3D_DEVCAP_DXFMT_R32G32_SINT,
885 1, 1, 8,
886 0
887 },
888 {
889 "SVGA3D_R32G8X24_TYPELESS",
890 SVGA3D_R32G8X24_TYPELESS,
891 SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS,
892 1, 1, 8, 0
893 },
894 {
895 "SVGA3D_D32_FLOAT_S8X24_UINT",
896 SVGA3D_D32_FLOAT_S8X24_UINT,
897 SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT,
898 1, 1, 8, 0
899 },
900 {
901 "SVGA3D_R32_FLOAT_X8X24",
902 SVGA3D_R32_FLOAT_X8X24,
903 SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24,
904 1, 1, 8, 0
905 },
906 {
907 "SVGA3D_X32_G8X24_UINT",
908 SVGA3D_X32_G8X24_UINT,
909 SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT,
910 1, 1, 4, 0
911 },
912 {
913 "SVGA3D_R10G10B10A2_TYPELESS",
914 SVGA3D_R10G10B10A2_TYPELESS,
915 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS,
916 1, 1, 4, 0
917 },
918 {
919 "SVGA3D_R10G10B10A2_UINT",
920 SVGA3D_R10G10B10A2_UINT,
921 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT,
922 1, 1, 4, 0
923 },
924 {
925 "SVGA3D_R11G11B10_FLOAT",
926 SVGA3D_R11G11B10_FLOAT,
927 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
928 1, 1, 4, 0
929 },
930 {
931 "SVGA3D_R8G8B8A8_TYPELESS",
932 SVGA3D_R8G8B8A8_TYPELESS,
933 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS,
934 1, 1, 4, 0
935 },
936 {
937 "SVGA3D_R8G8B8A8_UNORM",
938 SVGA3D_R8G8B8A8_UNORM,
939 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM,
940 1, 1, 4, 0
941 },
942 {
943 "SVGA3D_R8G8B8A8_UNORM_SRGB",
944 SVGA3D_R8G8B8A8_UNORM_SRGB,
945 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB,
946 1, 1, 4, 0
947 },
948 {
949 "SVGA3D_R8G8B8A8_UINT",
950 SVGA3D_R8G8B8A8_UINT,
951 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT,
952 1, 1, 4, 0
953 },
954 {
955 "SVGA3D_R8G8B8A8_SINT",
956 SVGA3D_R8G8B8A8_SINT,
957 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT,
958 1, 1, 4, 0
959 },
960 {
961 "SVGA3D_R16G16_TYPELESS",
962 SVGA3D_R16G16_TYPELESS,
963 SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS,
964 1, 1, 4, 0
965 },
966 {
967 "SVGA3D_R16G16_UINT",
968 SVGA3D_R16G16_UINT,
969 SVGA3D_DEVCAP_DXFMT_R16G16_UINT,
970 1, 1, 4, 0
971 },
972 {
973 "SVGA3D_R16G16_SINT",
974 SVGA3D_R16G16_SINT,
975 SVGA3D_DEVCAP_DXFMT_R16G16_SINT,
976 1, 1, 4, 0
977 },
978 {
979 "SVGA3D_R32_TYPELESS",
980 SVGA3D_R32_TYPELESS,
981 SVGA3D_DEVCAP_DXFMT_R32_TYPELESS,
982 1, 1, 4, 0
983 },
984 {
985 "SVGA3D_D32_FLOAT",
986 SVGA3D_D32_FLOAT,
987 SVGA3D_DEVCAP_DXFMT_D32_FLOAT,
988 1, 1, 4, 0
989 },
990 {
991 "SVGA3D_R32_UINT",
992 SVGA3D_R32_UINT,
993 SVGA3D_DEVCAP_DXFMT_R32_UINT,
994 1, 1, 4, 0
995 },
996 {
997 "SVGA3D_R32_SINT",
998 SVGA3D_R32_SINT,
999 SVGA3D_DEVCAP_DXFMT_R32_SINT,
1000 1, 1, 4, 0
1001 },
1002 {
1003 "SVGA3D_R24G8_TYPELESS",
1004 SVGA3D_R24G8_TYPELESS,
1005 SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS,
1006 1, 1, 4, 0
1007 },
1008 {
1009 "SVGA3D_D24_UNORM_S8_UINT",
1010 SVGA3D_D24_UNORM_S8_UINT,
1011 SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT,
1012 1, 1, 4, 0
1013 },
1014 {
1015 "SVGA3D_R24_UNORM_X8",
1016 SVGA3D_R24_UNORM_X8,
1017 SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8,
1018 1, 1, 4, 0
1019 },
1020 {
1021 "SVGA3D_X24_G8_UINT",
1022 SVGA3D_X24_G8_UINT,
1023 SVGA3D_DEVCAP_DXFMT_X24_G8_UINT,
1024 1, 1, 4, 0
1025 },
1026 {
1027 "SVGA3D_R8G8_TYPELESS",
1028 SVGA3D_R8G8_TYPELESS,
1029 SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS,
1030 1, 1, 2, 0
1031 },
1032 {
1033 "SVGA3D_R8G8_UNORM",
1034 SVGA3D_R8G8_UNORM,
1035 SVGA3D_DEVCAP_DXFMT_R8G8_UNORM,
1036 1, 1, 2, 0
1037 },
1038 {
1039 "SVGA3D_R8G8_UINT",
1040 SVGA3D_R8G8_UINT,
1041 SVGA3D_DEVCAP_DXFMT_R8G8_UINT,
1042 1, 1, 2, 0
1043 },
1044 {
1045 "SVGA3D_R8G8_SINT",
1046 SVGA3D_R8G8_SINT,
1047 SVGA3D_DEVCAP_DXFMT_R8G8_SINT,
1048 1, 1, 2, 0
1049 },
1050 {
1051 "SVGA3D_R16_TYPELESS",
1052 SVGA3D_R16_TYPELESS,
1053 SVGA3D_DEVCAP_DXFMT_R16_TYPELESS,
1054 1, 1, 2, 0
1055 },
1056 {
1057 "SVGA3D_R16_UNORM",
1058 SVGA3D_R16_UNORM,
1059 SVGA3D_DEVCAP_DXFMT_R16_UNORM,
1060 1, 1, 2, 0
1061 },
1062 {
1063 "SVGA3D_R16_UINT",
1064 SVGA3D_R16_UINT,
1065 SVGA3D_DEVCAP_DXFMT_R16_UINT,
1066 1, 1, 2, 0
1067 },
1068 {
1069 "SVGA3D_R16_SNORM",
1070 SVGA3D_R16_SNORM,
1071 SVGA3D_DEVCAP_DXFMT_R16_SNORM,
1072 1, 1, 2, 0
1073 },
1074 {
1075 "SVGA3D_R16_SINT",
1076 SVGA3D_R16_SINT,
1077 SVGA3D_DEVCAP_DXFMT_R16_SINT,
1078 1, 1, 2, 0
1079 },
1080 {
1081 "SVGA3D_R8_TYPELESS",
1082 SVGA3D_R8_TYPELESS,
1083 SVGA3D_DEVCAP_DXFMT_R8_TYPELESS,
1084 1, 1, 1, 0
1085 },
1086 {
1087 "SVGA3D_R8_UNORM",
1088 SVGA3D_R8_UNORM,
1089 SVGA3D_DEVCAP_DXFMT_R8_UNORM,
1090 1, 1, 1, 0
1091 },
1092 {
1093 "SVGA3D_R8_UINT",
1094 SVGA3D_R8_UINT,
1095 SVGA3D_DEVCAP_DXFMT_R8_UINT,
1096 1, 1, 1, 0
1097 },
1098 {
1099 "SVGA3D_R8_SNORM",
1100 SVGA3D_R8_SNORM,
1101 SVGA3D_DEVCAP_DXFMT_R8_SNORM,
1102 1, 1, 1, 0
1103 },
1104 {
1105 "SVGA3D_R8_SINT",
1106 SVGA3D_R8_SINT,
1107 SVGA3D_DEVCAP_DXFMT_R8_SINT,
1108 1, 1, 1, 0
1109 },
1110 {
1111 "SVGA3D_P8",
1112 SVGA3D_P8, 0, 0, 0, 0, 0
1113 },
1114 {
1115 "SVGA3D_R9G9B9E5_SHAREDEXP",
1116 SVGA3D_R9G9B9E5_SHAREDEXP,
1117 SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP,
1118 1, 1, 4, 0
1119 },
1120 {
1121 "SVGA3D_R8G8_B8G8_UNORM",
1122 SVGA3D_R8G8_B8G8_UNORM, 0, 0, 0, 0, 0
1123 },
1124 {
1125 "SVGA3D_G8R8_G8B8_UNORM",
1126 SVGA3D_G8R8_G8B8_UNORM, 0, 0, 0, 0, 0
1127 },
1128 {
1129 "SVGA3D_BC1_TYPELESS",
1130 SVGA3D_BC1_TYPELESS,
1131 SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS,
1132 4, 4, 8, 0
1133 },
1134 {
1135 "SVGA3D_BC1_UNORM_SRGB",
1136 SVGA3D_BC1_UNORM_SRGB,
1137 SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB,
1138 4, 4, 8, 0
1139 },
1140 {
1141 "SVGA3D_BC2_TYPELESS",
1142 SVGA3D_BC2_TYPELESS,
1143 SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS,
1144 4, 4, 16, 0
1145 },
1146 {
1147 "SVGA3D_BC2_UNORM_SRGB",
1148 SVGA3D_BC2_UNORM_SRGB,
1149 SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB,
1150 4, 4, 16, 0
1151 },
1152 {
1153 "SVGA3D_BC3_TYPELESS",
1154 SVGA3D_BC3_TYPELESS,
1155 SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS,
1156 4, 4, 16, 0
1157 },
1158 {
1159 "SVGA3D_BC3_UNORM_SRGB",
1160 SVGA3D_BC3_UNORM_SRGB,
1161 SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB,
1162 4, 4, 16, 0
1163 },
1164 {
1165 "SVGA3D_BC4_TYPELESS",
1166 SVGA3D_BC4_TYPELESS,
1167 SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS,
1168 4, 4, 8, 0
1169 },
1170 {
1171 "SVGA3D_ATI1",
1172 SVGA3D_ATI1, 0, 0, 0, 0, 0
1173 },
1174 {
1175 "SVGA3D_BC4_SNORM",
1176 SVGA3D_BC4_SNORM,
1177 SVGA3D_DEVCAP_DXFMT_BC4_SNORM,
1178 4, 4, 8, 0
1179 },
1180 {
1181 "SVGA3D_BC5_TYPELESS",
1182 SVGA3D_BC5_TYPELESS,
1183 SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS,
1184 4, 4, 16, 0
1185 },
1186 {
1187 "SVGA3D_ATI2",
1188 SVGA3D_ATI2, 0, 0, 0, 0, 0
1189 },
1190 {
1191 "SVGA3D_BC5_SNORM",
1192 SVGA3D_BC5_SNORM,
1193 SVGA3D_DEVCAP_DXFMT_BC5_SNORM,
1194 4, 4, 16, 0
1195 },
1196 {
1197 "SVGA3D_R10G10B10_XR_BIAS_A2_UNORM",
1198 SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, 0, 0, 0, 0, 0
1199 },
1200 {
1201 "SVGA3D_B8G8R8A8_TYPELESS",
1202 SVGA3D_B8G8R8A8_TYPELESS,
1203 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS,
1204 1, 1, 4, 0
1205 },
1206 {
1207 "SVGA3D_B8G8R8A8_UNORM_SRGB",
1208 SVGA3D_B8G8R8A8_UNORM_SRGB,
1209 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB,
1210 1, 1, 4, 0
1211 },
1212 {
1213 "SVGA3D_B8G8R8X8_TYPELESS",
1214 SVGA3D_B8G8R8X8_TYPELESS,
1215 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS,
1216 1, 1, 4, 0
1217 },
1218 {
1219 "SVGA3D_B8G8R8X8_UNORM_SRGB",
1220 SVGA3D_B8G8R8X8_UNORM_SRGB,
1221 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB,
1222 1, 1, 4, 0
1223 },
1224 {
1225 "SVGA3D_Z_DF16",
1226 SVGA3D_Z_DF16,
1227 SVGA3D_DEVCAP_SURFACEFMT_Z_DF16,
1228 1, 1, 2, 0
1229 },
1230 {
1231 "SVGA3D_Z_DF24",
1232 SVGA3D_Z_DF24,
1233 SVGA3D_DEVCAP_SURFACEFMT_Z_DF24,
1234 1, 1, 4, 0
1235 },
1236 {
1237 "SVGA3D_Z_D24S8_INT",
1238 SVGA3D_Z_D24S8_INT,
1239 SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT,
1240 1, 1, 4, 0
1241 },
1242 {
1243 "SVGA3D_YV12",
1244 SVGA3D_YV12, 0, 0, 0, 0, 0
1245 },
1246 {
1247 "SVGA3D_R32G32B32A32_FLOAT",
1248 SVGA3D_R32G32B32A32_FLOAT,
1249 SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT,
1250 1, 1, 16, 0
1251 },
1252 {
1253 "SVGA3D_R16G16B16A16_FLOAT",
1254 SVGA3D_R16G16B16A16_FLOAT,
1255 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT,
1256 1, 1, 8, 0
1257 },
1258 {
1259 "SVGA3D_R16G16B16A16_UNORM",
1260 SVGA3D_R16G16B16A16_UNORM,
1261 SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM,
1262 1, 1, 8, 0
1263 },
1264 {
1265 "SVGA3D_R32G32_FLOAT",
1266 SVGA3D_R32G32_FLOAT,
1267 SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT,
1268 1, 1, 8, 0
1269 },
1270 {
1271 "SVGA3D_R10G10B10A2_UNORM",
1272 SVGA3D_R10G10B10A2_UNORM,
1273 SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM,
1274 1, 1, 4, 0
1275 },
1276 {
1277 "SVGA3D_R8G8B8A8_SNORM",
1278 SVGA3D_R8G8B8A8_SNORM,
1279 SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM,
1280 1, 1, 4, 0
1281 },
1282 {
1283 "SVGA3D_R16G16_FLOAT",
1284 SVGA3D_R16G16_FLOAT,
1285 SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT,
1286 1, 1, 4, 0
1287 },
1288 {
1289 "SVGA3D_R16G16_UNORM",
1290 SVGA3D_R16G16_UNORM,
1291 SVGA3D_DEVCAP_DXFMT_R16G16_UNORM,
1292 1, 1, 4, 0
1293 },
1294 {
1295 "SVGA3D_R16G16_SNORM",
1296 SVGA3D_R16G16_SNORM,
1297 SVGA3D_DEVCAP_DXFMT_R16G16_SNORM,
1298 1, 1, 4, 0
1299 },
1300 {
1301 "SVGA3D_R32_FLOAT",
1302 SVGA3D_R32_FLOAT,
1303 SVGA3D_DEVCAP_DXFMT_R32_FLOAT,
1304 1, 1, 4, 0
1305 },
1306 {
1307 "SVGA3D_R8G8_SNORM",
1308 SVGA3D_R8G8_SNORM,
1309 SVGA3D_DEVCAP_DXFMT_R8G8_SNORM,
1310 1, 1, 2, 0
1311 },
1312 {
1313 "SVGA3D_R16_FLOAT",
1314 SVGA3D_R16_FLOAT,
1315 SVGA3D_DEVCAP_DXFMT_R16_FLOAT,
1316 1, 1, 2, 0
1317 },
1318 {
1319 "SVGA3D_D16_UNORM",
1320 SVGA3D_D16_UNORM,
1321 SVGA3D_DEVCAP_DXFMT_D16_UNORM,
1322 1, 1, 2, 0
1323 },
1324 {
1325 "SVGA3D_A8_UNORM",
1326 SVGA3D_A8_UNORM,
1327 SVGA3D_DEVCAP_DXFMT_A8_UNORM,
1328 1, 1, 1, 0
1329 },
1330 {
1331 "SVGA3D_BC1_UNORM",
1332 SVGA3D_BC1_UNORM,
1333 SVGA3D_DEVCAP_DXFMT_BC1_UNORM,
1334 4, 4, 8, 0
1335 },
1336 {
1337 "SVGA3D_BC2_UNORM",
1338 SVGA3D_BC2_UNORM,
1339 SVGA3D_DEVCAP_DXFMT_BC2_UNORM,
1340 4, 4, 16, 0
1341 },
1342 {
1343 "SVGA3D_BC3_UNORM",
1344 SVGA3D_BC3_UNORM,
1345 SVGA3D_DEVCAP_DXFMT_BC3_UNORM,
1346 4, 4, 16, 0
1347 },
1348 {
1349 "SVGA3D_B5G6R5_UNORM",
1350 SVGA3D_B5G6R5_UNORM,
1351 SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM,
1352 1, 1, 2, 0
1353 },
1354 {
1355 "SVGA3D_B5G5R5A1_UNORM",
1356 SVGA3D_B5G5R5A1_UNORM,
1357 SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM,
1358 1, 1, 2, 0
1359 },
1360 {
1361 "SVGA3D_B8G8R8A8_UNORM",
1362 SVGA3D_B8G8R8A8_UNORM,
1363 SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM,
1364 1, 1, 4, 0
1365 },
1366 {
1367 "SVGA3D_B8G8R8X8_UNORM",
1368 SVGA3D_B8G8R8X8_UNORM,
1369 SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM,
1370 1, 1, 4, 0
1371 },
1372 {
1373 "SVGA3D_BC4_UNORM",
1374 SVGA3D_BC4_UNORM,
1375 SVGA3D_DEVCAP_DXFMT_BC4_UNORM,
1376 4, 4, 8, 0
1377 },
1378 {
1379 "SVGA3D_BC5_UNORM",
1380 SVGA3D_BC5_UNORM,
1381 SVGA3D_DEVCAP_DXFMT_BC5_UNORM,
1382 4, 4, 16, 0
1383 },
1384 {
1385 "SVGA3D_B4G4R4A4_UNORM",
1386 SVGA3D_B4G4R4A4_UNORM,
1387 0, 0, 0, 0
1388 },
1389 {
1390 "SVGA3D_BC6H_TYPELESS",
1391 SVGA3D_BC6H_TYPELESS,
1392 SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
1393 4, 4, 16, 0
1394 },
1395 {
1396 "SVGA3D_BC6H_UF16",
1397 SVGA3D_BC6H_UF16,
1398 SVGA3D_DEVCAP_DXFMT_BC6H_UF16,
1399 4, 4, 16, 0
1400 },
1401 {
1402 "SVGA3D_BC6H_SF16",
1403 SVGA3D_BC6H_SF16,
1404 SVGA3D_DEVCAP_DXFMT_BC6H_SF16,
1405 4, 4, 16, 0
1406 },
1407 {
1408 "SVGA3D_BC7_TYPELESS",
1409 SVGA3D_BC7_TYPELESS,
1410 SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS,
1411 4, 4, 16, 0
1412 },
1413 {
1414 "SVGA3D_BC7_UNORM",
1415 SVGA3D_BC7_UNORM,
1416 SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
1417 4, 4, 16, 0
1418 },
1419 {
1420 "SVGA3D_BC7_UNORM_SRGB",
1421 SVGA3D_BC7_UNORM_SRGB,
1422 SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS,
1423 4, 4, 16, 0
1424 },
1425 {
1426 "SVGA3D_AYUV",
1427 SVGA3D_AYUV,
1428 0,
1429 1, 1, 4, 0
1430 },
1431 {
1432 "SVGA3D_R11G11B10_TYPELESS",
1433 SVGA3D_R11G11B10_TYPELESS,
1434 SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT,
1435 1, 1, 4, 0
1436 }
1437 };
1438
1439 static const SVGA3dSurfaceFormat compat_x8r8g8b8[] = {
1440 SVGA3D_X8R8G8B8, SVGA3D_A8R8G8B8, SVGA3D_B8G8R8X8_UNORM,
1441 SVGA3D_B8G8R8A8_UNORM, 0
1442 };
1443 static const SVGA3dSurfaceFormat compat_r8[] = {
1444 SVGA3D_R8_UNORM, SVGA3D_NV12, SVGA3D_YV12, 0
1445 };
1446 static const SVGA3dSurfaceFormat compat_g8r8[] = {
1447 SVGA3D_R8G8_UNORM, SVGA3D_NV12, 0
1448 };
1449 static const SVGA3dSurfaceFormat compat_r5g6b5[] = {
1450 SVGA3D_R5G6B5, SVGA3D_B5G6R5_UNORM, 0
1451 };
1452
1453 static const struct format_compat_entry format_compats[] = {
1454 {PIPE_FORMAT_B8G8R8X8_UNORM, compat_x8r8g8b8},
1455 {PIPE_FORMAT_B8G8R8A8_UNORM, compat_x8r8g8b8},
1456 {PIPE_FORMAT_R8_UNORM, compat_r8},
1457 {PIPE_FORMAT_R8G8_UNORM, compat_g8r8},
1458 {PIPE_FORMAT_B5G6R5_UNORM, compat_r5g6b5}
1459 };
1460
1461 /**
1462 * Debug only:
1463 * 1. check that format_cap_table[i] matches the i-th SVGA3D format.
1464 * 2. check that format_conversion_table[i].pformat == i.
1465 */
1466 static void
check_format_tables(void)1467 check_format_tables(void)
1468 {
1469 static boolean first_call = TRUE;
1470
1471 if (first_call) {
1472 unsigned i;
1473
1474 STATIC_ASSERT(ARRAY_SIZE(format_cap_table) == SVGA3D_FORMAT_MAX);
1475 for (i = 0; i < ARRAY_SIZE(format_cap_table); i++) {
1476 assert(format_cap_table[i].format == i);
1477 }
1478
1479 first_call = FALSE;
1480 }
1481 }
1482
1483
1484 /**
1485 * Return string name of an SVGA3dDevCapIndex value.
1486 * For debugging.
1487 */
1488 static const char *
svga_devcap_name(SVGA3dDevCapIndex cap)1489 svga_devcap_name(SVGA3dDevCapIndex cap)
1490 {
1491 static const struct debug_named_value devcap_names[] = {
1492 /* Note, we only list the DXFMT devcaps so far */
1493 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8R8G8B8),
1494 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8R8G8B8),
1495 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R5G6B5),
1496 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X1R5G5B5),
1497 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A1R5G5B5),
1498 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A4R4G4B4),
1499 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D32),
1500 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D16),
1501 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8),
1502 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D15S1),
1503 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8),
1504 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4),
1505 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE16),
1506 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8),
1507 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT1),
1508 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT2),
1509 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT3),
1510 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT4),
1511 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_DXT5),
1512 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPU8V8),
1513 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5),
1514 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8),
1515 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1),
1516 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S10E5),
1517 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ARGB_S23E8),
1518 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2R10G10B10),
1519 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V8U8),
1520 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Q8W8V8U8),
1521 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_CxV8U8),
1522 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X8L8V8U8),
1523 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A2W10V10U10),
1524 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ALPHA8),
1525 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S10E5),
1526 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R_S23E8),
1527 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S10E5),
1528 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_RG_S23E8),
1529 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BUFFER),
1530 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24X8),
1531 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_V16U16),
1532 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G16R16),
1533 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A16B16G16R16),
1534 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_UYVY),
1535 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YUY2),
1536 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_NV12),
1537 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS),
1538 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT),
1539 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT),
1540 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS),
1541 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT),
1542 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT),
1543 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT),
1544 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS),
1545 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT),
1546 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM),
1547 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT),
1548 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS),
1549 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_UINT),
1550 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_SINT),
1551 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS),
1552 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT),
1553 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24),
1554 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT),
1555 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS),
1556 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT),
1557 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT),
1558 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS),
1559 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM),
1560 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB),
1561 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT),
1562 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT),
1563 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS),
1564 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UINT),
1565 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SINT),
1566 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_TYPELESS),
1567 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D32_FLOAT),
1568 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_UINT),
1569 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_SINT),
1570 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS),
1571 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT),
1572 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8),
1573 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_X24_G8_UINT),
1574 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS),
1575 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UNORM),
1576 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_UINT),
1577 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SINT),
1578 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_TYPELESS),
1579 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UNORM),
1580 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_UINT),
1581 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SNORM),
1582 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_SINT),
1583 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_TYPELESS),
1584 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UNORM),
1585 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_UINT),
1586 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SNORM),
1587 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8_SINT),
1588 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_P8),
1589 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP),
1590 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM),
1591 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM),
1592 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS),
1593 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB),
1594 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS),
1595 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB),
1596 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS),
1597 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB),
1598 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS),
1599 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI1),
1600 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_SNORM),
1601 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS),
1602 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_ATI2),
1603 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_SNORM),
1604 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM),
1605 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS),
1606 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB),
1607 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS),
1608 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB),
1609 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF16),
1610 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_DF24),
1611 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT),
1612 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_YV12),
1613 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT),
1614 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT),
1615 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM),
1616 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT),
1617 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM),
1618 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM),
1619 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT),
1620 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_UNORM),
1621 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16G16_SNORM),
1622 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R32_FLOAT),
1623 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R8G8_SNORM),
1624 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_R16_FLOAT),
1625 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_D16_UNORM),
1626 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_A8_UNORM),
1627 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC1_UNORM),
1628 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC2_UNORM),
1629 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC3_UNORM),
1630 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM),
1631 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM),
1632 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM),
1633 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM),
1634 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC4_UNORM),
1635 DEBUG_NAMED_VALUE(SVGA3D_DEVCAP_DXFMT_BC5_UNORM),
1636 DEBUG_NAMED_VALUE_END,
1637 };
1638 return debug_dump_enum(devcap_names, cap);
1639 }
1640
1641
1642 /**
1643 * Return string for a bitmask of name of SVGA3D_DXFMT_x flags.
1644 * For debugging.
1645 */
1646 static const char *
svga_devcap_format_flags(unsigned flags)1647 svga_devcap_format_flags(unsigned flags)
1648 {
1649 static const struct debug_named_value devcap_flags[] = {
1650 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SUPPORTED),
1651 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_SHADER_SAMPLE),
1652 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_COLOR_RENDERTARGET),
1653 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DEPTH_RENDERTARGET),
1654 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_BLENDABLE),
1655 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MIPS),
1656 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_ARRAY),
1657 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_VOLUME),
1658 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_DX_VERTEX_BUFFER),
1659 DEBUG_NAMED_VALUE(SVGA3D_DXFMT_MULTISAMPLE),
1660 DEBUG_NAMED_VALUE_END
1661 };
1662
1663 return debug_dump_flags(devcap_flags, flags);
1664 }
1665
1666
1667 /*
1668 * Get format capabilities from the host. It takes in consideration
1669 * deprecated/unsupported formats, and formats which are implicitely assumed to
1670 * be supported when the host does not provide an explicit capability entry.
1671 */
1672 void
svga_get_format_cap(struct svga_screen * ss,SVGA3dSurfaceFormat format,SVGA3dSurfaceFormatCaps * caps)1673 svga_get_format_cap(struct svga_screen *ss,
1674 SVGA3dSurfaceFormat format,
1675 SVGA3dSurfaceFormatCaps *caps)
1676 {
1677 struct svga_winsys_screen *sws = ss->sws;
1678 SVGA3dDevCapResult result;
1679 const struct format_cap *entry;
1680
1681 #ifdef DEBUG
1682 check_format_tables();
1683 #else
1684 (void) check_format_tables;
1685 #endif
1686
1687 assert(format < ARRAY_SIZE(format_cap_table));
1688 entry = &format_cap_table[format];
1689 assert(entry->format == format);
1690
1691 if (entry->devcap && sws->get_cap(sws, entry->devcap, &result)) {
1692 assert(format < SVGA3D_UYVY || entry->defaultOperations == 0);
1693 caps->value = result.u;
1694 } else {
1695 /* Implicitly advertised format -- use default caps */
1696 caps->value = entry->defaultOperations;
1697 }
1698 }
1699
1700
1701 /*
1702 * Get DX format capabilities from VGPU10 device.
1703 */
1704 static void
svga_get_dx_format_cap(struct svga_screen * ss,SVGA3dSurfaceFormat format,SVGA3dDevCapResult * caps)1705 svga_get_dx_format_cap(struct svga_screen *ss,
1706 SVGA3dSurfaceFormat format,
1707 SVGA3dDevCapResult *caps)
1708 {
1709 struct svga_winsys_screen *sws = ss->sws;
1710 const struct format_cap *entry;
1711
1712 #ifdef DEBUG
1713 check_format_tables();
1714 #else
1715 (void) check_format_tables;
1716 #endif
1717
1718 assert(sws->have_vgpu10);
1719 assert(format < ARRAY_SIZE(format_cap_table));
1720 entry = &format_cap_table[format];
1721 assert(entry->format == format);
1722 assert(entry->devcap > SVGA3D_DEVCAP_DXCONTEXT);
1723
1724 caps->u = 0;
1725 if (entry->devcap) {
1726 sws->get_cap(sws, entry->devcap, caps);
1727
1728 /* pre-SM41 capable svga device supports SHADER_SAMPLE capability for
1729 * these formats but does not advertise the devcap.
1730 * So enable this bit here.
1731 */
1732 if (!sws->have_sm4_1 &&
1733 (format == SVGA3D_R32_FLOAT_X8X24 ||
1734 format == SVGA3D_R24_UNORM_X8)) {
1735 caps->u |= SVGA3D_DXFMT_SHADER_SAMPLE;
1736 }
1737 }
1738 else {
1739 caps->u = entry->defaultOperations;
1740 }
1741
1742 if (0) {
1743 debug_printf("Format %s, devcap %s = 0x%x (%s)\n",
1744 svga_format_name(format),
1745 svga_devcap_name(entry->devcap),
1746 caps->u,
1747 svga_devcap_format_flags(caps->u));
1748 }
1749 }
1750
1751
1752 void
svga_format_size(SVGA3dSurfaceFormat format,unsigned * block_width,unsigned * block_height,unsigned * bytes_per_block)1753 svga_format_size(SVGA3dSurfaceFormat format,
1754 unsigned *block_width,
1755 unsigned *block_height,
1756 unsigned *bytes_per_block)
1757 {
1758 assert(format < ARRAY_SIZE(format_cap_table));
1759 *block_width = format_cap_table[format].block_width;
1760 *block_height = format_cap_table[format].block_height;
1761 *bytes_per_block = format_cap_table[format].block_bytes;
1762 /* Make sure the table entry was valid */
1763 if (*block_width == 0)
1764 debug_printf("Bad table entry for %s\n", svga_format_name(format));
1765 assert(*block_width);
1766 assert(*block_height);
1767 assert(*bytes_per_block);
1768 }
1769
1770
1771 const char *
svga_format_name(SVGA3dSurfaceFormat format)1772 svga_format_name(SVGA3dSurfaceFormat format)
1773 {
1774 assert(format < ARRAY_SIZE(format_cap_table));
1775 return format_cap_table[format].name;
1776 }
1777
1778
1779 /**
1780 * Is the given SVGA3dSurfaceFormat a signed or unsigned integer color format?
1781 */
1782 boolean
svga_format_is_integer(SVGA3dSurfaceFormat format)1783 svga_format_is_integer(SVGA3dSurfaceFormat format)
1784 {
1785 switch (format) {
1786 case SVGA3D_R32G32B32A32_SINT:
1787 case SVGA3D_R32G32B32_SINT:
1788 case SVGA3D_R32G32_SINT:
1789 case SVGA3D_R32_SINT:
1790 case SVGA3D_R16G16B16A16_SINT:
1791 case SVGA3D_R16G16_SINT:
1792 case SVGA3D_R16_SINT:
1793 case SVGA3D_R8G8B8A8_SINT:
1794 case SVGA3D_R8G8_SINT:
1795 case SVGA3D_R8_SINT:
1796 case SVGA3D_R32G32B32A32_UINT:
1797 case SVGA3D_R32G32B32_UINT:
1798 case SVGA3D_R32G32_UINT:
1799 case SVGA3D_R32_UINT:
1800 case SVGA3D_R16G16B16A16_UINT:
1801 case SVGA3D_R16G16_UINT:
1802 case SVGA3D_R16_UINT:
1803 case SVGA3D_R8G8B8A8_UINT:
1804 case SVGA3D_R8G8_UINT:
1805 case SVGA3D_R8_UINT:
1806 case SVGA3D_R10G10B10A2_UINT:
1807 return TRUE;
1808 default:
1809 return FALSE;
1810 }
1811 }
1812
1813 boolean
svga_format_support_gen_mips(enum pipe_format format)1814 svga_format_support_gen_mips(enum pipe_format format)
1815 {
1816 const struct vgpu10_format_entry *entry = svga_format_entry(format);
1817
1818 return (entry->flags & TF_GEN_MIPS) > 0;
1819 }
1820
1821
1822 /**
1823 * Given a texture format, return the expected data type returned from
1824 * the texture sampler. For example, UNORM8 formats return floating point
1825 * values while SINT formats returned signed integer values.
1826 * Note: this function could be moved into the gallum u_format.[ch] code
1827 * if it's useful to anyone else.
1828 */
1829 enum tgsi_return_type
svga_get_texture_datatype(enum pipe_format format)1830 svga_get_texture_datatype(enum pipe_format format)
1831 {
1832 const struct util_format_description *desc = util_format_description(format);
1833 enum tgsi_return_type t;
1834
1835 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN ) {
1836 if (util_format_is_depth_or_stencil(format)) {
1837 t = TGSI_RETURN_TYPE_FLOAT; /* XXX revisit this */
1838 }
1839 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_FLOAT) {
1840 t = TGSI_RETURN_TYPE_FLOAT;
1841 }
1842 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1843 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_UNORM : TGSI_RETURN_TYPE_UINT;
1844 }
1845 else if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) {
1846 t = desc->channel[0].normalized ? TGSI_RETURN_TYPE_SNORM : TGSI_RETURN_TYPE_SINT;
1847 }
1848 else {
1849 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1850 t = TGSI_RETURN_TYPE_FLOAT;
1851 }
1852 }
1853 else {
1854 /* compressed format, shared exponent format, etc. */
1855 switch (format) {
1856 case PIPE_FORMAT_DXT1_RGB:
1857 case PIPE_FORMAT_DXT1_RGBA:
1858 case PIPE_FORMAT_DXT3_RGBA:
1859 case PIPE_FORMAT_DXT5_RGBA:
1860 case PIPE_FORMAT_DXT1_SRGB:
1861 case PIPE_FORMAT_DXT1_SRGBA:
1862 case PIPE_FORMAT_DXT3_SRGBA:
1863 case PIPE_FORMAT_DXT5_SRGBA:
1864 case PIPE_FORMAT_RGTC1_UNORM:
1865 case PIPE_FORMAT_RGTC2_UNORM:
1866 case PIPE_FORMAT_LATC1_UNORM:
1867 case PIPE_FORMAT_LATC2_UNORM:
1868 case PIPE_FORMAT_ETC1_RGB8:
1869 t = TGSI_RETURN_TYPE_UNORM;
1870 break;
1871 case PIPE_FORMAT_RGTC1_SNORM:
1872 case PIPE_FORMAT_RGTC2_SNORM:
1873 case PIPE_FORMAT_LATC1_SNORM:
1874 case PIPE_FORMAT_LATC2_SNORM:
1875 case PIPE_FORMAT_R10G10B10X2_SNORM:
1876 t = TGSI_RETURN_TYPE_SNORM;
1877 break;
1878 case PIPE_FORMAT_R11G11B10_FLOAT:
1879 case PIPE_FORMAT_R9G9B9E5_FLOAT:
1880 t = TGSI_RETURN_TYPE_FLOAT;
1881 break;
1882 default:
1883 assert(!"Unexpected channel type in svga_get_texture_datatype()");
1884 t = TGSI_RETURN_TYPE_FLOAT;
1885 }
1886 }
1887
1888 return t;
1889 }
1890
1891
1892 /**
1893 * Given an svga context, return true iff there are currently any integer color
1894 * buffers attached to the framebuffer.
1895 */
1896 boolean
svga_has_any_integer_cbufs(const struct svga_context * svga)1897 svga_has_any_integer_cbufs(const struct svga_context *svga)
1898 {
1899 unsigned i;
1900 for (i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
1901 struct pipe_surface *cbuf = svga->curr.framebuffer.cbufs[i];
1902
1903 if (cbuf && util_format_is_pure_integer(cbuf->format)) {
1904 return TRUE;
1905 }
1906 }
1907 return FALSE;
1908 }
1909
1910
1911 /**
1912 * Given an SVGA format, return the corresponding typeless format.
1913 * If there is no typeless format, return the format unchanged.
1914 */
1915 SVGA3dSurfaceFormat
svga_typeless_format(SVGA3dSurfaceFormat format)1916 svga_typeless_format(SVGA3dSurfaceFormat format)
1917 {
1918 switch (format) {
1919 case SVGA3D_R32G32B32A32_UINT:
1920 case SVGA3D_R32G32B32A32_SINT:
1921 case SVGA3D_R32G32B32A32_FLOAT:
1922 case SVGA3D_R32G32B32A32_TYPELESS:
1923 return SVGA3D_R32G32B32A32_TYPELESS;
1924 case SVGA3D_R32G32B32_FLOAT:
1925 case SVGA3D_R32G32B32_UINT:
1926 case SVGA3D_R32G32B32_SINT:
1927 case SVGA3D_R32G32B32_TYPELESS:
1928 return SVGA3D_R32G32B32_TYPELESS;
1929 case SVGA3D_R16G16B16A16_UINT:
1930 case SVGA3D_R16G16B16A16_UNORM:
1931 case SVGA3D_R16G16B16A16_SNORM:
1932 case SVGA3D_R16G16B16A16_SINT:
1933 case SVGA3D_R16G16B16A16_FLOAT:
1934 case SVGA3D_R16G16B16A16_TYPELESS:
1935 return SVGA3D_R16G16B16A16_TYPELESS;
1936 case SVGA3D_R32G32_UINT:
1937 case SVGA3D_R32G32_SINT:
1938 case SVGA3D_R32G32_FLOAT:
1939 case SVGA3D_R32G32_TYPELESS:
1940 return SVGA3D_R32G32_TYPELESS;
1941 case SVGA3D_D32_FLOAT_S8X24_UINT:
1942 case SVGA3D_X32_G8X24_UINT:
1943 case SVGA3D_R32G8X24_TYPELESS:
1944 return SVGA3D_R32G8X24_TYPELESS;
1945 case SVGA3D_R10G10B10A2_UINT:
1946 case SVGA3D_R10G10B10A2_UNORM:
1947 case SVGA3D_R10G10B10A2_TYPELESS:
1948 return SVGA3D_R10G10B10A2_TYPELESS;
1949 case SVGA3D_R8G8B8A8_UNORM:
1950 case SVGA3D_R8G8B8A8_SNORM:
1951 case SVGA3D_R8G8B8A8_UNORM_SRGB:
1952 case SVGA3D_R8G8B8A8_UINT:
1953 case SVGA3D_R8G8B8A8_SINT:
1954 case SVGA3D_R8G8B8A8_TYPELESS:
1955 return SVGA3D_R8G8B8A8_TYPELESS;
1956 case SVGA3D_R16G16_UINT:
1957 case SVGA3D_R16G16_SINT:
1958 case SVGA3D_R16G16_UNORM:
1959 case SVGA3D_R16G16_SNORM:
1960 case SVGA3D_R16G16_FLOAT:
1961 case SVGA3D_R16G16_TYPELESS:
1962 return SVGA3D_R16G16_TYPELESS;
1963 case SVGA3D_D32_FLOAT:
1964 case SVGA3D_R32_FLOAT:
1965 case SVGA3D_R32_UINT:
1966 case SVGA3D_R32_SINT:
1967 case SVGA3D_R32_TYPELESS:
1968 return SVGA3D_R32_TYPELESS;
1969 case SVGA3D_D24_UNORM_S8_UINT:
1970 case SVGA3D_R24G8_TYPELESS:
1971 return SVGA3D_R24G8_TYPELESS;
1972 case SVGA3D_X24_G8_UINT:
1973 return SVGA3D_R24_UNORM_X8;
1974 case SVGA3D_R8G8_UNORM:
1975 case SVGA3D_R8G8_SNORM:
1976 case SVGA3D_R8G8_UINT:
1977 case SVGA3D_R8G8_SINT:
1978 case SVGA3D_R8G8_TYPELESS:
1979 return SVGA3D_R8G8_TYPELESS;
1980 case SVGA3D_D16_UNORM:
1981 case SVGA3D_R16_UNORM:
1982 case SVGA3D_R16_UINT:
1983 case SVGA3D_R16_SNORM:
1984 case SVGA3D_R16_SINT:
1985 case SVGA3D_R16_FLOAT:
1986 case SVGA3D_R16_TYPELESS:
1987 return SVGA3D_R16_TYPELESS;
1988 case SVGA3D_R8_UNORM:
1989 case SVGA3D_R8_UINT:
1990 case SVGA3D_R8_SNORM:
1991 case SVGA3D_R8_SINT:
1992 case SVGA3D_R8_TYPELESS:
1993 return SVGA3D_R8_TYPELESS;
1994 case SVGA3D_B8G8R8A8_UNORM_SRGB:
1995 case SVGA3D_B8G8R8A8_UNORM:
1996 case SVGA3D_B8G8R8A8_TYPELESS:
1997 return SVGA3D_B8G8R8A8_TYPELESS;
1998 case SVGA3D_B8G8R8X8_UNORM_SRGB:
1999 case SVGA3D_B8G8R8X8_UNORM:
2000 case SVGA3D_B8G8R8X8_TYPELESS:
2001 return SVGA3D_B8G8R8X8_TYPELESS;
2002 case SVGA3D_BC1_UNORM:
2003 case SVGA3D_BC1_UNORM_SRGB:
2004 case SVGA3D_BC1_TYPELESS:
2005 return SVGA3D_BC1_TYPELESS;
2006 case SVGA3D_BC2_UNORM:
2007 case SVGA3D_BC2_UNORM_SRGB:
2008 case SVGA3D_BC2_TYPELESS:
2009 return SVGA3D_BC2_TYPELESS;
2010 case SVGA3D_BC3_UNORM:
2011 case SVGA3D_BC3_UNORM_SRGB:
2012 case SVGA3D_BC3_TYPELESS:
2013 return SVGA3D_BC3_TYPELESS;
2014 case SVGA3D_BC4_UNORM:
2015 case SVGA3D_BC4_SNORM:
2016 case SVGA3D_BC4_TYPELESS:
2017 return SVGA3D_BC4_TYPELESS;
2018 case SVGA3D_BC5_UNORM:
2019 case SVGA3D_BC5_SNORM:
2020 case SVGA3D_BC5_TYPELESS:
2021 return SVGA3D_BC5_TYPELESS;
2022 case SVGA3D_BC6H_UF16:
2023 case SVGA3D_BC6H_SF16:
2024 case SVGA3D_BC6H_TYPELESS:
2025 return SVGA3D_BC6H_TYPELESS;
2026 case SVGA3D_BC7_UNORM:
2027 case SVGA3D_BC7_UNORM_SRGB:
2028 case SVGA3D_BC7_TYPELESS:
2029 return SVGA3D_BC7_TYPELESS;
2030 case SVGA3D_R11G11B10_FLOAT:
2031 case SVGA3D_R11G11B10_TYPELESS:
2032 return SVGA3D_R11G11B10_TYPELESS;
2033
2034 /* Special cases (no corresponding _TYPELESS formats) */
2035 case SVGA3D_A8_UNORM:
2036 case SVGA3D_B5G5R5A1_UNORM:
2037 case SVGA3D_B5G6R5_UNORM:
2038 case SVGA3D_R9G9B9E5_SHAREDEXP:
2039 return format;
2040 default:
2041 debug_printf("Unexpected format %s in %s\n",
2042 svga_format_name(format), __FUNCTION__);
2043 return format;
2044 }
2045 }
2046
2047
2048 /**
2049 * Given a surface format, return the corresponding format to use for
2050 * a texture sampler. In most cases, it's the format unchanged, but there
2051 * are some special cases.
2052 */
2053 SVGA3dSurfaceFormat
svga_sampler_format(SVGA3dSurfaceFormat format)2054 svga_sampler_format(SVGA3dSurfaceFormat format)
2055 {
2056 switch (format) {
2057 case SVGA3D_D16_UNORM:
2058 return SVGA3D_R16_UNORM;
2059 case SVGA3D_D24_UNORM_S8_UINT:
2060 return SVGA3D_R24_UNORM_X8;
2061 case SVGA3D_D32_FLOAT:
2062 return SVGA3D_R32_FLOAT;
2063 case SVGA3D_D32_FLOAT_S8X24_UINT:
2064 return SVGA3D_R32_FLOAT_X8X24;
2065 default:
2066 return format;
2067 }
2068 }
2069
2070
2071 /**
2072 * Is the given format an uncompressed snorm format?
2073 */
2074 bool
svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)2075 svga_format_is_uncompressed_snorm(SVGA3dSurfaceFormat format)
2076 {
2077 switch (format) {
2078 case SVGA3D_R8G8B8A8_SNORM:
2079 case SVGA3D_R8G8_SNORM:
2080 case SVGA3D_R8_SNORM:
2081 case SVGA3D_R16G16B16A16_SNORM:
2082 case SVGA3D_R16G16_SNORM:
2083 case SVGA3D_R16_SNORM:
2084 return true;
2085 default:
2086 return false;
2087 }
2088 }
2089
2090
2091 bool
svga_format_is_typeless(SVGA3dSurfaceFormat format)2092 svga_format_is_typeless(SVGA3dSurfaceFormat format)
2093 {
2094 switch (format) {
2095 case SVGA3D_R32G32B32A32_TYPELESS:
2096 case SVGA3D_R32G32B32_TYPELESS:
2097 case SVGA3D_R16G16B16A16_TYPELESS:
2098 case SVGA3D_R32G32_TYPELESS:
2099 case SVGA3D_R32G8X24_TYPELESS:
2100 case SVGA3D_R10G10B10A2_TYPELESS:
2101 case SVGA3D_R8G8B8A8_TYPELESS:
2102 case SVGA3D_R16G16_TYPELESS:
2103 case SVGA3D_R32_TYPELESS:
2104 case SVGA3D_R24G8_TYPELESS:
2105 case SVGA3D_R8G8_TYPELESS:
2106 case SVGA3D_R16_TYPELESS:
2107 case SVGA3D_R8_TYPELESS:
2108 case SVGA3D_BC1_TYPELESS:
2109 case SVGA3D_BC2_TYPELESS:
2110 case SVGA3D_BC3_TYPELESS:
2111 case SVGA3D_BC4_TYPELESS:
2112 case SVGA3D_BC5_TYPELESS:
2113 case SVGA3D_BC6H_TYPELESS:
2114 case SVGA3D_BC7_TYPELESS:
2115 case SVGA3D_B8G8R8A8_TYPELESS:
2116 case SVGA3D_B8G8R8X8_TYPELESS:
2117 return true;
2118 default:
2119 return false;
2120 }
2121 }
2122
2123
2124 /**
2125 * \brief Can we import a surface with a given SVGA3D format as a texture?
2126 *
2127 * \param ss[in] pointer to the svga screen.
2128 * \param pformat[in] pipe format of the local texture.
2129 * \param sformat[in] svga3d format of the imported surface.
2130 * \param bind[in] bind flags of the imported texture.
2131 * \param verbose[in] Print out incompatibilities in debug mode.
2132 */
2133 bool
svga_format_is_shareable(const struct svga_screen * ss,enum pipe_format pformat,SVGA3dSurfaceFormat sformat,unsigned bind,bool verbose)2134 svga_format_is_shareable(const struct svga_screen *ss,
2135 enum pipe_format pformat,
2136 SVGA3dSurfaceFormat sformat,
2137 unsigned bind,
2138 bool verbose)
2139 {
2140 SVGA3dSurfaceFormat default_format =
2141 svga_translate_format(ss, pformat, bind);
2142 int i;
2143
2144 if (default_format == SVGA3D_FORMAT_INVALID)
2145 return false;
2146 if (default_format == sformat)
2147 return true;
2148
2149 for (i = 0; i < ARRAY_SIZE(format_compats); ++i) {
2150 if (format_compats[i].pformat == pformat) {
2151 const SVGA3dSurfaceFormat *compat_format =
2152 format_compats[i].compat_format;
2153 while (*compat_format != 0) {
2154 if (*compat_format == sformat)
2155 return true;
2156 compat_format++;
2157 }
2158 }
2159 }
2160
2161 if (verbose) {
2162 debug_printf("Incompatible imported surface format.\n");
2163 debug_printf("Texture format: \"%s\". Imported format: \"%s\".\n",
2164 svga_format_name(default_format),
2165 svga_format_name(sformat));
2166 }
2167
2168 return false;
2169 }
2170
2171
2172 /**
2173 * Return the sRGB format which corresponds to the given (linear) format.
2174 * If there's no such sRGB format, return the format as-is.
2175 */
2176 SVGA3dSurfaceFormat
svga_linear_to_srgb(SVGA3dSurfaceFormat format)2177 svga_linear_to_srgb(SVGA3dSurfaceFormat format)
2178 {
2179 switch (format) {
2180 case SVGA3D_R8G8B8A8_UNORM:
2181 return SVGA3D_R8G8B8A8_UNORM_SRGB;
2182 case SVGA3D_BC1_UNORM:
2183 return SVGA3D_BC1_UNORM_SRGB;
2184 case SVGA3D_BC2_UNORM:
2185 return SVGA3D_BC2_UNORM_SRGB;
2186 case SVGA3D_BC3_UNORM:
2187 return SVGA3D_BC3_UNORM_SRGB;
2188 case SVGA3D_B8G8R8A8_UNORM:
2189 return SVGA3D_B8G8R8A8_UNORM_SRGB;
2190 case SVGA3D_B8G8R8X8_UNORM:
2191 return SVGA3D_B8G8R8X8_UNORM_SRGB;
2192 default:
2193 return format;
2194 }
2195 }
2196
2197
2198 /**
2199 * Implement pipe_screen::is_format_supported().
2200 * \param bindings bitmask of PIPE_BIND_x flags
2201 */
2202 bool
svga_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)2203 svga_is_format_supported(struct pipe_screen *screen,
2204 enum pipe_format format,
2205 enum pipe_texture_target target,
2206 unsigned sample_count,
2207 unsigned storage_sample_count,
2208 unsigned bindings)
2209 {
2210 struct svga_screen *ss = svga_screen(screen);
2211 SVGA3dSurfaceFormat svga_format;
2212 SVGA3dSurfaceFormatCaps caps;
2213 SVGA3dSurfaceFormatCaps mask;
2214
2215 assert(bindings);
2216 assert(!ss->sws->have_vgpu10);
2217
2218 /* Multisamples is not supported in VGPU9 device */
2219 if (sample_count > 1)
2220 return false;
2221
2222 svga_format = svga_translate_format(ss, format, bindings);
2223 if (svga_format == SVGA3D_FORMAT_INVALID) {
2224 return false;
2225 }
2226
2227 if (util_format_is_srgb(format) &&
2228 (bindings & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_RENDER_TARGET))) {
2229 /* We only support sRGB rendering with vgpu10 */
2230 return false;
2231 }
2232
2233 /*
2234 * Override host capabilities, so that we end up with the same
2235 * visuals for all virtual hardware implementations.
2236 */
2237 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2238 switch (svga_format) {
2239 case SVGA3D_A8R8G8B8:
2240 case SVGA3D_X8R8G8B8:
2241 case SVGA3D_R5G6B5:
2242 break;
2243
2244 /* VGPU10 formats */
2245 case SVGA3D_B8G8R8A8_UNORM:
2246 case SVGA3D_B8G8R8X8_UNORM:
2247 case SVGA3D_B5G6R5_UNORM:
2248 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2249 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2250 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2251 break;
2252
2253 /* Often unsupported/problematic. This means we end up with the same
2254 * visuals for all virtual hardware implementations.
2255 */
2256 case SVGA3D_A4R4G4B4:
2257 case SVGA3D_A1R5G5B5:
2258 return false;
2259
2260 default:
2261 return false;
2262 }
2263 }
2264
2265 /*
2266 * Query the host capabilities.
2267 */
2268 svga_get_format_cap(ss, svga_format, &caps);
2269
2270 if (bindings & PIPE_BIND_RENDER_TARGET) {
2271 /* Check that the color surface is blendable, unless it's an
2272 * integer format.
2273 */
2274 if (!svga_format_is_integer(svga_format) &&
2275 (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
2276 return false;
2277 }
2278 }
2279
2280 mask.value = 0;
2281 if (bindings & PIPE_BIND_RENDER_TARGET)
2282 mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
2283
2284 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2285 mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
2286
2287 if (bindings & PIPE_BIND_SAMPLER_VIEW)
2288 mask.value |= SVGA3DFORMAT_OP_TEXTURE;
2289
2290 if (target == PIPE_TEXTURE_CUBE)
2291 mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
2292 else if (target == PIPE_TEXTURE_3D)
2293 mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
2294
2295 return (caps.value & mask.value) == mask.value;
2296 }
2297
2298
2299 /**
2300 * Implement pipe_screen::is_format_supported() for VGPU10 device.
2301 * \param bindings bitmask of PIPE_BIND_x flags
2302 */
2303 bool
svga_is_dx_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)2304 svga_is_dx_format_supported(struct pipe_screen *screen,
2305 enum pipe_format format,
2306 enum pipe_texture_target target,
2307 unsigned sample_count,
2308 unsigned storage_sample_count,
2309 unsigned bindings)
2310 {
2311 struct svga_screen *ss = svga_screen(screen);
2312 SVGA3dSurfaceFormat svga_format;
2313 SVGA3dDevCapResult caps;
2314 unsigned int mask = 0;
2315
2316 assert(bindings);
2317 assert(ss->sws->have_vgpu10);
2318
2319 /* To support framebuffer without attachments */
2320 if ((format == PIPE_FORMAT_NONE) && (bindings == PIPE_BIND_RENDER_TARGET))
2321 return (ss->sws->have_gl43 && (sample_count <= ss->forcedSampleCount));
2322
2323 if (sample_count > 1) {
2324
2325 /* No MSAA support for shader image */
2326 if (bindings & PIPE_BIND_SHADER_IMAGE)
2327 return false;
2328
2329 /* In ms_samples, if bit N is set it means that we support
2330 * multisample with N+1 samples per pixel.
2331 */
2332 if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
2333 return false;
2334 }
2335 mask |= SVGA3D_DXFMT_MULTISAMPLE;
2336 }
2337
2338 /*
2339 * For VGPU10 vertex formats, skip querying host capabilities
2340 */
2341
2342 if (bindings & PIPE_BIND_VERTEX_BUFFER) {
2343 unsigned flags;
2344 svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
2345 return svga_format != SVGA3D_FORMAT_INVALID;
2346 }
2347
2348 if (bindings & PIPE_BIND_SAMPLER_VIEW && target == PIPE_BUFFER) {
2349 unsigned flags;
2350 svga_translate_texture_buffer_view_format(format, &svga_format, &flags);
2351 return svga_format != SVGA3D_FORMAT_INVALID;
2352 }
2353
2354 svga_format = svga_translate_format(ss, format, bindings);
2355 if (svga_format == SVGA3D_FORMAT_INVALID) {
2356 return false;
2357 }
2358
2359 /*
2360 * Override host capabilities, so that we end up with the same
2361 * visuals for all virtual hardware implementations.
2362 */
2363 if (bindings & PIPE_BIND_DISPLAY_TARGET) {
2364 switch (svga_format) {
2365 case SVGA3D_A8R8G8B8:
2366 case SVGA3D_X8R8G8B8:
2367 case SVGA3D_R5G6B5:
2368 break;
2369
2370 /* VGPU10 formats */
2371 case SVGA3D_B8G8R8A8_UNORM:
2372 case SVGA3D_B8G8R8X8_UNORM:
2373 case SVGA3D_B5G6R5_UNORM:
2374 case SVGA3D_B8G8R8X8_UNORM_SRGB:
2375 case SVGA3D_B8G8R8A8_UNORM_SRGB:
2376 case SVGA3D_R8G8B8A8_UNORM_SRGB:
2377 break;
2378
2379 /* Often unsupported/problematic. This means we end up with the same
2380 * visuals for all virtual hardware implementations.
2381 */
2382 case SVGA3D_A4R4G4B4:
2383 case SVGA3D_A1R5G5B5:
2384 return false;
2385
2386 default:
2387 return false;
2388 }
2389 }
2390
2391 /*
2392 * Query the host capabilities.
2393 */
2394 svga_get_dx_format_cap(ss, svga_format, &caps);
2395
2396 if (bindings & PIPE_BIND_RENDER_TARGET) {
2397 /* Check that the color surface is blendable, unless it's an
2398 * integer format.
2399 */
2400 if (!(svga_format_is_integer(svga_format) ||
2401 (caps.u & SVGA3D_DXFMT_BLENDABLE))) {
2402 return false;
2403 }
2404 mask |= SVGA3D_DXFMT_COLOR_RENDERTARGET;
2405 }
2406
2407 if (bindings & PIPE_BIND_DEPTH_STENCIL)
2408 mask |= SVGA3D_DXFMT_DEPTH_RENDERTARGET;
2409
2410 switch (target) {
2411 case PIPE_TEXTURE_3D:
2412 mask |= SVGA3D_DXFMT_VOLUME;
2413 break;
2414 case PIPE_TEXTURE_1D_ARRAY:
2415 case PIPE_TEXTURE_2D_ARRAY:
2416 case PIPE_TEXTURE_CUBE_ARRAY:
2417 mask |= SVGA3D_DXFMT_ARRAY;
2418 break;
2419 default:
2420 break;
2421 }
2422
2423 /* Is the format supported for rendering */
2424 if ((caps.u & mask) != mask)
2425 return false;
2426
2427 if (bindings & PIPE_BIND_SAMPLER_VIEW) {
2428 SVGA3dSurfaceFormat sampler_format;
2429
2430 /* Get the sampler view format */
2431 sampler_format = svga_sampler_format(svga_format);
2432 if (sampler_format != svga_format) {
2433 caps.u = 0;
2434 svga_get_dx_format_cap(ss, sampler_format, &caps);
2435 mask &= SVGA3D_DXFMT_VOLUME;
2436 mask |= SVGA3D_DXFMT_SHADER_SAMPLE;
2437 if ((caps.u & mask) != mask)
2438 return false;
2439 }
2440 }
2441
2442 return true;
2443 }
2444