1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_UART_STRUCT_H_ 15 #define _SOC_UART_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct uart_dev_s { 24 union { 25 struct { 26 uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/ 27 uint8_t reserved[3]; 28 }; 29 uint32_t val; 30 } fifo; 31 union { 32 struct { 33 uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ 34 uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ 35 uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/ 36 uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/ 37 uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/ 38 uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/ 39 uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/ 40 uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/ 41 uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/ 42 uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/ 43 uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/ 44 uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects the start bit.*/ 45 uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending 0 after all the data in transmitter's fifo are send.*/ 46 uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.*/ 47 uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/ 48 uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/ 49 uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/ 50 uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/ 51 uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/ 52 uint32_t reserved19: 13; 53 }; 54 uint32_t val; 55 } int_raw; 56 union { 57 struct { 58 uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/ 59 uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/ 60 uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/ 61 uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ 62 uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/ 63 uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ 64 uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ 65 uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ 66 uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/ 67 uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ 68 uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ 69 uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/ 70 uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/ 71 uint32_t tx_brk_idle_done: 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/ 72 uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ 73 uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/ 74 uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/ 75 uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/ 76 uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/ 77 uint32_t reserved19: 13; 78 }; 79 uint32_t val; 80 } int_st; 81 union { 82 struct { 83 uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ 84 uint32_t txfifo_empty: 1; /*This is the enable bit for rxfifo_full_int_st register.*/ 85 uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/ 86 uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/ 87 uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/ 88 uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/ 89 uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/ 90 uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/ 91 uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/ 92 uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/ 93 uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/ 94 uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/ 95 uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/ 96 uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/ 97 uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/ 98 uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ 99 uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/ 100 uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/ 101 uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/ 102 uint32_t reserved19: 13; 103 }; 104 uint32_t val; 105 } int_ena; 106 union { 107 struct { 108 uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/ 109 uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/ 110 uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/ 111 uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/ 112 uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ 113 uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/ 114 uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/ 115 uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/ 116 uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ 117 uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ 118 uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/ 119 uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/ 120 uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/ 121 uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ 122 uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/ 123 uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ 124 uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ 125 uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/ 126 uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ 127 uint32_t reserved19: 13; 128 }; 129 uint32_t val; 130 } int_clr; 131 union { 132 struct { 133 uint32_t div_int: 20; /*The register value is the integer part of the frequency divider's factor.*/ 134 uint32_t div_frag: 4; /*The register value is the decimal part of the frequency divider's factor.*/ 135 uint32_t reserved24: 8; 136 }; 137 uint32_t val; 138 } clk_div; 139 union { 140 struct { 141 uint32_t en: 1; /*This is the enable bit for detecting baudrate.*/ 142 uint32_t reserved1: 7; 143 uint32_t glitch_filt: 8; /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/ 144 uint32_t reserved16: 16; 145 }; 146 uint32_t val; 147 } auto_baud; 148 union { 149 struct { 150 uint32_t rxfifo_cnt: 8; /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ 151 uint32_t st_urx_out: 4; /*This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ 152 uint32_t reserved12: 1; 153 uint32_t dsrn: 1; /*This register stores the level value of the internal uart dsr signal.*/ 154 uint32_t ctsn: 1; /*This register stores the level value of the internal uart cts signal.*/ 155 uint32_t rxd: 1; /*This register stores the level value of the internal uart rxd signal.*/ 156 uint32_t txfifo_cnt: 8; /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ 157 uint32_t st_utx_out: 4; /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ 158 uint32_t reserved28: 1; 159 uint32_t dtrn: 1; /*The register represent the level value of the internal uart dsr signal.*/ 160 uint32_t rtsn: 1; /*This register represent the level value of the internal uart cts signal.*/ 161 uint32_t txd: 1; /*This register represent the level value of the internal uart rxd signal.*/ 162 }; 163 uint32_t val; 164 } status; 165 union { 166 struct { 167 uint32_t parity: 1; /*This register is used to configure the parity check mode. 0:even 1:odd*/ 168 uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/ 169 uint32_t bit_num: 2; /*This register is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ 170 uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ 171 uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/ 172 uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control..*/ 173 uint32_t txd_brk: 1; /*Set this bit to enable transmitter to send 0 when the process of sending data is done.*/ 174 uint32_t irda_dplx: 1; /*Set this bit to enable irda loop-back mode.*/ 175 uint32_t irda_tx_en: 1; /*This is the start enable bit for irda transmitter.*/ 176 uint32_t irda_wctl: 1; /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/ 177 uint32_t irda_tx_inv: 1; /*Set this bit to inverse the level value of irda transmitter's level.*/ 178 uint32_t irda_rx_inv: 1; /*Set this bit to inverse the level value of irda receiver's level.*/ 179 uint32_t loopback: 1; /*Set this bit to enable uart loop-back test mode.*/ 180 uint32_t tx_flow_en: 1; /*Set this bit to enable transmitter's flow control function.*/ 181 uint32_t irda_en: 1; /*Set this bit to enable irda protocol.*/ 182 uint32_t rxfifo_rst: 1; /*Set this bit to reset uart receiver's fifo.*/ 183 uint32_t txfifo_rst: 1; /*Set this bit to reset uart transmitter's fifo.*/ 184 uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/ 185 uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/ 186 uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/ 187 uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/ 188 uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/ 189 uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/ 190 uint32_t clk_en: 1; /*1：force clock on for registers：support clock only when write registers*/ 191 uint32_t err_wr_mask: 1; /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the received data is wrong.*/ 192 uint32_t tick_ref_always_on: 1; /*This register is used to select the clock.1：apb clock：ref_tick*/ 193 uint32_t reserved28: 4; 194 }; 195 uint32_t val; 196 } conf0; 197 union { 198 struct { 199 uint32_t rxfifo_full_thrhd: 7; /*When receiver receives more data than its threshold value，receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ 200 uint32_t reserved7: 1; 201 uint32_t txfifo_empty_thrhd: 7; /*when the data amount in transmitter fifo is less than its threshold value， it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ 202 uint32_t reserved15: 1; 203 uint32_t rx_flow_thrhd: 7; /*when receiver receives more data than its threshold value， receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ 204 uint32_t rx_flow_en: 1; /*This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal*/ 205 uint32_t rx_tout_thrhd: 7; /*This register is used to configure the timeout value for uart receiver receiving a byte.*/ 206 uint32_t rx_tout_en: 1; /*This is the enable bit for uart receiver's timeout function.*/ 207 }; 208 uint32_t val; 209 } conf1; 210 union { 211 struct { 212 uint32_t min_cnt: 20; /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/ 213 uint32_t reserved20: 12; 214 }; 215 uint32_t val; 216 } lowpulse; 217 union { 218 struct { 219 uint32_t min_cnt: 20; /*This register stores the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/ 220 uint32_t reserved20: 12; 221 }; 222 uint32_t val; 223 } highpulse; 224 union { 225 struct { 226 uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/ 227 uint32_t reserved10: 22; 228 }; 229 uint32_t val; 230 } rxd_cnt; 231 union { 232 struct { 233 uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff .*/ 234 uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/ 235 uint32_t force_xon: 1; /*Set this bit to clear ctsn to stop the transmitter from sending data.*/ 236 uint32_t force_xoff: 1; /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/ 237 uint32_t send_xon: 1; /*Set this bit to send xon char， it is cleared by hardware automatically.*/ 238 uint32_t send_xoff: 1; /*Set this bit to send xoff char， it is cleared by hardware automatically.*/ 239 uint32_t reserved6: 26; 240 }; 241 uint32_t val; 242 } flow_conf; 243 union { 244 struct { 245 uint32_t active_threshold:10; /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/ 246 uint32_t reserved10: 22; 247 }; 248 uint32_t val; 249 } sleep_conf; 250 union { 251 struct { 252 uint32_t xon_threshold: 8; /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/ 253 uint32_t xoff_threshold: 8; /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/ 254 uint32_t xon_char: 8; /*This register stores the xon flow control char.*/ 255 uint32_t xoff_char: 8; /*This register stores the xoff flow control char.*/ 256 }; 257 uint32_t val; 258 } swfc_conf; 259 union { 260 struct { 261 uint32_t rx_idle_thrhd:10; /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/ 262 uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/ 263 uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/ 264 uint32_t reserved28: 4; 265 }; 266 uint32_t val; 267 } idle_conf; 268 union { 269 struct { 270 uint32_t en: 1; /*Set this bit to choose rs485 mode.*/ 271 uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ 272 uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/ 273 uint32_t tx_rx_en: 1; /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/ 274 uint32_t rx_busy_tx_en: 1; /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ 275 uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/ 276 uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/ 277 uint32_t reserved10: 22; 278 }; 279 uint32_t val; 280 } rs485_conf; 281 union { 282 struct { 283 uint32_t pre_idle_num:24; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ 284 uint32_t reserved24: 8; 285 }; 286 uint32_t val; 287 } at_cmd_precnt; 288 union { 289 struct { 290 uint32_t post_idle_num:24; /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value it will not take the previous data as at_cmd char.*/ 291 uint32_t reserved24: 8; 292 }; 293 uint32_t val; 294 } at_cmd_postcnt; 295 union { 296 struct { 297 uint32_t rx_gap_tout:24; /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/ 298 uint32_t reserved24: 8; 299 }; 300 uint32_t val; 301 } at_cmd_gaptout; 302 union { 303 struct { 304 uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/ 305 uint32_t char_num: 8; /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/ 306 uint32_t reserved16: 16; 307 }; 308 uint32_t val; 309 } at_cmd_char; 310 union { 311 struct { 312 uint32_t mem_pd: 1; /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1 memory will enter low power mode.*/ 313 uint32_t reserved1: 1; 314 uint32_t reserved2: 1; 315 uint32_t rx_size: 4; /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/ 316 uint32_t tx_size: 4; /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/ 317 uint32_t reserved11: 4; 318 uint32_t rx_flow_thrhd_h3: 3; /*refer to the rx_flow_thrhd's description.*/ 319 uint32_t rx_tout_thrhd_h3: 3; /*refer to the rx_tout_thrhd's description.*/ 320 uint32_t xon_threshold_h2: 2; /*refer to the uart_xon_threshold's description.*/ 321 uint32_t xoff_threshold_h2: 2; /*refer to the uart_xoff_threshold's description.*/ 322 uint32_t rx_mem_full_thrhd: 3; /*refer to the rxfifo_full_thrhd's description.*/ 323 uint32_t tx_mem_empty_thrhd: 3; /*refer to txfifo_empty_thrhd 's description.*/ 324 uint32_t reserved31: 1; 325 }; 326 uint32_t val; 327 } mem_conf; 328 union { 329 struct { 330 uint32_t status:24; 331 uint32_t reserved24: 8; 332 }; 333 uint32_t val; 334 } mem_tx_status; 335 union { 336 struct { 337 uint32_t status: 24; 338 uint32_t reserved24: 8; 339 }; 340 struct { 341 uint32_t reserved0: 2; 342 uint32_t rd_addr: 11; /*This register stores the rx mem read address.*/ 343 uint32_t wr_addr: 11; /*This register stores the rx mem write address.*/ 344 uint32_t reserved: 8; 345 }; 346 uint32_t val; 347 } mem_rx_status; 348 union { 349 struct { 350 uint32_t rx_cnt: 3; /*refer to the rxfifo_cnt's description.*/ 351 uint32_t tx_cnt: 3; /*refer to the txfifo_cnt's description.*/ 352 uint32_t reserved6: 26; 353 }; 354 uint32_t val; 355 } mem_cnt_status; 356 union { 357 struct { 358 uint32_t min_cnt: 20; /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/ 359 uint32_t reserved20: 12; 360 }; 361 uint32_t val; 362 } pospulse; 363 union { 364 struct { 365 uint32_t min_cnt: 20; /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/ 366 uint32_t reserved20: 12; 367 }; 368 uint32_t val; 369 } negpulse; 370 uint32_t reserved_70; 371 uint32_t reserved_74; 372 uint32_t date; /**/ 373 uint32_t id; /**/ 374 } uart_dev_t; 375 extern uart_dev_t UART0; 376 extern uart_dev_t UART1; 377 extern uart_dev_t UART2; 378 379 #ifdef __cplusplus 380 } 381 #endif 382 383 #endif /* _SOC_UART_STRUCT_H_ */ 384