1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel Transactional Synchronization Extensions (TSX) control.
4 *
5 * Copyright (C) 2019 Intel Corporation
6 *
7 * Author:
8 * Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
9 */
10
11 #include <linux/cpufeature.h>
12
13 #include <asm/cmdline.h>
14
15 #include "cpu.h"
16
17 #undef pr_fmt
18 #define pr_fmt(fmt) "tsx: " fmt
19
20 enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
21
tsx_disable(void)22 void tsx_disable(void)
23 {
24 u64 tsx;
25
26 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
27
28 /* Force all transactions to immediately abort */
29 tsx |= TSX_CTRL_RTM_DISABLE;
30
31 /*
32 * Ensure TSX support is not enumerated in CPUID.
33 * This is visible to userspace and will ensure they
34 * do not waste resources trying TSX transactions that
35 * will always abort.
36 */
37 tsx |= TSX_CTRL_CPUID_CLEAR;
38
39 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
40 }
41
tsx_enable(void)42 void tsx_enable(void)
43 {
44 u64 tsx;
45
46 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
47
48 /* Enable the RTM feature in the cpu */
49 tsx &= ~TSX_CTRL_RTM_DISABLE;
50
51 /*
52 * Ensure TSX support is enumerated in CPUID.
53 * This is visible to userspace and will ensure they
54 * can enumerate and use the TSX feature.
55 */
56 tsx &= ~TSX_CTRL_CPUID_CLEAR;
57
58 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
59 }
60
x86_get_tsx_auto_mode(void)61 static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
62 {
63 if (boot_cpu_has_bug(X86_BUG_TAA))
64 return TSX_CTRL_DISABLE;
65
66 return TSX_CTRL_ENABLE;
67 }
68
tsx_init(void)69 void __init tsx_init(void)
70 {
71 char arg[5] = {};
72 int ret;
73
74 /*
75 * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
76 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
77 *
78 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
79 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
80 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
81 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
82 * tsx= cmdline requests will do nothing on CPUs without
83 * MSR_IA32_TSX_CTRL support.
84 */
85 if (!(x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR))
86 return;
87
88 setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL);
89
90 ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
91 if (ret >= 0) {
92 if (!strcmp(arg, "on")) {
93 tsx_ctrl_state = TSX_CTRL_ENABLE;
94 } else if (!strcmp(arg, "off")) {
95 tsx_ctrl_state = TSX_CTRL_DISABLE;
96 } else if (!strcmp(arg, "auto")) {
97 tsx_ctrl_state = x86_get_tsx_auto_mode();
98 } else {
99 tsx_ctrl_state = TSX_CTRL_DISABLE;
100 pr_err("invalid option, defaulting to off\n");
101 }
102 } else {
103 /* tsx= not provided */
104 if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
105 tsx_ctrl_state = x86_get_tsx_auto_mode();
106 else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
107 tsx_ctrl_state = TSX_CTRL_DISABLE;
108 else
109 tsx_ctrl_state = TSX_CTRL_ENABLE;
110 }
111
112 if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
113 tsx_disable();
114
115 /*
116 * tsx_disable() will change the state of the RTM and HLE CPUID
117 * bits. Clear them here since they are now expected to be not
118 * set.
119 */
120 setup_clear_cpu_cap(X86_FEATURE_RTM);
121 setup_clear_cpu_cap(X86_FEATURE_HLE);
122 } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
123
124 /*
125 * HW defaults TSX to be enabled at bootup.
126 * We may still need the TSX enable support
127 * during init for special cases like
128 * kexec after TSX is disabled.
129 */
130 tsx_enable();
131
132 /*
133 * tsx_enable() will change the state of the RTM and HLE CPUID
134 * bits. Force them here since they are now expected to be set.
135 */
136 setup_force_cpu_cap(X86_FEATURE_RTM);
137 setup_force_cpu_cap(X86_FEATURE_HLE);
138 }
139 }
140