1 ir_function_signature *
udivmod64(void * mem_ctx,builtin_available_predicate avail)2 udivmod64(void *mem_ctx, builtin_available_predicate avail)
3 {
4 ir_function_signature *const sig =
5 new(mem_ctx) ir_function_signature(glsl_type::uvec4_type, avail);
6 ir_factory body(&sig->body, mem_ctx);
7 sig->is_defined = true;
8
9 exec_list sig_parameters;
10
11 ir_variable *const r000C = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "n", ir_var_function_in);
12 sig_parameters.push_tail(r000C);
13 ir_variable *const r000D = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "d", ir_var_function_in);
14 sig_parameters.push_tail(r000D);
15 ir_variable *const r000E = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
16 body.emit(r000E);
17 ir_variable *const r000F = new(mem_ctx) ir_variable(glsl_type::uint64_t_type, "n64", ir_var_auto);
18 body.emit(r000F);
19 ir_variable *const r0010 = new(mem_ctx) ir_variable(glsl_type::int_type, "log2_denom", ir_var_auto);
20 body.emit(r0010);
21 ir_variable *const r0011 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "quot", ir_var_auto);
22 body.emit(r0011);
23 body.emit(assign(r0011, ir_constant::zero(mem_ctx, glsl_type::uvec2_type), 0x03));
24
25 ir_expression *const r0012 = expr(ir_unop_find_msb, swizzle_y(r000D));
26 body.emit(assign(r0010, add(r0012, body.constant(int(32))), 0x01));
27
28 /* IF CONDITION */
29 ir_expression *const r0014 = equal(swizzle_y(r000D), body.constant(0u));
30 ir_expression *const r0015 = gequal(swizzle_y(r000C), swizzle_x(r000D));
31 ir_expression *const r0016 = logic_and(r0014, r0015);
32 ir_if *f0013 = new(mem_ctx) ir_if(operand(r0016).val);
33 exec_list *const f0013_parent_instructions = body.instructions;
34
35 /* THEN INSTRUCTIONS */
36 body.instructions = &f0013->then_instructions;
37
38 ir_variable *const r0017 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
39 body.emit(r0017);
40 ir_variable *const r0018 = body.make_temp(glsl_type::int_type, "findMSB_retval");
41 body.emit(assign(r0018, expr(ir_unop_find_msb, swizzle_x(r000D)), 0x01));
42
43 body.emit(assign(r0010, r0018, 0x01));
44
45 body.emit(assign(r0017, body.constant(int(31)), 0x01));
46
47 /* LOOP BEGIN */
48 ir_loop *f0019 = new(mem_ctx) ir_loop();
49 exec_list *const f0019_parent_instructions = body.instructions;
50
51 body.instructions = &f0019->body_instructions;
52
53 /* IF CONDITION */
54 ir_expression *const r001B = less(r0017, body.constant(int(1)));
55 ir_if *f001A = new(mem_ctx) ir_if(operand(r001B).val);
56 exec_list *const f001A_parent_instructions = body.instructions;
57
58 /* THEN INSTRUCTIONS */
59 body.instructions = &f001A->then_instructions;
60
61 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
62
63
64 body.instructions = f001A_parent_instructions;
65 body.emit(f001A);
66
67 /* END IF */
68
69 /* IF CONDITION */
70 ir_expression *const r001D = sub(body.constant(int(31)), r0017);
71 ir_expression *const r001E = lequal(r0018, r001D);
72 ir_expression *const r001F = lshift(swizzle_x(r000D), r0017);
73 ir_expression *const r0020 = lequal(r001F, swizzle_y(r000C));
74 ir_expression *const r0021 = logic_and(r001E, r0020);
75 ir_if *f001C = new(mem_ctx) ir_if(operand(r0021).val);
76 exec_list *const f001C_parent_instructions = body.instructions;
77
78 /* THEN INSTRUCTIONS */
79 body.instructions = &f001C->then_instructions;
80
81 ir_expression *const r0022 = lshift(swizzle_x(r000D), r0017);
82 body.emit(assign(r000C, sub(swizzle_y(r000C), r0022), 0x02));
83
84 ir_expression *const r0023 = lshift(body.constant(1u), r0017);
85 body.emit(assign(r0011, bit_or(swizzle_y(r0011), r0023), 0x02));
86
87
88 body.instructions = f001C_parent_instructions;
89 body.emit(f001C);
90
91 /* END IF */
92
93 body.emit(assign(r0017, add(r0017, body.constant(int(-1))), 0x01));
94
95 /* LOOP END */
96
97 body.instructions = f0019_parent_instructions;
98 body.emit(f0019);
99
100 /* IF CONDITION */
101 ir_expression *const r0025 = lequal(swizzle_x(r000D), swizzle_y(r000C));
102 ir_if *f0024 = new(mem_ctx) ir_if(operand(r0025).val);
103 exec_list *const f0024_parent_instructions = body.instructions;
104
105 /* THEN INSTRUCTIONS */
106 body.instructions = &f0024->then_instructions;
107
108 body.emit(assign(r000C, sub(swizzle_y(r000C), swizzle_x(r000D)), 0x02));
109
110 body.emit(assign(r0011, bit_or(swizzle_y(r0011), body.constant(1u)), 0x02));
111
112
113 body.instructions = f0024_parent_instructions;
114 body.emit(f0024);
115
116 /* END IF */
117
118
119 body.instructions = f0013_parent_instructions;
120 body.emit(f0013);
121
122 /* END IF */
123
124 ir_variable *const r0026 = body.make_temp(glsl_type::uint64_t_type, "packUint2x32_retval");
125 body.emit(assign(r0026, expr(ir_unop_pack_uint_2x32, r000D), 0x01));
126
127 body.emit(assign(r000F, expr(ir_unop_pack_uint_2x32, r000C), 0x01));
128
129 body.emit(assign(r000E, body.constant(int(31)), 0x01));
130
131 /* LOOP BEGIN */
132 ir_loop *f0027 = new(mem_ctx) ir_loop();
133 exec_list *const f0027_parent_instructions = body.instructions;
134
135 body.instructions = &f0027->body_instructions;
136
137 /* IF CONDITION */
138 ir_expression *const r0029 = less(r000E, body.constant(int(1)));
139 ir_if *f0028 = new(mem_ctx) ir_if(operand(r0029).val);
140 exec_list *const f0028_parent_instructions = body.instructions;
141
142 /* THEN INSTRUCTIONS */
143 body.instructions = &f0028->then_instructions;
144
145 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
146
147
148 body.instructions = f0028_parent_instructions;
149 body.emit(f0028);
150
151 /* END IF */
152
153 /* IF CONDITION */
154 ir_expression *const r002B = sub(body.constant(int(63)), r000E);
155 ir_expression *const r002C = lequal(r0010, r002B);
156 ir_expression *const r002D = lshift(r0026, r000E);
157 ir_expression *const r002E = lequal(r002D, r000F);
158 ir_expression *const r002F = logic_and(r002C, r002E);
159 ir_if *f002A = new(mem_ctx) ir_if(operand(r002F).val);
160 exec_list *const f002A_parent_instructions = body.instructions;
161
162 /* THEN INSTRUCTIONS */
163 body.instructions = &f002A->then_instructions;
164
165 ir_expression *const r0030 = lshift(r0026, r000E);
166 body.emit(assign(r000F, sub(r000F, r0030), 0x01));
167
168 ir_expression *const r0031 = lshift(body.constant(1u), r000E);
169 body.emit(assign(r0011, bit_or(swizzle_x(r0011), r0031), 0x01));
170
171
172 body.instructions = f002A_parent_instructions;
173 body.emit(f002A);
174
175 /* END IF */
176
177 body.emit(assign(r000E, add(r000E, body.constant(int(-1))), 0x01));
178
179 /* LOOP END */
180
181 body.instructions = f0027_parent_instructions;
182 body.emit(f0027);
183
184 /* IF CONDITION */
185 ir_expression *const r0033 = lequal(r0026, r000F);
186 ir_if *f0032 = new(mem_ctx) ir_if(operand(r0033).val);
187 exec_list *const f0032_parent_instructions = body.instructions;
188
189 /* THEN INSTRUCTIONS */
190 body.instructions = &f0032->then_instructions;
191
192 body.emit(assign(r000F, sub(r000F, r0026), 0x01));
193
194 body.emit(assign(r0011, bit_or(swizzle_x(r0011), body.constant(1u)), 0x01));
195
196
197 body.instructions = f0032_parent_instructions;
198 body.emit(f0032);
199
200 /* END IF */
201
202 ir_variable *const r0034 = body.make_temp(glsl_type::uvec4_type, "vec_ctor");
203 body.emit(assign(r0034, r0011, 0x03));
204
205 body.emit(assign(r0034, expr(ir_unop_unpack_uint_2x32, r000F), 0x0c));
206
207 body.emit(ret(r0034));
208
209 sig->replace_parameters(&sig_parameters);
210 return sig;
211 }
212 ir_function_signature *
udiv64(void * mem_ctx,builtin_available_predicate avail)213 udiv64(void *mem_ctx, builtin_available_predicate avail)
214 {
215 ir_function_signature *const sig =
216 new(mem_ctx) ir_function_signature(glsl_type::uvec2_type, avail);
217 ir_factory body(&sig->body, mem_ctx);
218 sig->is_defined = true;
219
220 exec_list sig_parameters;
221
222 ir_variable *const r0035 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "n", ir_var_function_in);
223 sig_parameters.push_tail(r0035);
224 ir_variable *const r0036 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "d", ir_var_function_in);
225 sig_parameters.push_tail(r0036);
226 ir_variable *const r0037 = body.make_temp(glsl_type::uvec2_type, "n");
227 body.emit(assign(r0037, r0035, 0x03));
228
229 ir_variable *const r0038 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
230 body.emit(r0038);
231 ir_variable *const r0039 = new(mem_ctx) ir_variable(glsl_type::uint64_t_type, "n64", ir_var_auto);
232 body.emit(r0039);
233 ir_variable *const r003A = new(mem_ctx) ir_variable(glsl_type::int_type, "log2_denom", ir_var_auto);
234 body.emit(r003A);
235 ir_variable *const r003B = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "quot", ir_var_auto);
236 body.emit(r003B);
237 body.emit(assign(r003B, ir_constant::zero(mem_ctx, glsl_type::uvec2_type), 0x03));
238
239 ir_expression *const r003C = expr(ir_unop_find_msb, swizzle_y(r0036));
240 body.emit(assign(r003A, add(r003C, body.constant(int(32))), 0x01));
241
242 /* IF CONDITION */
243 ir_expression *const r003E = equal(swizzle_y(r0036), body.constant(0u));
244 ir_expression *const r003F = gequal(swizzle_y(r0035), swizzle_x(r0036));
245 ir_expression *const r0040 = logic_and(r003E, r003F);
246 ir_if *f003D = new(mem_ctx) ir_if(operand(r0040).val);
247 exec_list *const f003D_parent_instructions = body.instructions;
248
249 /* THEN INSTRUCTIONS */
250 body.instructions = &f003D->then_instructions;
251
252 ir_variable *const r0041 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
253 body.emit(r0041);
254 ir_variable *const r0042 = body.make_temp(glsl_type::int_type, "findMSB_retval");
255 body.emit(assign(r0042, expr(ir_unop_find_msb, swizzle_x(r0036)), 0x01));
256
257 body.emit(assign(r003A, r0042, 0x01));
258
259 body.emit(assign(r0041, body.constant(int(31)), 0x01));
260
261 /* LOOP BEGIN */
262 ir_loop *f0043 = new(mem_ctx) ir_loop();
263 exec_list *const f0043_parent_instructions = body.instructions;
264
265 body.instructions = &f0043->body_instructions;
266
267 /* IF CONDITION */
268 ir_expression *const r0045 = less(r0041, body.constant(int(1)));
269 ir_if *f0044 = new(mem_ctx) ir_if(operand(r0045).val);
270 exec_list *const f0044_parent_instructions = body.instructions;
271
272 /* THEN INSTRUCTIONS */
273 body.instructions = &f0044->then_instructions;
274
275 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
276
277
278 body.instructions = f0044_parent_instructions;
279 body.emit(f0044);
280
281 /* END IF */
282
283 /* IF CONDITION */
284 ir_expression *const r0047 = sub(body.constant(int(31)), r0041);
285 ir_expression *const r0048 = lequal(r0042, r0047);
286 ir_expression *const r0049 = lshift(swizzle_x(r0036), r0041);
287 ir_expression *const r004A = lequal(r0049, swizzle_y(r0037));
288 ir_expression *const r004B = logic_and(r0048, r004A);
289 ir_if *f0046 = new(mem_ctx) ir_if(operand(r004B).val);
290 exec_list *const f0046_parent_instructions = body.instructions;
291
292 /* THEN INSTRUCTIONS */
293 body.instructions = &f0046->then_instructions;
294
295 ir_expression *const r004C = lshift(swizzle_x(r0036), r0041);
296 body.emit(assign(r0037, sub(swizzle_y(r0037), r004C), 0x02));
297
298 ir_expression *const r004D = lshift(body.constant(1u), r0041);
299 body.emit(assign(r003B, bit_or(swizzle_y(r003B), r004D), 0x02));
300
301
302 body.instructions = f0046_parent_instructions;
303 body.emit(f0046);
304
305 /* END IF */
306
307 body.emit(assign(r0041, add(r0041, body.constant(int(-1))), 0x01));
308
309 /* LOOP END */
310
311 body.instructions = f0043_parent_instructions;
312 body.emit(f0043);
313
314 /* IF CONDITION */
315 ir_expression *const r004F = lequal(swizzle_x(r0036), swizzle_y(r0037));
316 ir_if *f004E = new(mem_ctx) ir_if(operand(r004F).val);
317 exec_list *const f004E_parent_instructions = body.instructions;
318
319 /* THEN INSTRUCTIONS */
320 body.instructions = &f004E->then_instructions;
321
322 body.emit(assign(r0037, sub(swizzle_y(r0037), swizzle_x(r0036)), 0x02));
323
324 body.emit(assign(r003B, bit_or(swizzle_y(r003B), body.constant(1u)), 0x02));
325
326
327 body.instructions = f004E_parent_instructions;
328 body.emit(f004E);
329
330 /* END IF */
331
332
333 body.instructions = f003D_parent_instructions;
334 body.emit(f003D);
335
336 /* END IF */
337
338 ir_variable *const r0050 = body.make_temp(glsl_type::uint64_t_type, "packUint2x32_retval");
339 body.emit(assign(r0050, expr(ir_unop_pack_uint_2x32, r0036), 0x01));
340
341 body.emit(assign(r0039, expr(ir_unop_pack_uint_2x32, r0037), 0x01));
342
343 body.emit(assign(r0038, body.constant(int(31)), 0x01));
344
345 /* LOOP BEGIN */
346 ir_loop *f0051 = new(mem_ctx) ir_loop();
347 exec_list *const f0051_parent_instructions = body.instructions;
348
349 body.instructions = &f0051->body_instructions;
350
351 /* IF CONDITION */
352 ir_expression *const r0053 = less(r0038, body.constant(int(1)));
353 ir_if *f0052 = new(mem_ctx) ir_if(operand(r0053).val);
354 exec_list *const f0052_parent_instructions = body.instructions;
355
356 /* THEN INSTRUCTIONS */
357 body.instructions = &f0052->then_instructions;
358
359 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
360
361
362 body.instructions = f0052_parent_instructions;
363 body.emit(f0052);
364
365 /* END IF */
366
367 /* IF CONDITION */
368 ir_expression *const r0055 = sub(body.constant(int(63)), r0038);
369 ir_expression *const r0056 = lequal(r003A, r0055);
370 ir_expression *const r0057 = lshift(r0050, r0038);
371 ir_expression *const r0058 = lequal(r0057, r0039);
372 ir_expression *const r0059 = logic_and(r0056, r0058);
373 ir_if *f0054 = new(mem_ctx) ir_if(operand(r0059).val);
374 exec_list *const f0054_parent_instructions = body.instructions;
375
376 /* THEN INSTRUCTIONS */
377 body.instructions = &f0054->then_instructions;
378
379 ir_expression *const r005A = lshift(r0050, r0038);
380 body.emit(assign(r0039, sub(r0039, r005A), 0x01));
381
382 ir_expression *const r005B = lshift(body.constant(1u), r0038);
383 body.emit(assign(r003B, bit_or(swizzle_x(r003B), r005B), 0x01));
384
385
386 body.instructions = f0054_parent_instructions;
387 body.emit(f0054);
388
389 /* END IF */
390
391 body.emit(assign(r0038, add(r0038, body.constant(int(-1))), 0x01));
392
393 /* LOOP END */
394
395 body.instructions = f0051_parent_instructions;
396 body.emit(f0051);
397
398 /* IF CONDITION */
399 ir_expression *const r005D = lequal(r0050, r0039);
400 ir_if *f005C = new(mem_ctx) ir_if(operand(r005D).val);
401 exec_list *const f005C_parent_instructions = body.instructions;
402
403 /* THEN INSTRUCTIONS */
404 body.instructions = &f005C->then_instructions;
405
406 body.emit(assign(r0039, sub(r0039, r0050), 0x01));
407
408 body.emit(assign(r003B, bit_or(swizzle_x(r003B), body.constant(1u)), 0x01));
409
410
411 body.instructions = f005C_parent_instructions;
412 body.emit(f005C);
413
414 /* END IF */
415
416 body.emit(ret(r003B));
417
418 sig->replace_parameters(&sig_parameters);
419 return sig;
420 }
421 ir_function_signature *
idiv64(void * mem_ctx,builtin_available_predicate avail)422 idiv64(void *mem_ctx, builtin_available_predicate avail)
423 {
424 ir_function_signature *const sig =
425 new(mem_ctx) ir_function_signature(glsl_type::ivec2_type, avail);
426 ir_factory body(&sig->body, mem_ctx);
427 sig->is_defined = true;
428
429 exec_list sig_parameters;
430
431 ir_variable *const r005E = new(mem_ctx) ir_variable(glsl_type::ivec2_type, "_n", ir_var_function_in);
432 sig_parameters.push_tail(r005E);
433 ir_variable *const r005F = new(mem_ctx) ir_variable(glsl_type::ivec2_type, "_d", ir_var_function_in);
434 sig_parameters.push_tail(r005F);
435 ir_variable *const r0060 = new(mem_ctx) ir_variable(glsl_type::bool_type, "negate", ir_var_auto);
436 body.emit(r0060);
437 ir_expression *const r0061 = less(swizzle_y(r005E), body.constant(int(0)));
438 ir_expression *const r0062 = less(swizzle_y(r005F), body.constant(int(0)));
439 body.emit(assign(r0060, nequal(r0061, r0062), 0x01));
440
441 ir_variable *const r0063 = body.make_temp(glsl_type::uvec2_type, "n");
442 ir_expression *const r0064 = expr(ir_unop_pack_int_2x32, r005E);
443 ir_expression *const r0065 = expr(ir_unop_abs, r0064);
444 ir_expression *const r0066 = expr(ir_unop_i642u64, r0065);
445 body.emit(assign(r0063, expr(ir_unop_unpack_uint_2x32, r0066), 0x03));
446
447 ir_variable *const r0067 = body.make_temp(glsl_type::uvec2_type, "d");
448 ir_expression *const r0068 = expr(ir_unop_pack_int_2x32, r005F);
449 ir_expression *const r0069 = expr(ir_unop_abs, r0068);
450 ir_expression *const r006A = expr(ir_unop_i642u64, r0069);
451 body.emit(assign(r0067, expr(ir_unop_unpack_uint_2x32, r006A), 0x03));
452
453 ir_variable *const r006B = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
454 body.emit(r006B);
455 ir_variable *const r006C = new(mem_ctx) ir_variable(glsl_type::uint64_t_type, "n64", ir_var_auto);
456 body.emit(r006C);
457 ir_variable *const r006D = new(mem_ctx) ir_variable(glsl_type::int_type, "log2_denom", ir_var_auto);
458 body.emit(r006D);
459 ir_variable *const r006E = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "quot", ir_var_auto);
460 body.emit(r006E);
461 body.emit(assign(r006E, ir_constant::zero(mem_ctx, glsl_type::uvec2_type), 0x03));
462
463 ir_expression *const r006F = expr(ir_unop_find_msb, swizzle_y(r0067));
464 body.emit(assign(r006D, add(r006F, body.constant(int(32))), 0x01));
465
466 /* IF CONDITION */
467 ir_expression *const r0071 = equal(swizzle_y(r0067), body.constant(0u));
468 ir_expression *const r0072 = gequal(swizzle_y(r0063), swizzle_x(r0067));
469 ir_expression *const r0073 = logic_and(r0071, r0072);
470 ir_if *f0070 = new(mem_ctx) ir_if(operand(r0073).val);
471 exec_list *const f0070_parent_instructions = body.instructions;
472
473 /* THEN INSTRUCTIONS */
474 body.instructions = &f0070->then_instructions;
475
476 ir_variable *const r0074 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
477 body.emit(r0074);
478 ir_variable *const r0075 = body.make_temp(glsl_type::int_type, "findMSB_retval");
479 body.emit(assign(r0075, expr(ir_unop_find_msb, swizzle_x(r0067)), 0x01));
480
481 body.emit(assign(r006D, r0075, 0x01));
482
483 body.emit(assign(r0074, body.constant(int(31)), 0x01));
484
485 /* LOOP BEGIN */
486 ir_loop *f0076 = new(mem_ctx) ir_loop();
487 exec_list *const f0076_parent_instructions = body.instructions;
488
489 body.instructions = &f0076->body_instructions;
490
491 /* IF CONDITION */
492 ir_expression *const r0078 = less(r0074, body.constant(int(1)));
493 ir_if *f0077 = new(mem_ctx) ir_if(operand(r0078).val);
494 exec_list *const f0077_parent_instructions = body.instructions;
495
496 /* THEN INSTRUCTIONS */
497 body.instructions = &f0077->then_instructions;
498
499 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
500
501
502 body.instructions = f0077_parent_instructions;
503 body.emit(f0077);
504
505 /* END IF */
506
507 /* IF CONDITION */
508 ir_expression *const r007A = sub(body.constant(int(31)), r0074);
509 ir_expression *const r007B = lequal(r0075, r007A);
510 ir_expression *const r007C = lshift(swizzle_x(r0067), r0074);
511 ir_expression *const r007D = lequal(r007C, swizzle_y(r0063));
512 ir_expression *const r007E = logic_and(r007B, r007D);
513 ir_if *f0079 = new(mem_ctx) ir_if(operand(r007E).val);
514 exec_list *const f0079_parent_instructions = body.instructions;
515
516 /* THEN INSTRUCTIONS */
517 body.instructions = &f0079->then_instructions;
518
519 ir_expression *const r007F = lshift(swizzle_x(r0067), r0074);
520 body.emit(assign(r0063, sub(swizzle_y(r0063), r007F), 0x02));
521
522 ir_expression *const r0080 = lshift(body.constant(1u), r0074);
523 body.emit(assign(r006E, bit_or(swizzle_y(r006E), r0080), 0x02));
524
525
526 body.instructions = f0079_parent_instructions;
527 body.emit(f0079);
528
529 /* END IF */
530
531 body.emit(assign(r0074, add(r0074, body.constant(int(-1))), 0x01));
532
533 /* LOOP END */
534
535 body.instructions = f0076_parent_instructions;
536 body.emit(f0076);
537
538 /* IF CONDITION */
539 ir_expression *const r0082 = lequal(swizzle_x(r0067), swizzle_y(r0063));
540 ir_if *f0081 = new(mem_ctx) ir_if(operand(r0082).val);
541 exec_list *const f0081_parent_instructions = body.instructions;
542
543 /* THEN INSTRUCTIONS */
544 body.instructions = &f0081->then_instructions;
545
546 body.emit(assign(r0063, sub(swizzle_y(r0063), swizzle_x(r0067)), 0x02));
547
548 body.emit(assign(r006E, bit_or(swizzle_y(r006E), body.constant(1u)), 0x02));
549
550
551 body.instructions = f0081_parent_instructions;
552 body.emit(f0081);
553
554 /* END IF */
555
556
557 body.instructions = f0070_parent_instructions;
558 body.emit(f0070);
559
560 /* END IF */
561
562 ir_variable *const r0083 = body.make_temp(glsl_type::uint64_t_type, "packUint2x32_retval");
563 body.emit(assign(r0083, expr(ir_unop_pack_uint_2x32, r0067), 0x01));
564
565 body.emit(assign(r006C, expr(ir_unop_pack_uint_2x32, r0063), 0x01));
566
567 body.emit(assign(r006B, body.constant(int(31)), 0x01));
568
569 /* LOOP BEGIN */
570 ir_loop *f0084 = new(mem_ctx) ir_loop();
571 exec_list *const f0084_parent_instructions = body.instructions;
572
573 body.instructions = &f0084->body_instructions;
574
575 /* IF CONDITION */
576 ir_expression *const r0086 = less(r006B, body.constant(int(1)));
577 ir_if *f0085 = new(mem_ctx) ir_if(operand(r0086).val);
578 exec_list *const f0085_parent_instructions = body.instructions;
579
580 /* THEN INSTRUCTIONS */
581 body.instructions = &f0085->then_instructions;
582
583 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
584
585
586 body.instructions = f0085_parent_instructions;
587 body.emit(f0085);
588
589 /* END IF */
590
591 /* IF CONDITION */
592 ir_expression *const r0088 = sub(body.constant(int(63)), r006B);
593 ir_expression *const r0089 = lequal(r006D, r0088);
594 ir_expression *const r008A = lshift(r0083, r006B);
595 ir_expression *const r008B = lequal(r008A, r006C);
596 ir_expression *const r008C = logic_and(r0089, r008B);
597 ir_if *f0087 = new(mem_ctx) ir_if(operand(r008C).val);
598 exec_list *const f0087_parent_instructions = body.instructions;
599
600 /* THEN INSTRUCTIONS */
601 body.instructions = &f0087->then_instructions;
602
603 ir_expression *const r008D = lshift(r0083, r006B);
604 body.emit(assign(r006C, sub(r006C, r008D), 0x01));
605
606 ir_expression *const r008E = lshift(body.constant(1u), r006B);
607 body.emit(assign(r006E, bit_or(swizzle_x(r006E), r008E), 0x01));
608
609
610 body.instructions = f0087_parent_instructions;
611 body.emit(f0087);
612
613 /* END IF */
614
615 body.emit(assign(r006B, add(r006B, body.constant(int(-1))), 0x01));
616
617 /* LOOP END */
618
619 body.instructions = f0084_parent_instructions;
620 body.emit(f0084);
621
622 /* IF CONDITION */
623 ir_expression *const r0090 = lequal(r0083, r006C);
624 ir_if *f008F = new(mem_ctx) ir_if(operand(r0090).val);
625 exec_list *const f008F_parent_instructions = body.instructions;
626
627 /* THEN INSTRUCTIONS */
628 body.instructions = &f008F->then_instructions;
629
630 body.emit(assign(r006C, sub(r006C, r0083), 0x01));
631
632 body.emit(assign(r006E, bit_or(swizzle_x(r006E), body.constant(1u)), 0x01));
633
634
635 body.instructions = f008F_parent_instructions;
636 body.emit(f008F);
637
638 /* END IF */
639
640 ir_variable *const r0091 = body.make_temp(glsl_type::ivec2_type, "conditional_tmp");
641 /* IF CONDITION */
642 ir_if *f0092 = new(mem_ctx) ir_if(operand(r0060).val);
643 exec_list *const f0092_parent_instructions = body.instructions;
644
645 /* THEN INSTRUCTIONS */
646 body.instructions = &f0092->then_instructions;
647
648 ir_expression *const r0093 = expr(ir_unop_pack_uint_2x32, r006E);
649 ir_expression *const r0094 = expr(ir_unop_u642i64, r0093);
650 ir_expression *const r0095 = neg(r0094);
651 body.emit(assign(r0091, expr(ir_unop_unpack_int_2x32, r0095), 0x03));
652
653
654 /* ELSE INSTRUCTIONS */
655 body.instructions = &f0092->else_instructions;
656
657 body.emit(assign(r0091, expr(ir_unop_u2i, r006E), 0x03));
658
659
660 body.instructions = f0092_parent_instructions;
661 body.emit(f0092);
662
663 /* END IF */
664
665 body.emit(ret(r0091));
666
667 sig->replace_parameters(&sig_parameters);
668 return sig;
669 }
670 ir_function_signature *
umod64(void * mem_ctx,builtin_available_predicate avail)671 umod64(void *mem_ctx, builtin_available_predicate avail)
672 {
673 ir_function_signature *const sig =
674 new(mem_ctx) ir_function_signature(glsl_type::uvec2_type, avail);
675 ir_factory body(&sig->body, mem_ctx);
676 sig->is_defined = true;
677
678 exec_list sig_parameters;
679
680 ir_variable *const r0096 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "n", ir_var_function_in);
681 sig_parameters.push_tail(r0096);
682 ir_variable *const r0097 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "d", ir_var_function_in);
683 sig_parameters.push_tail(r0097);
684 ir_variable *const r0098 = body.make_temp(glsl_type::uvec2_type, "n");
685 body.emit(assign(r0098, r0096, 0x03));
686
687 ir_variable *const r0099 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
688 body.emit(r0099);
689 ir_variable *const r009A = new(mem_ctx) ir_variable(glsl_type::uint64_t_type, "n64", ir_var_auto);
690 body.emit(r009A);
691 ir_variable *const r009B = new(mem_ctx) ir_variable(glsl_type::int_type, "log2_denom", ir_var_auto);
692 body.emit(r009B);
693 ir_variable *const r009C = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "quot", ir_var_auto);
694 body.emit(r009C);
695 body.emit(assign(r009C, ir_constant::zero(mem_ctx, glsl_type::uvec2_type), 0x03));
696
697 ir_expression *const r009D = expr(ir_unop_find_msb, swizzle_y(r0097));
698 body.emit(assign(r009B, add(r009D, body.constant(int(32))), 0x01));
699
700 /* IF CONDITION */
701 ir_expression *const r009F = equal(swizzle_y(r0097), body.constant(0u));
702 ir_expression *const r00A0 = gequal(swizzle_y(r0096), swizzle_x(r0097));
703 ir_expression *const r00A1 = logic_and(r009F, r00A0);
704 ir_if *f009E = new(mem_ctx) ir_if(operand(r00A1).val);
705 exec_list *const f009E_parent_instructions = body.instructions;
706
707 /* THEN INSTRUCTIONS */
708 body.instructions = &f009E->then_instructions;
709
710 ir_variable *const r00A2 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
711 body.emit(r00A2);
712 ir_variable *const r00A3 = body.make_temp(glsl_type::int_type, "findMSB_retval");
713 body.emit(assign(r00A3, expr(ir_unop_find_msb, swizzle_x(r0097)), 0x01));
714
715 body.emit(assign(r009B, r00A3, 0x01));
716
717 body.emit(assign(r00A2, body.constant(int(31)), 0x01));
718
719 /* LOOP BEGIN */
720 ir_loop *f00A4 = new(mem_ctx) ir_loop();
721 exec_list *const f00A4_parent_instructions = body.instructions;
722
723 body.instructions = &f00A4->body_instructions;
724
725 /* IF CONDITION */
726 ir_expression *const r00A6 = less(r00A2, body.constant(int(1)));
727 ir_if *f00A5 = new(mem_ctx) ir_if(operand(r00A6).val);
728 exec_list *const f00A5_parent_instructions = body.instructions;
729
730 /* THEN INSTRUCTIONS */
731 body.instructions = &f00A5->then_instructions;
732
733 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
734
735
736 body.instructions = f00A5_parent_instructions;
737 body.emit(f00A5);
738
739 /* END IF */
740
741 /* IF CONDITION */
742 ir_expression *const r00A8 = sub(body.constant(int(31)), r00A2);
743 ir_expression *const r00A9 = lequal(r00A3, r00A8);
744 ir_expression *const r00AA = lshift(swizzle_x(r0097), r00A2);
745 ir_expression *const r00AB = lequal(r00AA, swizzle_y(r0098));
746 ir_expression *const r00AC = logic_and(r00A9, r00AB);
747 ir_if *f00A7 = new(mem_ctx) ir_if(operand(r00AC).val);
748 exec_list *const f00A7_parent_instructions = body.instructions;
749
750 /* THEN INSTRUCTIONS */
751 body.instructions = &f00A7->then_instructions;
752
753 ir_expression *const r00AD = lshift(swizzle_x(r0097), r00A2);
754 body.emit(assign(r0098, sub(swizzle_y(r0098), r00AD), 0x02));
755
756 ir_expression *const r00AE = lshift(body.constant(1u), r00A2);
757 body.emit(assign(r009C, bit_or(swizzle_y(r009C), r00AE), 0x02));
758
759
760 body.instructions = f00A7_parent_instructions;
761 body.emit(f00A7);
762
763 /* END IF */
764
765 body.emit(assign(r00A2, add(r00A2, body.constant(int(-1))), 0x01));
766
767 /* LOOP END */
768
769 body.instructions = f00A4_parent_instructions;
770 body.emit(f00A4);
771
772 /* IF CONDITION */
773 ir_expression *const r00B0 = lequal(swizzle_x(r0097), swizzle_y(r0098));
774 ir_if *f00AF = new(mem_ctx) ir_if(operand(r00B0).val);
775 exec_list *const f00AF_parent_instructions = body.instructions;
776
777 /* THEN INSTRUCTIONS */
778 body.instructions = &f00AF->then_instructions;
779
780 body.emit(assign(r0098, sub(swizzle_y(r0098), swizzle_x(r0097)), 0x02));
781
782 body.emit(assign(r009C, bit_or(swizzle_y(r009C), body.constant(1u)), 0x02));
783
784
785 body.instructions = f00AF_parent_instructions;
786 body.emit(f00AF);
787
788 /* END IF */
789
790
791 body.instructions = f009E_parent_instructions;
792 body.emit(f009E);
793
794 /* END IF */
795
796 ir_variable *const r00B1 = body.make_temp(glsl_type::uint64_t_type, "packUint2x32_retval");
797 body.emit(assign(r00B1, expr(ir_unop_pack_uint_2x32, r0097), 0x01));
798
799 body.emit(assign(r009A, expr(ir_unop_pack_uint_2x32, r0098), 0x01));
800
801 body.emit(assign(r0099, body.constant(int(31)), 0x01));
802
803 /* LOOP BEGIN */
804 ir_loop *f00B2 = new(mem_ctx) ir_loop();
805 exec_list *const f00B2_parent_instructions = body.instructions;
806
807 body.instructions = &f00B2->body_instructions;
808
809 /* IF CONDITION */
810 ir_expression *const r00B4 = less(r0099, body.constant(int(1)));
811 ir_if *f00B3 = new(mem_ctx) ir_if(operand(r00B4).val);
812 exec_list *const f00B3_parent_instructions = body.instructions;
813
814 /* THEN INSTRUCTIONS */
815 body.instructions = &f00B3->then_instructions;
816
817 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
818
819
820 body.instructions = f00B3_parent_instructions;
821 body.emit(f00B3);
822
823 /* END IF */
824
825 /* IF CONDITION */
826 ir_expression *const r00B6 = sub(body.constant(int(63)), r0099);
827 ir_expression *const r00B7 = lequal(r009B, r00B6);
828 ir_expression *const r00B8 = lshift(r00B1, r0099);
829 ir_expression *const r00B9 = lequal(r00B8, r009A);
830 ir_expression *const r00BA = logic_and(r00B7, r00B9);
831 ir_if *f00B5 = new(mem_ctx) ir_if(operand(r00BA).val);
832 exec_list *const f00B5_parent_instructions = body.instructions;
833
834 /* THEN INSTRUCTIONS */
835 body.instructions = &f00B5->then_instructions;
836
837 ir_expression *const r00BB = lshift(r00B1, r0099);
838 body.emit(assign(r009A, sub(r009A, r00BB), 0x01));
839
840 ir_expression *const r00BC = lshift(body.constant(1u), r0099);
841 body.emit(assign(r009C, bit_or(swizzle_x(r009C), r00BC), 0x01));
842
843
844 body.instructions = f00B5_parent_instructions;
845 body.emit(f00B5);
846
847 /* END IF */
848
849 body.emit(assign(r0099, add(r0099, body.constant(int(-1))), 0x01));
850
851 /* LOOP END */
852
853 body.instructions = f00B2_parent_instructions;
854 body.emit(f00B2);
855
856 /* IF CONDITION */
857 ir_expression *const r00BE = lequal(r00B1, r009A);
858 ir_if *f00BD = new(mem_ctx) ir_if(operand(r00BE).val);
859 exec_list *const f00BD_parent_instructions = body.instructions;
860
861 /* THEN INSTRUCTIONS */
862 body.instructions = &f00BD->then_instructions;
863
864 body.emit(assign(r009A, sub(r009A, r00B1), 0x01));
865
866 body.emit(assign(r009C, bit_or(swizzle_x(r009C), body.constant(1u)), 0x01));
867
868
869 body.instructions = f00BD_parent_instructions;
870 body.emit(f00BD);
871
872 /* END IF */
873
874 ir_variable *const r00BF = body.make_temp(glsl_type::uvec4_type, "vec_ctor");
875 body.emit(assign(r00BF, r009C, 0x03));
876
877 body.emit(assign(r00BF, expr(ir_unop_unpack_uint_2x32, r009A), 0x0c));
878
879 ir_swizzle *const r00C0 = swizzle(r00BF, MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_X), 2);
880 body.emit(ret(r00C0));
881
882 sig->replace_parameters(&sig_parameters);
883 return sig;
884 }
885 ir_function_signature *
imod64(void * mem_ctx,builtin_available_predicate avail)886 imod64(void *mem_ctx, builtin_available_predicate avail)
887 {
888 ir_function_signature *const sig =
889 new(mem_ctx) ir_function_signature(glsl_type::ivec2_type, avail);
890 ir_factory body(&sig->body, mem_ctx);
891 sig->is_defined = true;
892
893 exec_list sig_parameters;
894
895 ir_variable *const r00C1 = new(mem_ctx) ir_variable(glsl_type::ivec2_type, "_n", ir_var_function_in);
896 sig_parameters.push_tail(r00C1);
897 ir_variable *const r00C2 = new(mem_ctx) ir_variable(glsl_type::ivec2_type, "_d", ir_var_function_in);
898 sig_parameters.push_tail(r00C2);
899 ir_variable *const r00C3 = new(mem_ctx) ir_variable(glsl_type::bool_type, "negate", ir_var_auto);
900 body.emit(r00C3);
901 ir_expression *const r00C4 = less(swizzle_y(r00C1), body.constant(int(0)));
902 ir_expression *const r00C5 = less(swizzle_y(r00C2), body.constant(int(0)));
903 body.emit(assign(r00C3, nequal(r00C4, r00C5), 0x01));
904
905 ir_variable *const r00C6 = body.make_temp(glsl_type::uvec2_type, "n");
906 ir_expression *const r00C7 = expr(ir_unop_pack_int_2x32, r00C1);
907 ir_expression *const r00C8 = expr(ir_unop_abs, r00C7);
908 ir_expression *const r00C9 = expr(ir_unop_i642u64, r00C8);
909 body.emit(assign(r00C6, expr(ir_unop_unpack_uint_2x32, r00C9), 0x03));
910
911 ir_variable *const r00CA = body.make_temp(glsl_type::uvec2_type, "d");
912 ir_expression *const r00CB = expr(ir_unop_pack_int_2x32, r00C2);
913 ir_expression *const r00CC = expr(ir_unop_abs, r00CB);
914 ir_expression *const r00CD = expr(ir_unop_i642u64, r00CC);
915 body.emit(assign(r00CA, expr(ir_unop_unpack_uint_2x32, r00CD), 0x03));
916
917 ir_variable *const r00CE = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
918 body.emit(r00CE);
919 ir_variable *const r00CF = new(mem_ctx) ir_variable(glsl_type::uint64_t_type, "n64", ir_var_auto);
920 body.emit(r00CF);
921 ir_variable *const r00D0 = new(mem_ctx) ir_variable(glsl_type::int_type, "log2_denom", ir_var_auto);
922 body.emit(r00D0);
923 ir_variable *const r00D1 = new(mem_ctx) ir_variable(glsl_type::uvec2_type, "quot", ir_var_auto);
924 body.emit(r00D1);
925 body.emit(assign(r00D1, ir_constant::zero(mem_ctx, glsl_type::uvec2_type), 0x03));
926
927 ir_expression *const r00D2 = expr(ir_unop_find_msb, swizzle_y(r00CA));
928 body.emit(assign(r00D0, add(r00D2, body.constant(int(32))), 0x01));
929
930 /* IF CONDITION */
931 ir_expression *const r00D4 = equal(swizzle_y(r00CA), body.constant(0u));
932 ir_expression *const r00D5 = gequal(swizzle_y(r00C6), swizzle_x(r00CA));
933 ir_expression *const r00D6 = logic_and(r00D4, r00D5);
934 ir_if *f00D3 = new(mem_ctx) ir_if(operand(r00D6).val);
935 exec_list *const f00D3_parent_instructions = body.instructions;
936
937 /* THEN INSTRUCTIONS */
938 body.instructions = &f00D3->then_instructions;
939
940 ir_variable *const r00D7 = new(mem_ctx) ir_variable(glsl_type::int_type, "i", ir_var_auto);
941 body.emit(r00D7);
942 ir_variable *const r00D8 = body.make_temp(glsl_type::int_type, "findMSB_retval");
943 body.emit(assign(r00D8, expr(ir_unop_find_msb, swizzle_x(r00CA)), 0x01));
944
945 body.emit(assign(r00D0, r00D8, 0x01));
946
947 body.emit(assign(r00D7, body.constant(int(31)), 0x01));
948
949 /* LOOP BEGIN */
950 ir_loop *f00D9 = new(mem_ctx) ir_loop();
951 exec_list *const f00D9_parent_instructions = body.instructions;
952
953 body.instructions = &f00D9->body_instructions;
954
955 /* IF CONDITION */
956 ir_expression *const r00DB = less(r00D7, body.constant(int(1)));
957 ir_if *f00DA = new(mem_ctx) ir_if(operand(r00DB).val);
958 exec_list *const f00DA_parent_instructions = body.instructions;
959
960 /* THEN INSTRUCTIONS */
961 body.instructions = &f00DA->then_instructions;
962
963 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
964
965
966 body.instructions = f00DA_parent_instructions;
967 body.emit(f00DA);
968
969 /* END IF */
970
971 /* IF CONDITION */
972 ir_expression *const r00DD = sub(body.constant(int(31)), r00D7);
973 ir_expression *const r00DE = lequal(r00D8, r00DD);
974 ir_expression *const r00DF = lshift(swizzle_x(r00CA), r00D7);
975 ir_expression *const r00E0 = lequal(r00DF, swizzle_y(r00C6));
976 ir_expression *const r00E1 = logic_and(r00DE, r00E0);
977 ir_if *f00DC = new(mem_ctx) ir_if(operand(r00E1).val);
978 exec_list *const f00DC_parent_instructions = body.instructions;
979
980 /* THEN INSTRUCTIONS */
981 body.instructions = &f00DC->then_instructions;
982
983 ir_expression *const r00E2 = lshift(swizzle_x(r00CA), r00D7);
984 body.emit(assign(r00C6, sub(swizzle_y(r00C6), r00E2), 0x02));
985
986 ir_expression *const r00E3 = lshift(body.constant(1u), r00D7);
987 body.emit(assign(r00D1, bit_or(swizzle_y(r00D1), r00E3), 0x02));
988
989
990 body.instructions = f00DC_parent_instructions;
991 body.emit(f00DC);
992
993 /* END IF */
994
995 body.emit(assign(r00D7, add(r00D7, body.constant(int(-1))), 0x01));
996
997 /* LOOP END */
998
999 body.instructions = f00D9_parent_instructions;
1000 body.emit(f00D9);
1001
1002 /* IF CONDITION */
1003 ir_expression *const r00E5 = lequal(swizzle_x(r00CA), swizzle_y(r00C6));
1004 ir_if *f00E4 = new(mem_ctx) ir_if(operand(r00E5).val);
1005 exec_list *const f00E4_parent_instructions = body.instructions;
1006
1007 /* THEN INSTRUCTIONS */
1008 body.instructions = &f00E4->then_instructions;
1009
1010 body.emit(assign(r00C6, sub(swizzle_y(r00C6), swizzle_x(r00CA)), 0x02));
1011
1012 body.emit(assign(r00D1, bit_or(swizzle_y(r00D1), body.constant(1u)), 0x02));
1013
1014
1015 body.instructions = f00E4_parent_instructions;
1016 body.emit(f00E4);
1017
1018 /* END IF */
1019
1020
1021 body.instructions = f00D3_parent_instructions;
1022 body.emit(f00D3);
1023
1024 /* END IF */
1025
1026 ir_variable *const r00E6 = body.make_temp(glsl_type::uint64_t_type, "packUint2x32_retval");
1027 body.emit(assign(r00E6, expr(ir_unop_pack_uint_2x32, r00CA), 0x01));
1028
1029 body.emit(assign(r00CF, expr(ir_unop_pack_uint_2x32, r00C6), 0x01));
1030
1031 body.emit(assign(r00CE, body.constant(int(31)), 0x01));
1032
1033 /* LOOP BEGIN */
1034 ir_loop *f00E7 = new(mem_ctx) ir_loop();
1035 exec_list *const f00E7_parent_instructions = body.instructions;
1036
1037 body.instructions = &f00E7->body_instructions;
1038
1039 /* IF CONDITION */
1040 ir_expression *const r00E9 = less(r00CE, body.constant(int(1)));
1041 ir_if *f00E8 = new(mem_ctx) ir_if(operand(r00E9).val);
1042 exec_list *const f00E8_parent_instructions = body.instructions;
1043
1044 /* THEN INSTRUCTIONS */
1045 body.instructions = &f00E8->then_instructions;
1046
1047 body.emit(new(mem_ctx) ir_loop_jump(ir_loop_jump::jump_break));
1048
1049
1050 body.instructions = f00E8_parent_instructions;
1051 body.emit(f00E8);
1052
1053 /* END IF */
1054
1055 /* IF CONDITION */
1056 ir_expression *const r00EB = sub(body.constant(int(63)), r00CE);
1057 ir_expression *const r00EC = lequal(r00D0, r00EB);
1058 ir_expression *const r00ED = lshift(r00E6, r00CE);
1059 ir_expression *const r00EE = lequal(r00ED, r00CF);
1060 ir_expression *const r00EF = logic_and(r00EC, r00EE);
1061 ir_if *f00EA = new(mem_ctx) ir_if(operand(r00EF).val);
1062 exec_list *const f00EA_parent_instructions = body.instructions;
1063
1064 /* THEN INSTRUCTIONS */
1065 body.instructions = &f00EA->then_instructions;
1066
1067 ir_expression *const r00F0 = lshift(r00E6, r00CE);
1068 body.emit(assign(r00CF, sub(r00CF, r00F0), 0x01));
1069
1070 ir_expression *const r00F1 = lshift(body.constant(1u), r00CE);
1071 body.emit(assign(r00D1, bit_or(swizzle_x(r00D1), r00F1), 0x01));
1072
1073
1074 body.instructions = f00EA_parent_instructions;
1075 body.emit(f00EA);
1076
1077 /* END IF */
1078
1079 body.emit(assign(r00CE, add(r00CE, body.constant(int(-1))), 0x01));
1080
1081 /* LOOP END */
1082
1083 body.instructions = f00E7_parent_instructions;
1084 body.emit(f00E7);
1085
1086 /* IF CONDITION */
1087 ir_expression *const r00F3 = lequal(r00E6, r00CF);
1088 ir_if *f00F2 = new(mem_ctx) ir_if(operand(r00F3).val);
1089 exec_list *const f00F2_parent_instructions = body.instructions;
1090
1091 /* THEN INSTRUCTIONS */
1092 body.instructions = &f00F2->then_instructions;
1093
1094 body.emit(assign(r00CF, sub(r00CF, r00E6), 0x01));
1095
1096 body.emit(assign(r00D1, bit_or(swizzle_x(r00D1), body.constant(1u)), 0x01));
1097
1098
1099 body.instructions = f00F2_parent_instructions;
1100 body.emit(f00F2);
1101
1102 /* END IF */
1103
1104 ir_variable *const r00F4 = body.make_temp(glsl_type::uvec4_type, "vec_ctor");
1105 body.emit(assign(r00F4, r00D1, 0x03));
1106
1107 body.emit(assign(r00F4, expr(ir_unop_unpack_uint_2x32, r00CF), 0x0c));
1108
1109 ir_variable *const r00F5 = body.make_temp(glsl_type::ivec2_type, "conditional_tmp");
1110 /* IF CONDITION */
1111 ir_if *f00F6 = new(mem_ctx) ir_if(operand(r00C3).val);
1112 exec_list *const f00F6_parent_instructions = body.instructions;
1113
1114 /* THEN INSTRUCTIONS */
1115 body.instructions = &f00F6->then_instructions;
1116
1117 ir_swizzle *const r00F7 = swizzle(r00F4, MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_X), 2);
1118 ir_expression *const r00F8 = expr(ir_unop_pack_uint_2x32, r00F7);
1119 ir_expression *const r00F9 = expr(ir_unop_u642i64, r00F8);
1120 ir_expression *const r00FA = neg(r00F9);
1121 body.emit(assign(r00F5, expr(ir_unop_unpack_int_2x32, r00FA), 0x03));
1122
1123
1124 /* ELSE INSTRUCTIONS */
1125 body.instructions = &f00F6->else_instructions;
1126
1127 ir_swizzle *const r00FB = swizzle(r00F4, MAKE_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_X), 2);
1128 body.emit(assign(r00F5, expr(ir_unop_u2i, r00FB), 0x03));
1129
1130
1131 body.instructions = f00F6_parent_instructions;
1132 body.emit(f00F6);
1133
1134 /* END IF */
1135
1136 body.emit(ret(r00F5));
1137
1138 sig->replace_parameters(&sig_parameters);
1139 return sig;
1140 }
1141