1 /* 2 * Copyright © 2022 Imagination Technologies Ltd. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef PVR_ROGUE_FWIF_SHARED_H 25 #define PVR_ROGUE_FWIF_SHARED_H 26 27 #include <stdbool.h> 28 #include <stdint.h> 29 30 #define ALIGN_ATTR(x) __attribute__((aligned(x))) 31 32 /** Indicates the number of RTDATAs per RTDATASET. */ 33 #define ROGUE_FWIF_NUM_RTDATAS 2U 34 #define ROGUE_FWIF_NUM_GEOMDATAS 1U 35 #define ROGUE_FWIF_NUM_RTDATA_FREELISTS 2U 36 #define ROGUE_NUM_GEOM_CORES 1U 37 38 #define ROGUE_NUM_GEOM_CORES_SIZE 2U 39 40 /** 41 * Maximum number of UFOs in a CCB command. 42 * The number is based on having 32 sync prims (as originally), plus 32 sync 43 * checkpoints. 44 * Once the use of sync prims is no longer supported, we will retain 45 * the same total (64) as the number of sync checkpoints which may be 46 * supporting a fence is not visible to the client driver and has to 47 * allow for the number of different timelines involved in fence merges. 48 */ 49 #define ROGUE_FWIF_CCB_CMD_MAX_UFOS (32U + 32U) 50 51 /** 52 * This is a generic limit imposed on any DM (TA,3D,CDM,TDM,2D,TRANSFER) 53 * command passed through the bridge. 54 * Just across the bridge in the server, any incoming kick command size is 55 * checked against this maximum limit. 56 * In case the incoming command size is larger than the specified limit, 57 * the bridge call is retired with error. 58 */ 59 #define ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE (1024U) 60 61 struct rogue_fwif_dev_addr { 62 uint32_t addr; 63 }; 64 65 struct rogue_fwif_dma_addr { 66 uint64_t ALIGN_ATTR(8) dev_vaddr; 67 struct rogue_fwif_dev_addr fw_addr; 68 uint32_t padding; 69 } ALIGN_ATTR(8); 70 71 /** 72 * \brief Command data for fence & update types Client CCB commands. 73 */ 74 struct rogue_fwif_ufo { 75 /** Address to be checked/updated. */ 76 struct rogue_fwif_dev_addr ufo_addr; 77 /** Value to check-against/update-to. */ 78 uint32_t value; 79 }; 80 81 struct rogue_fwif_cleanup_ctl { 82 /** Number of commands received by the FW. */ 83 uint32_t submitted_cmds; 84 85 /** Number of commands executed by the FW. */ 86 uint32_t executed_cmds; 87 } ALIGN_ATTR(8); 88 89 #define ROGUE_FWIF_PRBUFFER_START 0U 90 #define ROGUE_FWIF_PRBUFFER_ZSBUFFER 0U 91 #define ROGUE_FWIF_PRBUFFER_MSAABUFFER 1U 92 #define ROGUE_FWIF_PRBUFFER_MAXSUPPORTED 2U 93 94 enum rogue_fwif_prbuffer_state { 95 ROGUE_FWIF_PRBUFFER_UNBACKED = 0, 96 ROGUE_FWIF_PRBUFFER_BACKED, 97 ROGUE_FWIF_PRBUFFER_BACKING_PENDING, 98 ROGUE_FWIF_PRBUFFER_UNBACKING_PENDING, 99 }; 100 101 /** 102 * \brief On-demand Z/S/MSAA buffers. 103 */ 104 struct rogue_fwif_prbuffer { 105 /** Buffer ID. */ 106 uint32_t buffer_id; 107 /** Needs on-demand Z/S/MSAA buffer allocation. */ 108 bool ALIGN_ATTR(4) on_demand; 109 /** Z/S/MSAA - Buffer state. */ 110 enum rogue_fwif_prbuffer_state state; 111 /** Cleanup state. */ 112 struct rogue_fwif_cleanup_ctl cleanup_state; 113 /** Compatibility and other flags. */ 114 uint32_t pr_buffer_flags; 115 } ALIGN_ATTR(8); 116 117 /** 118 * Used to share frame numbers across UM-KM-FW, 119 * frame number is set in UM, 120 * frame number is required in both KM for HTB and FW for FW trace. 121 * 122 * May be used to house Kick flags in the future. 123 */ 124 struct rogue_fwif_cmd_common { 125 /** Associated frame number. */ 126 uint32_t frame_num; 127 }; 128 129 /** 130 * TA and 3D commands require set of firmware addresses that are stored in the 131 * Kernel. Client has handle(s) to Kernel containers storing these addresses, 132 * instead of raw addresses. We have to patch/write these addresses in KM to 133 * prevent UM from controlling FW addresses directly. 134 * Structures for TA and 3D commands are shared between Client and Firmware 135 * (both single-BVNC). Kernel is implemented in a multi-BVNC manner, so it can't 136 * use TA|3D CMD type definitions directly. Therefore we have a SHARED block 137 * that is shared between UM-KM-FW across all BVNC configurations. 138 */ 139 struct rogue_fwif_cmd_ta_3d_shared { 140 /** Common command attributes. */ 141 struct rogue_fwif_cmd_common cmn; 142 143 /** 144 * RTData associated with this command, this is used for context 145 * selection and for storing out HW-context, when TA is switched out for 146 * continuing later. 147 */ 148 struct rogue_fwif_dev_addr hw_rt_data; 149 150 /** Supported PR Buffers like Z/S/MSAA Scratch. */ 151 struct rogue_fwif_dev_addr pr_buffers[ROGUE_FWIF_PRBUFFER_MAXSUPPORTED]; 152 }; 153 154 /** 155 * Client Circular Command Buffer (CCCB) control structure. 156 * This is shared between the KM driver and the Firmware and holds byte offsets 157 * into the CCCB as well as the wrapping mask to aid wrap around. A given 158 * snapshot of this queue with Cmd 1 running on the GPU might be: 159 * 160 * Roff Doff Woff 161 * [..........|-1----------|=2===|=3===|=4===|~5~~~~|~6~~~~|~7~~~~|..........] 162 * < runnable commands >< !ready to run > 163 * 164 * Cmd 1 : Currently executing on the GPU data master. 165 * Cmd 2,3,4: Fence dependencies met, commands runnable. 166 * Cmd 5... : Fence dependency not met yet. 167 */ 168 struct rogue_fwif_cccb_ctl { 169 /** Host write offset into CCB. This must be aligned to 16 bytes. */ 170 uint32_t write_offset; 171 172 /** 173 * Firmware read offset into CCB. Points to the command that is runnable 174 * on GPU, if R!=W. 175 */ 176 uint32_t read_offset; 177 178 /** 179 * Firmware fence dependency offset. Points to commands not ready, i.e. 180 * fence dependencies are not met. 181 */ 182 uint32_t dep_offset; 183 184 /** Offset wrapping mask, total capacity in bytes of the CCB-1. */ 185 uint32_t wrap_mask; 186 187 /* Only used if SUPPORT_AGP is present. */ 188 uint32_t read_offset2; 189 190 /* Only used if SUPPORT_AGP4 is present. */ 191 uint32_t read_offset3; 192 /* Only used if SUPPORT_AGP4 is present. */ 193 uint32_t read_offset4; 194 195 uint32_t padding; 196 } ALIGN_ATTR(8); 197 198 #define ROGUE_FW_LOCAL_FREELIST 0U 199 #define ROGUE_FW_GLOBAL_FREELIST 1U 200 #define ROGUE_FW_MAX_FREELISTS (ROGUE_FW_GLOBAL_FREELIST + 1U) 201 #define ROGUE_FW_MAX_HWFREELISTS 2U 202 203 /** 204 * \brief Geom DM or TA register controls for context switch. 205 */ 206 struct rogue_fwif_ta_regs_cswitch { 207 /** The base address of the VDM's context state buffer. */ 208 uint64_t vdm_context_state_base_addr; 209 uint64_t vdm_context_state_resume_addr; 210 /** The base address of the TA's context state buffer. */ 211 uint64_t ta_context_state_base_addr; 212 213 struct { 214 /** VDM context store task 0. */ 215 uint64_t vdm_context_store_task0; 216 /** VDM context store task 1. */ 217 uint64_t vdm_context_store_task1; 218 /** VDM context store task 2. */ 219 uint64_t vdm_context_store_task2; 220 221 /* VDM resume state update controls. */ 222 /** VDM context resume task 0. */ 223 uint64_t vdm_context_resume_task0; 224 /** VDM context resume task 1. */ 225 uint64_t vdm_context_resume_task1; 226 /** VDM context resume task 2. */ 227 uint64_t vdm_context_resume_task2; 228 229 uint64_t vdm_context_store_task3; 230 uint64_t vdm_context_store_task4; 231 232 uint64_t vdm_context_resume_task3; 233 uint64_t vdm_context_resume_task4; 234 } ta_state[2]; 235 }; 236 237 #define ROGUE_FWIF_TAREGISTERS_CSWITCH_SIZE \ 238 sizeof(struct rogue_fwif_taregisters_cswitch) 239 240 struct rogue_fwif_cdm_regs_cswitch { 241 uint64_t cdm_context_pds0; 242 uint64_t cdm_context_pds1; 243 uint64_t cdm_terminate_pds; 244 uint64_t cdm_terminate_pds1; 245 246 /* CDM resume controls. */ 247 uint64_t cdm_resume_pds0; 248 uint64_t cdm_context_pds0_b; 249 uint64_t cdm_resume_pds0_b; 250 }; 251 252 /** 253 * \brief Render context static register controls for context switch. 254 */ 255 struct rogue_fwif_static_rendercontext_state { 256 /** Geom registers for ctx switch. */ 257 struct rogue_fwif_ta_regs_cswitch 258 ALIGN_ATTR(8) ctx_switch_geom_regs[ROGUE_NUM_GEOM_CORES_SIZE]; 259 }; 260 261 #define ROGUE_FWIF_STATIC_RENDERCONTEXT_SIZE \ 262 sizeof(struct rogue_fwif_static_rendercontext_state) 263 264 struct rogue_fwif_static_computecontext_state { 265 /** CDM registers for ctx switch. */ 266 struct rogue_fwif_cdm_regs_cswitch ALIGN_ATTR(8) ctx_switch_regs; 267 }; 268 269 #define ROGUE_FWIF_STATIC_COMPUTECONTEXT_SIZE \ 270 sizeof(struct rogue_fwif_static_computecontext_state) 271 272 /** 273 * /brief Context reset reason. Last reset reason for a reset context. 274 */ 275 enum rogue_context_reset_reason { 276 /** No reset reason recorded. */ 277 ROGUE_CONTEXT_RESET_REASON_NONE = 0, 278 /** Caused a reset due to locking up. */ 279 ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP = 1, 280 /** Affected by another context locking up. */ 281 ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP = 2, 282 /** Overran the global deadline. */ 283 ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING = 3, 284 /** Affected by another context overrunning. */ 285 ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4, 286 /** Forced reset to ensure scheduling requirements. */ 287 ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5, 288 /** FW page fault (no HWR). */ 289 ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT = 13, 290 /** FW execution error (GPU reset requested). */ 291 ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR = 14, 292 /** Host watchdog detected FW error. */ 293 ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR = 15, 294 /** Geometry DM OOM event is not allowed. */ 295 ROGUE_CONTEXT_GEOM_OOM_DISABLED = 16, 296 }; 297 298 /** 299 * \brief Context reset data shared with the host. 300 */ 301 struct rogue_context_reset_reason_data { 302 /** Reset reason. */ 303 enum rogue_context_reset_reason reset_reason; 304 /** External Job ID. */ 305 uint32_t reset_ext_job_ref; 306 }; 307 308 #endif /* PVR_ROGUE_FWIF_SHARED_H */ 309