1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
10 */
11 #include <linux/init.h>
12 #include <linux/utsname.h>
13 #include <linux/cpu.h>
14 #include <linux/module.h>
15 #include <linux/nospec.h>
16 #include <linux/prctl.h>
17 #include <linux/sched/smt.h>
18 #include <linux/pgtable.h>
19 #include <linux/bpf.h>
20
21 #include <asm/spec-ctrl.h>
22 #include <asm/cmdline.h>
23 #include <asm/bugs.h>
24 #include <asm/processor.h>
25 #include <asm/processor-flags.h>
26 #include <asm/fpu/internal.h>
27 #include <asm/msr.h>
28 #include <asm/vmx.h>
29 #include <asm/paravirt.h>
30 #include <asm/alternative.h>
31 #include <asm/set_memory.h>
32 #include <asm/intel-family.h>
33 #include <asm/e820/api.h>
34 #include <asm/hypervisor.h>
35 #include <asm/tlbflush.h>
36
37 #include "cpu.h"
38
39 static void __init spectre_v1_select_mitigation(void);
40 static void __init spectre_v2_select_mitigation(void);
41 static void __init retbleed_select_mitigation(void);
42 static void __init spectre_v2_user_select_mitigation(void);
43 static void __init ssb_select_mitigation(void);
44 static void __init l1tf_select_mitigation(void);
45 static void __init mds_select_mitigation(void);
46 static void __init md_clear_update_mitigation(void);
47 static void __init md_clear_select_mitigation(void);
48 static void __init taa_select_mitigation(void);
49 static void __init mmio_select_mitigation(void);
50 static void __init srbds_select_mitigation(void);
51
52 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
53 u64 x86_spec_ctrl_base;
54 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
55
56 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
57 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
58 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
59
60 static DEFINE_MUTEX(spec_ctrl_mutex);
61
62 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
update_spec_ctrl(u64 val)63 static void update_spec_ctrl(u64 val)
64 {
65 this_cpu_write(x86_spec_ctrl_current, val);
66 wrmsrl(MSR_IA32_SPEC_CTRL, val);
67 }
68
69 /*
70 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
71 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
72 */
update_spec_ctrl_cond(u64 val)73 void update_spec_ctrl_cond(u64 val)
74 {
75 if (this_cpu_read(x86_spec_ctrl_current) == val)
76 return;
77
78 this_cpu_write(x86_spec_ctrl_current, val);
79
80 /*
81 * When KERNEL_IBRS this MSR is written on return-to-user, unless
82 * forced the update can be delayed until that time.
83 */
84 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
85 wrmsrl(MSR_IA32_SPEC_CTRL, val);
86 }
87
spec_ctrl_current(void)88 u64 spec_ctrl_current(void)
89 {
90 return this_cpu_read(x86_spec_ctrl_current);
91 }
92 EXPORT_SYMBOL_GPL(spec_ctrl_current);
93
94 /*
95 * AMD specific MSR info for Speculative Store Bypass control.
96 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
97 */
98 u64 __ro_after_init x86_amd_ls_cfg_base;
99 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
100
101 /* Control conditional STIBP in switch_to() */
102 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
103 /* Control conditional IBPB in switch_mm() */
104 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
105 /* Control unconditional IBPB in switch_mm() */
106 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
107
108 /* Control MDS CPU buffer clear before returning to user space */
109 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
110 EXPORT_SYMBOL_GPL(mds_user_clear);
111 /* Control MDS CPU buffer clear before idling (halt, mwait) */
112 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
113 EXPORT_SYMBOL_GPL(mds_idle_clear);
114
115 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
116 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
117 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
118
check_bugs(void)119 void __init check_bugs(void)
120 {
121 identify_boot_cpu();
122
123 /*
124 * identify_boot_cpu() initialized SMT support information, let the
125 * core code know.
126 */
127 cpu_smt_check_topology();
128
129 if (!IS_ENABLED(CONFIG_SMP)) {
130 pr_info("CPU: ");
131 print_cpu_info(&boot_cpu_data);
132 }
133
134 /*
135 * Read the SPEC_CTRL MSR to account for reserved bits which may
136 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
137 * init code as it is not enumerated and depends on the family.
138 */
139 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
140 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
141
142 /* Select the proper CPU mitigations before patching alternatives: */
143 spectre_v1_select_mitigation();
144 spectre_v2_select_mitigation();
145 /*
146 * retbleed_select_mitigation() relies on the state set by
147 * spectre_v2_select_mitigation(); specifically it wants to know about
148 * spectre_v2=ibrs.
149 */
150 retbleed_select_mitigation();
151 /*
152 * spectre_v2_user_select_mitigation() relies on the state set by
153 * retbleed_select_mitigation(); specifically the STIBP selection is
154 * forced for UNRET or IBPB.
155 */
156 spectre_v2_user_select_mitigation();
157 ssb_select_mitigation();
158 l1tf_select_mitigation();
159 md_clear_select_mitigation();
160 srbds_select_mitigation();
161
162 arch_smt_update();
163
164 #ifdef CONFIG_X86_32
165 /*
166 * Check whether we are able to run this kernel safely on SMP.
167 *
168 * - i386 is no longer supported.
169 * - In order to run on anything without a TSC, we need to be
170 * compiled for a i486.
171 */
172 if (boot_cpu_data.x86 < 4)
173 panic("Kernel requires i486+ for 'invlpg' and other features");
174
175 init_utsname()->machine[1] =
176 '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
177 alternative_instructions();
178
179 fpu__init_check_bugs();
180 #else /* CONFIG_X86_64 */
181 alternative_instructions();
182
183 /*
184 * Make sure the first 2MB area is not mapped by huge pages
185 * There are typically fixed size MTRRs in there and overlapping
186 * MTRRs into large pages causes slow downs.
187 *
188 * Right now we don't do that with gbpages because there seems
189 * very little benefit for that case.
190 */
191 if (!direct_gbpages)
192 set_memory_4k((unsigned long)__va(0), 1);
193 #endif
194 }
195
196 /*
197 * NOTE: For VMX, this function is not called in the vmexit path.
198 * It uses vmx_spec_ctrl_restore_host() instead.
199 */
200 void
x86_virt_spec_ctrl(u64 guest_spec_ctrl,u64 guest_virt_spec_ctrl,bool setguest)201 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
202 {
203 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
204 struct thread_info *ti = current_thread_info();
205
206 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
207 if (hostval != guestval) {
208 msrval = setguest ? guestval : hostval;
209 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
210 }
211 }
212
213 /*
214 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
215 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
216 */
217 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
218 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
219 return;
220
221 /*
222 * If the host has SSBD mitigation enabled, force it in the host's
223 * virtual MSR value. If its not permanently enabled, evaluate
224 * current's TIF_SSBD thread flag.
225 */
226 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
227 hostval = SPEC_CTRL_SSBD;
228 else
229 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
230
231 /* Sanitize the guest value */
232 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
233
234 if (hostval != guestval) {
235 unsigned long tif;
236
237 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
238 ssbd_spec_ctrl_to_tif(hostval);
239
240 speculation_ctrl_update(tif);
241 }
242 }
243 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
244
x86_amd_ssb_disable(void)245 static void x86_amd_ssb_disable(void)
246 {
247 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
248
249 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
250 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
251 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
252 wrmsrl(MSR_AMD64_LS_CFG, msrval);
253 }
254
255 #undef pr_fmt
256 #define pr_fmt(fmt) "MDS: " fmt
257
258 /* Default mitigation for MDS-affected CPUs */
259 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
260 static bool mds_nosmt __ro_after_init = false;
261
262 static const char * const mds_strings[] = {
263 [MDS_MITIGATION_OFF] = "Vulnerable",
264 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
265 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
266 };
267
mds_select_mitigation(void)268 static void __init mds_select_mitigation(void)
269 {
270 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
271 mds_mitigation = MDS_MITIGATION_OFF;
272 return;
273 }
274
275 if (mds_mitigation == MDS_MITIGATION_FULL) {
276 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
277 mds_mitigation = MDS_MITIGATION_VMWERV;
278
279 static_branch_enable(&mds_user_clear);
280
281 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
282 (mds_nosmt || cpu_mitigations_auto_nosmt()))
283 cpu_smt_disable(false);
284 }
285 }
286
mds_cmdline(char * str)287 static int __init mds_cmdline(char *str)
288 {
289 if (!boot_cpu_has_bug(X86_BUG_MDS))
290 return 0;
291
292 if (!str)
293 return -EINVAL;
294
295 if (!strcmp(str, "off"))
296 mds_mitigation = MDS_MITIGATION_OFF;
297 else if (!strcmp(str, "full"))
298 mds_mitigation = MDS_MITIGATION_FULL;
299 else if (!strcmp(str, "full,nosmt")) {
300 mds_mitigation = MDS_MITIGATION_FULL;
301 mds_nosmt = true;
302 }
303
304 return 0;
305 }
306 early_param("mds", mds_cmdline);
307
308 #undef pr_fmt
309 #define pr_fmt(fmt) "TAA: " fmt
310
311 enum taa_mitigations {
312 TAA_MITIGATION_OFF,
313 TAA_MITIGATION_UCODE_NEEDED,
314 TAA_MITIGATION_VERW,
315 TAA_MITIGATION_TSX_DISABLED,
316 };
317
318 /* Default mitigation for TAA-affected CPUs */
319 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
320 static bool taa_nosmt __ro_after_init;
321
322 static const char * const taa_strings[] = {
323 [TAA_MITIGATION_OFF] = "Vulnerable",
324 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
325 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
326 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
327 };
328
taa_select_mitigation(void)329 static void __init taa_select_mitigation(void)
330 {
331 u64 ia32_cap;
332
333 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
334 taa_mitigation = TAA_MITIGATION_OFF;
335 return;
336 }
337
338 /* TSX previously disabled by tsx=off */
339 if (!boot_cpu_has(X86_FEATURE_RTM)) {
340 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
341 return;
342 }
343
344 if (cpu_mitigations_off()) {
345 taa_mitigation = TAA_MITIGATION_OFF;
346 return;
347 }
348
349 /*
350 * TAA mitigation via VERW is turned off if both
351 * tsx_async_abort=off and mds=off are specified.
352 */
353 if (taa_mitigation == TAA_MITIGATION_OFF &&
354 mds_mitigation == MDS_MITIGATION_OFF)
355 return;
356
357 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
358 taa_mitigation = TAA_MITIGATION_VERW;
359 else
360 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
361
362 /*
363 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
364 * A microcode update fixes this behavior to clear CPU buffers. It also
365 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
366 * ARCH_CAP_TSX_CTRL_MSR bit.
367 *
368 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
369 * update is required.
370 */
371 ia32_cap = x86_read_arch_cap_msr();
372 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
373 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
374 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
375
376 /*
377 * TSX is enabled, select alternate mitigation for TAA which is
378 * the same as MDS. Enable MDS static branch to clear CPU buffers.
379 *
380 * For guests that can't determine whether the correct microcode is
381 * present on host, enable the mitigation for UCODE_NEEDED as well.
382 */
383 static_branch_enable(&mds_user_clear);
384
385 if (taa_nosmt || cpu_mitigations_auto_nosmt())
386 cpu_smt_disable(false);
387 }
388
tsx_async_abort_parse_cmdline(char * str)389 static int __init tsx_async_abort_parse_cmdline(char *str)
390 {
391 if (!boot_cpu_has_bug(X86_BUG_TAA))
392 return 0;
393
394 if (!str)
395 return -EINVAL;
396
397 if (!strcmp(str, "off")) {
398 taa_mitigation = TAA_MITIGATION_OFF;
399 } else if (!strcmp(str, "full")) {
400 taa_mitigation = TAA_MITIGATION_VERW;
401 } else if (!strcmp(str, "full,nosmt")) {
402 taa_mitigation = TAA_MITIGATION_VERW;
403 taa_nosmt = true;
404 }
405
406 return 0;
407 }
408 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
409
410 #undef pr_fmt
411 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
412
413 enum mmio_mitigations {
414 MMIO_MITIGATION_OFF,
415 MMIO_MITIGATION_UCODE_NEEDED,
416 MMIO_MITIGATION_VERW,
417 };
418
419 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
420 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
421 static bool mmio_nosmt __ro_after_init = false;
422
423 static const char * const mmio_strings[] = {
424 [MMIO_MITIGATION_OFF] = "Vulnerable",
425 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
426 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
427 };
428
mmio_select_mitigation(void)429 static void __init mmio_select_mitigation(void)
430 {
431 u64 ia32_cap;
432
433 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
434 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
435 cpu_mitigations_off()) {
436 mmio_mitigation = MMIO_MITIGATION_OFF;
437 return;
438 }
439
440 if (mmio_mitigation == MMIO_MITIGATION_OFF)
441 return;
442
443 ia32_cap = x86_read_arch_cap_msr();
444
445 /*
446 * Enable CPU buffer clear mitigation for host and VMM, if also affected
447 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
448 */
449 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
450 boot_cpu_has(X86_FEATURE_RTM)))
451 static_branch_enable(&mds_user_clear);
452 else
453 static_branch_enable(&mmio_stale_data_clear);
454
455 /*
456 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
457 * be propagated to uncore buffers, clearing the Fill buffers on idle
458 * is required irrespective of SMT state.
459 */
460 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
461 static_branch_enable(&mds_idle_clear);
462
463 /*
464 * Check if the system has the right microcode.
465 *
466 * CPU Fill buffer clear mitigation is enumerated by either an explicit
467 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
468 * affected systems.
469 */
470 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
471 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
472 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
473 !(ia32_cap & ARCH_CAP_MDS_NO)))
474 mmio_mitigation = MMIO_MITIGATION_VERW;
475 else
476 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
477
478 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
479 cpu_smt_disable(false);
480 }
481
mmio_stale_data_parse_cmdline(char * str)482 static int __init mmio_stale_data_parse_cmdline(char *str)
483 {
484 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
485 return 0;
486
487 if (!str)
488 return -EINVAL;
489
490 if (!strcmp(str, "off")) {
491 mmio_mitigation = MMIO_MITIGATION_OFF;
492 } else if (!strcmp(str, "full")) {
493 mmio_mitigation = MMIO_MITIGATION_VERW;
494 } else if (!strcmp(str, "full,nosmt")) {
495 mmio_mitigation = MMIO_MITIGATION_VERW;
496 mmio_nosmt = true;
497 }
498
499 return 0;
500 }
501 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
502
503 #undef pr_fmt
504 #define pr_fmt(fmt) "" fmt
505
md_clear_update_mitigation(void)506 static void __init md_clear_update_mitigation(void)
507 {
508 if (cpu_mitigations_off())
509 return;
510
511 if (!static_key_enabled(&mds_user_clear))
512 goto out;
513
514 /*
515 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
516 * mitigation, if necessary.
517 */
518 if (mds_mitigation == MDS_MITIGATION_OFF &&
519 boot_cpu_has_bug(X86_BUG_MDS)) {
520 mds_mitigation = MDS_MITIGATION_FULL;
521 mds_select_mitigation();
522 }
523 if (taa_mitigation == TAA_MITIGATION_OFF &&
524 boot_cpu_has_bug(X86_BUG_TAA)) {
525 taa_mitigation = TAA_MITIGATION_VERW;
526 taa_select_mitigation();
527 }
528 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
529 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
530 mmio_mitigation = MMIO_MITIGATION_VERW;
531 mmio_select_mitigation();
532 }
533 out:
534 if (boot_cpu_has_bug(X86_BUG_MDS))
535 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
536 if (boot_cpu_has_bug(X86_BUG_TAA))
537 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
538 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
539 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
540 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
541 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
542 }
543
md_clear_select_mitigation(void)544 static void __init md_clear_select_mitigation(void)
545 {
546 mds_select_mitigation();
547 taa_select_mitigation();
548 mmio_select_mitigation();
549
550 /*
551 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
552 * and print their mitigation after MDS, TAA and MMIO Stale Data
553 * mitigation selection is done.
554 */
555 md_clear_update_mitigation();
556 }
557
558 #undef pr_fmt
559 #define pr_fmt(fmt) "SRBDS: " fmt
560
561 enum srbds_mitigations {
562 SRBDS_MITIGATION_OFF,
563 SRBDS_MITIGATION_UCODE_NEEDED,
564 SRBDS_MITIGATION_FULL,
565 SRBDS_MITIGATION_TSX_OFF,
566 SRBDS_MITIGATION_HYPERVISOR,
567 };
568
569 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
570
571 static const char * const srbds_strings[] = {
572 [SRBDS_MITIGATION_OFF] = "Vulnerable",
573 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
574 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
575 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
576 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
577 };
578
579 static bool srbds_off;
580
update_srbds_msr(void)581 void update_srbds_msr(void)
582 {
583 u64 mcu_ctrl;
584
585 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
586 return;
587
588 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
589 return;
590
591 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
592 return;
593
594 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
595
596 switch (srbds_mitigation) {
597 case SRBDS_MITIGATION_OFF:
598 case SRBDS_MITIGATION_TSX_OFF:
599 mcu_ctrl |= RNGDS_MITG_DIS;
600 break;
601 case SRBDS_MITIGATION_FULL:
602 mcu_ctrl &= ~RNGDS_MITG_DIS;
603 break;
604 default:
605 break;
606 }
607
608 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
609 }
610
srbds_select_mitigation(void)611 static void __init srbds_select_mitigation(void)
612 {
613 u64 ia32_cap;
614
615 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
616 return;
617
618 /*
619 * Check to see if this is one of the MDS_NO systems supporting TSX that
620 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
621 * by Processor MMIO Stale Data vulnerability.
622 */
623 ia32_cap = x86_read_arch_cap_msr();
624 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
625 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
626 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
627 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
628 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
629 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
630 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
631 else if (cpu_mitigations_off() || srbds_off)
632 srbds_mitigation = SRBDS_MITIGATION_OFF;
633
634 update_srbds_msr();
635 pr_info("%s\n", srbds_strings[srbds_mitigation]);
636 }
637
srbds_parse_cmdline(char * str)638 static int __init srbds_parse_cmdline(char *str)
639 {
640 if (!str)
641 return -EINVAL;
642
643 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
644 return 0;
645
646 srbds_off = !strcmp(str, "off");
647 return 0;
648 }
649 early_param("srbds", srbds_parse_cmdline);
650
651 #undef pr_fmt
652 #define pr_fmt(fmt) "Spectre V1 : " fmt
653
654 enum spectre_v1_mitigation {
655 SPECTRE_V1_MITIGATION_NONE,
656 SPECTRE_V1_MITIGATION_AUTO,
657 };
658
659 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
660 SPECTRE_V1_MITIGATION_AUTO;
661
662 static const char * const spectre_v1_strings[] = {
663 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
664 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
665 };
666
667 /*
668 * Does SMAP provide full mitigation against speculative kernel access to
669 * userspace?
670 */
smap_works_speculatively(void)671 static bool smap_works_speculatively(void)
672 {
673 if (!boot_cpu_has(X86_FEATURE_SMAP))
674 return false;
675
676 /*
677 * On CPUs which are vulnerable to Meltdown, SMAP does not
678 * prevent speculative access to user data in the L1 cache.
679 * Consider SMAP to be non-functional as a mitigation on these
680 * CPUs.
681 */
682 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
683 return false;
684
685 return true;
686 }
687
spectre_v1_select_mitigation(void)688 static void __init spectre_v1_select_mitigation(void)
689 {
690 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
691 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
692 return;
693 }
694
695 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
696 /*
697 * With Spectre v1, a user can speculatively control either
698 * path of a conditional swapgs with a user-controlled GS
699 * value. The mitigation is to add lfences to both code paths.
700 *
701 * If FSGSBASE is enabled, the user can put a kernel address in
702 * GS, in which case SMAP provides no protection.
703 *
704 * If FSGSBASE is disabled, the user can only put a user space
705 * address in GS. That makes an attack harder, but still
706 * possible if there's no SMAP protection.
707 */
708 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
709 !smap_works_speculatively()) {
710 /*
711 * Mitigation can be provided from SWAPGS itself or
712 * PTI as the CR3 write in the Meltdown mitigation
713 * is serializing.
714 *
715 * If neither is there, mitigate with an LFENCE to
716 * stop speculation through swapgs.
717 */
718 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
719 !boot_cpu_has(X86_FEATURE_PTI))
720 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
721
722 /*
723 * Enable lfences in the kernel entry (non-swapgs)
724 * paths, to prevent user entry from speculatively
725 * skipping swapgs.
726 */
727 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
728 }
729 }
730
731 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
732 }
733
nospectre_v1_cmdline(char * str)734 static int __init nospectre_v1_cmdline(char *str)
735 {
736 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
737 return 0;
738 }
739 early_param("nospectre_v1", nospectre_v1_cmdline);
740
741 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
742 SPECTRE_V2_NONE;
743
744 #undef pr_fmt
745 #define pr_fmt(fmt) "RETBleed: " fmt
746
747 enum retbleed_mitigation {
748 RETBLEED_MITIGATION_NONE,
749 RETBLEED_MITIGATION_UNRET,
750 RETBLEED_MITIGATION_IBPB,
751 RETBLEED_MITIGATION_IBRS,
752 RETBLEED_MITIGATION_EIBRS,
753 };
754
755 enum retbleed_mitigation_cmd {
756 RETBLEED_CMD_OFF,
757 RETBLEED_CMD_AUTO,
758 RETBLEED_CMD_UNRET,
759 RETBLEED_CMD_IBPB,
760 };
761
762 const char * const retbleed_strings[] = {
763 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
764 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
765 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
766 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
767 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
768 };
769
770 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
771 RETBLEED_MITIGATION_NONE;
772 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
773 RETBLEED_CMD_AUTO;
774
775 static int __ro_after_init retbleed_nosmt = false;
776
retbleed_parse_cmdline(char * str)777 static int __init retbleed_parse_cmdline(char *str)
778 {
779 if (!str)
780 return -EINVAL;
781
782 while (str) {
783 char *next = strchr(str, ',');
784 if (next) {
785 *next = 0;
786 next++;
787 }
788
789 if (!strcmp(str, "off")) {
790 retbleed_cmd = RETBLEED_CMD_OFF;
791 } else if (!strcmp(str, "auto")) {
792 retbleed_cmd = RETBLEED_CMD_AUTO;
793 } else if (!strcmp(str, "unret")) {
794 retbleed_cmd = RETBLEED_CMD_UNRET;
795 } else if (!strcmp(str, "ibpb")) {
796 retbleed_cmd = RETBLEED_CMD_IBPB;
797 } else if (!strcmp(str, "nosmt")) {
798 retbleed_nosmt = true;
799 } else {
800 pr_err("Ignoring unknown retbleed option (%s).", str);
801 }
802
803 str = next;
804 }
805
806 return 0;
807 }
808 early_param("retbleed", retbleed_parse_cmdline);
809
810 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
811 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
812
retbleed_select_mitigation(void)813 static void __init retbleed_select_mitigation(void)
814 {
815 bool mitigate_smt = false;
816
817 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
818 return;
819
820 switch (retbleed_cmd) {
821 case RETBLEED_CMD_OFF:
822 return;
823
824 case RETBLEED_CMD_UNRET:
825 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
826 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
827 } else {
828 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
829 goto do_cmd_auto;
830 }
831 break;
832
833 case RETBLEED_CMD_IBPB:
834 if (!boot_cpu_has(X86_FEATURE_IBPB)) {
835 pr_err("WARNING: CPU does not support IBPB.\n");
836 goto do_cmd_auto;
837 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
838 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
839 } else {
840 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
841 goto do_cmd_auto;
842 }
843 break;
844
845 do_cmd_auto:
846 case RETBLEED_CMD_AUTO:
847 default:
848 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
849 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
850 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
851 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
852 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
853 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
854 }
855
856 /*
857 * The Intel mitigation (IBRS or eIBRS) was already selected in
858 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
859 * be set accordingly below.
860 */
861
862 break;
863 }
864
865 switch (retbleed_mitigation) {
866 case RETBLEED_MITIGATION_UNRET:
867 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
868 setup_force_cpu_cap(X86_FEATURE_UNRET);
869
870 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
871 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
872 pr_err(RETBLEED_UNTRAIN_MSG);
873
874 mitigate_smt = true;
875 break;
876
877 case RETBLEED_MITIGATION_IBPB:
878 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
879 mitigate_smt = true;
880 break;
881
882 default:
883 break;
884 }
885
886 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
887 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
888 cpu_smt_disable(false);
889
890 /*
891 * Let IBRS trump all on Intel without affecting the effects of the
892 * retbleed= cmdline option.
893 */
894 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
895 switch (spectre_v2_enabled) {
896 case SPECTRE_V2_IBRS:
897 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
898 break;
899 case SPECTRE_V2_EIBRS:
900 case SPECTRE_V2_EIBRS_RETPOLINE:
901 case SPECTRE_V2_EIBRS_LFENCE:
902 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
903 break;
904 default:
905 pr_err(RETBLEED_INTEL_MSG);
906 }
907 }
908
909 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
910 }
911
912 #undef pr_fmt
913 #define pr_fmt(fmt) "Spectre V2 : " fmt
914
915 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
916 SPECTRE_V2_USER_NONE;
917 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
918 SPECTRE_V2_USER_NONE;
919
920 #ifdef CONFIG_RETPOLINE
921 static bool spectre_v2_bad_module;
922
retpoline_module_ok(bool has_retpoline)923 bool retpoline_module_ok(bool has_retpoline)
924 {
925 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
926 return true;
927
928 pr_err("System may be vulnerable to spectre v2\n");
929 spectre_v2_bad_module = true;
930 return false;
931 }
932
spectre_v2_module_string(void)933 static inline const char *spectre_v2_module_string(void)
934 {
935 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
936 }
937 #else
spectre_v2_module_string(void)938 static inline const char *spectre_v2_module_string(void) { return ""; }
939 #endif
940
941 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
942 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
943 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
944 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
945
946 #ifdef CONFIG_BPF_SYSCALL
unpriv_ebpf_notify(int new_state)947 void unpriv_ebpf_notify(int new_state)
948 {
949 if (new_state)
950 return;
951
952 /* Unprivileged eBPF is enabled */
953
954 switch (spectre_v2_enabled) {
955 case SPECTRE_V2_EIBRS:
956 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
957 break;
958 case SPECTRE_V2_EIBRS_LFENCE:
959 if (sched_smt_active())
960 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
961 break;
962 default:
963 break;
964 }
965 }
966 #endif
967
match_option(const char * arg,int arglen,const char * opt)968 static inline bool match_option(const char *arg, int arglen, const char *opt)
969 {
970 int len = strlen(opt);
971
972 return len == arglen && !strncmp(arg, opt, len);
973 }
974
975 /* The kernel command line selection for spectre v2 */
976 enum spectre_v2_mitigation_cmd {
977 SPECTRE_V2_CMD_NONE,
978 SPECTRE_V2_CMD_AUTO,
979 SPECTRE_V2_CMD_FORCE,
980 SPECTRE_V2_CMD_RETPOLINE,
981 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
982 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
983 SPECTRE_V2_CMD_EIBRS,
984 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
985 SPECTRE_V2_CMD_EIBRS_LFENCE,
986 SPECTRE_V2_CMD_IBRS,
987 };
988
989 enum spectre_v2_user_cmd {
990 SPECTRE_V2_USER_CMD_NONE,
991 SPECTRE_V2_USER_CMD_AUTO,
992 SPECTRE_V2_USER_CMD_FORCE,
993 SPECTRE_V2_USER_CMD_PRCTL,
994 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
995 SPECTRE_V2_USER_CMD_SECCOMP,
996 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
997 };
998
999 static const char * const spectre_v2_user_strings[] = {
1000 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1001 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1002 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1003 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1004 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1005 };
1006
1007 static const struct {
1008 const char *option;
1009 enum spectre_v2_user_cmd cmd;
1010 bool secure;
1011 } v2_user_options[] __initconst = {
1012 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1013 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1014 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1015 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1016 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1017 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1018 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1019 };
1020
spec_v2_user_print_cond(const char * reason,bool secure)1021 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1022 {
1023 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1024 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1025 }
1026
1027 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1028
1029 static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(void)1030 spectre_v2_parse_user_cmdline(void)
1031 {
1032 char arg[20];
1033 int ret, i;
1034
1035 switch (spectre_v2_cmd) {
1036 case SPECTRE_V2_CMD_NONE:
1037 return SPECTRE_V2_USER_CMD_NONE;
1038 case SPECTRE_V2_CMD_FORCE:
1039 return SPECTRE_V2_USER_CMD_FORCE;
1040 default:
1041 break;
1042 }
1043
1044 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1045 arg, sizeof(arg));
1046 if (ret < 0)
1047 return SPECTRE_V2_USER_CMD_AUTO;
1048
1049 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1050 if (match_option(arg, ret, v2_user_options[i].option)) {
1051 spec_v2_user_print_cond(v2_user_options[i].option,
1052 v2_user_options[i].secure);
1053 return v2_user_options[i].cmd;
1054 }
1055 }
1056
1057 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1058 return SPECTRE_V2_USER_CMD_AUTO;
1059 }
1060
spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)1061 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
1062 {
1063 return mode == SPECTRE_V2_EIBRS ||
1064 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1065 mode == SPECTRE_V2_EIBRS_LFENCE;
1066 }
1067
spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)1068 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1069 {
1070 return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
1071 }
1072
1073 static void __init
spectre_v2_user_select_mitigation(void)1074 spectre_v2_user_select_mitigation(void)
1075 {
1076 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1077 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1078 enum spectre_v2_user_cmd cmd;
1079
1080 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1081 return;
1082
1083 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1084 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1085 smt_possible = false;
1086
1087 cmd = spectre_v2_parse_user_cmdline();
1088 switch (cmd) {
1089 case SPECTRE_V2_USER_CMD_NONE:
1090 goto set_mode;
1091 case SPECTRE_V2_USER_CMD_FORCE:
1092 mode = SPECTRE_V2_USER_STRICT;
1093 break;
1094 case SPECTRE_V2_USER_CMD_PRCTL:
1095 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1096 mode = SPECTRE_V2_USER_PRCTL;
1097 break;
1098 case SPECTRE_V2_USER_CMD_AUTO:
1099 case SPECTRE_V2_USER_CMD_SECCOMP:
1100 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1101 if (IS_ENABLED(CONFIG_SECCOMP))
1102 mode = SPECTRE_V2_USER_SECCOMP;
1103 else
1104 mode = SPECTRE_V2_USER_PRCTL;
1105 break;
1106 }
1107
1108 /* Initialize Indirect Branch Prediction Barrier */
1109 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1110 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1111
1112 spectre_v2_user_ibpb = mode;
1113 switch (cmd) {
1114 case SPECTRE_V2_USER_CMD_FORCE:
1115 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1116 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1117 static_branch_enable(&switch_mm_always_ibpb);
1118 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1119 break;
1120 case SPECTRE_V2_USER_CMD_PRCTL:
1121 case SPECTRE_V2_USER_CMD_AUTO:
1122 case SPECTRE_V2_USER_CMD_SECCOMP:
1123 static_branch_enable(&switch_mm_cond_ibpb);
1124 break;
1125 default:
1126 break;
1127 }
1128
1129 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1130 static_key_enabled(&switch_mm_always_ibpb) ?
1131 "always-on" : "conditional");
1132 }
1133
1134 /*
1135 * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
1136 * is not required.
1137 *
1138 * Enhanced IBRS also protects against cross-thread branch target
1139 * injection in user-mode as the IBRS bit remains always set which
1140 * implicitly enables cross-thread protections. However, in legacy IBRS
1141 * mode, the IBRS bit is set only on kernel entry and cleared on return
1142 * to userspace. This disables the implicit cross-thread protection,
1143 * so allow for STIBP to be selected in that case.
1144 */
1145 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1146 !smt_possible ||
1147 spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1148 return;
1149
1150 /*
1151 * At this point, an STIBP mode other than "off" has been set.
1152 * If STIBP support is not being forced, check if STIBP always-on
1153 * is preferred.
1154 */
1155 if (mode != SPECTRE_V2_USER_STRICT &&
1156 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1157 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1158
1159 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1160 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1161 if (mode != SPECTRE_V2_USER_STRICT &&
1162 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1163 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1164 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1165 }
1166
1167 spectre_v2_user_stibp = mode;
1168
1169 set_mode:
1170 pr_info("%s\n", spectre_v2_user_strings[mode]);
1171 }
1172
1173 static const char * const spectre_v2_strings[] = {
1174 [SPECTRE_V2_NONE] = "Vulnerable",
1175 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1176 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1177 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
1178 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
1179 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
1180 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1181 };
1182
1183 static const struct {
1184 const char *option;
1185 enum spectre_v2_mitigation_cmd cmd;
1186 bool secure;
1187 } mitigation_options[] __initconst = {
1188 { "off", SPECTRE_V2_CMD_NONE, false },
1189 { "on", SPECTRE_V2_CMD_FORCE, true },
1190 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1191 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1192 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1193 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1194 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1195 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1196 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1197 { "auto", SPECTRE_V2_CMD_AUTO, false },
1198 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1199 };
1200
spec_v2_print_cond(const char * reason,bool secure)1201 static void __init spec_v2_print_cond(const char *reason, bool secure)
1202 {
1203 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1204 pr_info("%s selected on command line.\n", reason);
1205 }
1206
spectre_v2_parse_cmdline(void)1207 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1208 {
1209 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1210 char arg[20];
1211 int ret, i;
1212
1213 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1214 cpu_mitigations_off())
1215 return SPECTRE_V2_CMD_NONE;
1216
1217 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1218 if (ret < 0)
1219 return SPECTRE_V2_CMD_AUTO;
1220
1221 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1222 if (!match_option(arg, ret, mitigation_options[i].option))
1223 continue;
1224 cmd = mitigation_options[i].cmd;
1225 break;
1226 }
1227
1228 if (i >= ARRAY_SIZE(mitigation_options)) {
1229 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1230 return SPECTRE_V2_CMD_AUTO;
1231 }
1232
1233 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1234 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1235 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1236 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1237 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1238 !IS_ENABLED(CONFIG_RETPOLINE)) {
1239 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1240 mitigation_options[i].option);
1241 return SPECTRE_V2_CMD_AUTO;
1242 }
1243
1244 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1245 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1246 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1247 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1248 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1249 mitigation_options[i].option);
1250 return SPECTRE_V2_CMD_AUTO;
1251 }
1252
1253 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1254 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1255 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1256 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1257 mitigation_options[i].option);
1258 return SPECTRE_V2_CMD_AUTO;
1259 }
1260
1261 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1262 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1263 mitigation_options[i].option);
1264 return SPECTRE_V2_CMD_AUTO;
1265 }
1266
1267 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1268 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1269 mitigation_options[i].option);
1270 return SPECTRE_V2_CMD_AUTO;
1271 }
1272
1273 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1274 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1275 mitigation_options[i].option);
1276 return SPECTRE_V2_CMD_AUTO;
1277 }
1278
1279 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1280 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1281 mitigation_options[i].option);
1282 return SPECTRE_V2_CMD_AUTO;
1283 }
1284
1285 spec_v2_print_cond(mitigation_options[i].option,
1286 mitigation_options[i].secure);
1287 return cmd;
1288 }
1289
spectre_v2_select_retpoline(void)1290 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1291 {
1292 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1293 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1294 return SPECTRE_V2_NONE;
1295 }
1296
1297 return SPECTRE_V2_RETPOLINE;
1298 }
1299
1300 /* Disable in-kernel use of non-RSB RET predictors */
spec_ctrl_disable_kernel_rrsba(void)1301 static void __init spec_ctrl_disable_kernel_rrsba(void)
1302 {
1303 u64 ia32_cap;
1304
1305 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1306 return;
1307
1308 ia32_cap = x86_read_arch_cap_msr();
1309
1310 if (ia32_cap & ARCH_CAP_RRSBA) {
1311 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1312 update_spec_ctrl(x86_spec_ctrl_base);
1313 }
1314 }
1315
spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)1316 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1317 {
1318 /*
1319 * Similar to context switches, there are two types of RSB attacks
1320 * after VM exit:
1321 *
1322 * 1) RSB underflow
1323 *
1324 * 2) Poisoned RSB entry
1325 *
1326 * When retpoline is enabled, both are mitigated by filling/clearing
1327 * the RSB.
1328 *
1329 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1330 * prediction isolation protections, RSB still needs to be cleared
1331 * because of #2. Note that SMEP provides no protection here, unlike
1332 * user-space-poisoned RSB entries.
1333 *
1334 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1335 * bug is present then a LITE version of RSB protection is required,
1336 * just a single call needs to retire before a RET is executed.
1337 */
1338 switch (mode) {
1339 case SPECTRE_V2_NONE:
1340 return;
1341
1342 case SPECTRE_V2_EIBRS_LFENCE:
1343 case SPECTRE_V2_EIBRS:
1344 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1345 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1346 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1347 }
1348 return;
1349
1350 case SPECTRE_V2_EIBRS_RETPOLINE:
1351 case SPECTRE_V2_RETPOLINE:
1352 case SPECTRE_V2_LFENCE:
1353 case SPECTRE_V2_IBRS:
1354 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1355 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1356 return;
1357 }
1358
1359 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1360 dump_stack();
1361 }
1362
spectre_v2_select_mitigation(void)1363 static void __init spectre_v2_select_mitigation(void)
1364 {
1365 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1366 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1367
1368 /*
1369 * If the CPU is not affected and the command line mode is NONE or AUTO
1370 * then nothing to do.
1371 */
1372 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1373 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1374 return;
1375
1376 switch (cmd) {
1377 case SPECTRE_V2_CMD_NONE:
1378 return;
1379
1380 case SPECTRE_V2_CMD_FORCE:
1381 case SPECTRE_V2_CMD_AUTO:
1382 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1383 mode = SPECTRE_V2_EIBRS;
1384 break;
1385 }
1386
1387 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1388 boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1389 retbleed_cmd != RETBLEED_CMD_OFF &&
1390 boot_cpu_has(X86_FEATURE_IBRS) &&
1391 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1392 mode = SPECTRE_V2_IBRS;
1393 break;
1394 }
1395
1396 mode = spectre_v2_select_retpoline();
1397 break;
1398
1399 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1400 pr_err(SPECTRE_V2_LFENCE_MSG);
1401 mode = SPECTRE_V2_LFENCE;
1402 break;
1403
1404 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1405 mode = SPECTRE_V2_RETPOLINE;
1406 break;
1407
1408 case SPECTRE_V2_CMD_RETPOLINE:
1409 mode = spectre_v2_select_retpoline();
1410 break;
1411
1412 case SPECTRE_V2_CMD_IBRS:
1413 mode = SPECTRE_V2_IBRS;
1414 break;
1415
1416 case SPECTRE_V2_CMD_EIBRS:
1417 mode = SPECTRE_V2_EIBRS;
1418 break;
1419
1420 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1421 mode = SPECTRE_V2_EIBRS_LFENCE;
1422 break;
1423
1424 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1425 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1426 break;
1427 }
1428
1429 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1430 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1431
1432 if (spectre_v2_in_ibrs_mode(mode)) {
1433 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1434 update_spec_ctrl(x86_spec_ctrl_base);
1435 }
1436
1437 switch (mode) {
1438 case SPECTRE_V2_NONE:
1439 case SPECTRE_V2_EIBRS:
1440 break;
1441
1442 case SPECTRE_V2_IBRS:
1443 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1444 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1445 pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1446 break;
1447
1448 case SPECTRE_V2_LFENCE:
1449 case SPECTRE_V2_EIBRS_LFENCE:
1450 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1451 fallthrough;
1452
1453 case SPECTRE_V2_RETPOLINE:
1454 case SPECTRE_V2_EIBRS_RETPOLINE:
1455 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1456 break;
1457 }
1458
1459 /*
1460 * Disable alternate RSB predictions in kernel when indirect CALLs and
1461 * JMPs gets protection against BHI and Intramode-BTI, but RET
1462 * prediction from a non-RSB predictor is still a risk.
1463 */
1464 if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1465 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1466 mode == SPECTRE_V2_RETPOLINE)
1467 spec_ctrl_disable_kernel_rrsba();
1468
1469 spectre_v2_enabled = mode;
1470 pr_info("%s\n", spectre_v2_strings[mode]);
1471
1472 /*
1473 * If Spectre v2 protection has been enabled, fill the RSB during a
1474 * context switch. In general there are two types of RSB attacks
1475 * across context switches, for which the CALLs/RETs may be unbalanced.
1476 *
1477 * 1) RSB underflow
1478 *
1479 * Some Intel parts have "bottomless RSB". When the RSB is empty,
1480 * speculated return targets may come from the branch predictor,
1481 * which could have a user-poisoned BTB or BHB entry.
1482 *
1483 * AMD has it even worse: *all* returns are speculated from the BTB,
1484 * regardless of the state of the RSB.
1485 *
1486 * When IBRS or eIBRS is enabled, the "user -> kernel" attack
1487 * scenario is mitigated by the IBRS branch prediction isolation
1488 * properties, so the RSB buffer filling wouldn't be necessary to
1489 * protect against this type of attack.
1490 *
1491 * The "user -> user" attack scenario is mitigated by RSB filling.
1492 *
1493 * 2) Poisoned RSB entry
1494 *
1495 * If the 'next' in-kernel return stack is shorter than 'prev',
1496 * 'next' could be tricked into speculating with a user-poisoned RSB
1497 * entry.
1498 *
1499 * The "user -> kernel" attack scenario is mitigated by SMEP and
1500 * eIBRS.
1501 *
1502 * The "user -> user" scenario, also known as SpectreBHB, requires
1503 * RSB clearing.
1504 *
1505 * So to mitigate all cases, unconditionally fill RSB on context
1506 * switches.
1507 *
1508 * FIXME: Is this pointless for retbleed-affected AMD?
1509 */
1510 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1511 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1512
1513 spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1514
1515 /*
1516 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1517 * and Enhanced IBRS protect firmware too, so enable IBRS around
1518 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1519 * enabled.
1520 *
1521 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1522 * the user might select retpoline on the kernel command line and if
1523 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1524 * enable IBRS around firmware calls.
1525 */
1526 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1527 boot_cpu_has(X86_FEATURE_IBPB) &&
1528 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1529 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1530
1531 if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1532 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1533 pr_info("Enabling Speculation Barrier for firmware calls\n");
1534 }
1535
1536 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1537 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1538 pr_info("Enabling Restricted Speculation for firmware calls\n");
1539 }
1540
1541 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1542 spectre_v2_cmd = cmd;
1543 }
1544
update_stibp_msr(void * __unused)1545 static void update_stibp_msr(void * __unused)
1546 {
1547 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1548 update_spec_ctrl(val);
1549 }
1550
1551 /* Update x86_spec_ctrl_base in case SMT state changed. */
update_stibp_strict(void)1552 static void update_stibp_strict(void)
1553 {
1554 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1555
1556 if (sched_smt_active())
1557 mask |= SPEC_CTRL_STIBP;
1558
1559 if (mask == x86_spec_ctrl_base)
1560 return;
1561
1562 pr_info("Update user space SMT mitigation: STIBP %s\n",
1563 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1564 x86_spec_ctrl_base = mask;
1565 on_each_cpu(update_stibp_msr, NULL, 1);
1566 }
1567
1568 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
update_indir_branch_cond(void)1569 static void update_indir_branch_cond(void)
1570 {
1571 if (sched_smt_active())
1572 static_branch_enable(&switch_to_cond_stibp);
1573 else
1574 static_branch_disable(&switch_to_cond_stibp);
1575 }
1576
1577 #undef pr_fmt
1578 #define pr_fmt(fmt) fmt
1579
1580 /* Update the static key controlling the MDS CPU buffer clear in idle */
update_mds_branch_idle(void)1581 static void update_mds_branch_idle(void)
1582 {
1583 u64 ia32_cap = x86_read_arch_cap_msr();
1584
1585 /*
1586 * Enable the idle clearing if SMT is active on CPUs which are
1587 * affected only by MSBDS and not any other MDS variant.
1588 *
1589 * The other variants cannot be mitigated when SMT is enabled, so
1590 * clearing the buffers on idle just to prevent the Store Buffer
1591 * repartitioning leak would be a window dressing exercise.
1592 */
1593 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1594 return;
1595
1596 if (sched_smt_active()) {
1597 static_branch_enable(&mds_idle_clear);
1598 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1599 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1600 static_branch_disable(&mds_idle_clear);
1601 }
1602 }
1603
1604 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1605 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1606 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1607
cpu_bugs_smt_update(void)1608 void cpu_bugs_smt_update(void)
1609 {
1610 mutex_lock(&spec_ctrl_mutex);
1611
1612 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1613 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1614 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1615
1616 switch (spectre_v2_user_stibp) {
1617 case SPECTRE_V2_USER_NONE:
1618 break;
1619 case SPECTRE_V2_USER_STRICT:
1620 case SPECTRE_V2_USER_STRICT_PREFERRED:
1621 update_stibp_strict();
1622 break;
1623 case SPECTRE_V2_USER_PRCTL:
1624 case SPECTRE_V2_USER_SECCOMP:
1625 update_indir_branch_cond();
1626 break;
1627 }
1628
1629 switch (mds_mitigation) {
1630 case MDS_MITIGATION_FULL:
1631 case MDS_MITIGATION_VMWERV:
1632 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1633 pr_warn_once(MDS_MSG_SMT);
1634 update_mds_branch_idle();
1635 break;
1636 case MDS_MITIGATION_OFF:
1637 break;
1638 }
1639
1640 switch (taa_mitigation) {
1641 case TAA_MITIGATION_VERW:
1642 case TAA_MITIGATION_UCODE_NEEDED:
1643 if (sched_smt_active())
1644 pr_warn_once(TAA_MSG_SMT);
1645 break;
1646 case TAA_MITIGATION_TSX_DISABLED:
1647 case TAA_MITIGATION_OFF:
1648 break;
1649 }
1650
1651 switch (mmio_mitigation) {
1652 case MMIO_MITIGATION_VERW:
1653 case MMIO_MITIGATION_UCODE_NEEDED:
1654 if (sched_smt_active())
1655 pr_warn_once(MMIO_MSG_SMT);
1656 break;
1657 case MMIO_MITIGATION_OFF:
1658 break;
1659 }
1660
1661 mutex_unlock(&spec_ctrl_mutex);
1662 }
1663
1664 #undef pr_fmt
1665 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1666
1667 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1668
1669 /* The kernel command line selection */
1670 enum ssb_mitigation_cmd {
1671 SPEC_STORE_BYPASS_CMD_NONE,
1672 SPEC_STORE_BYPASS_CMD_AUTO,
1673 SPEC_STORE_BYPASS_CMD_ON,
1674 SPEC_STORE_BYPASS_CMD_PRCTL,
1675 SPEC_STORE_BYPASS_CMD_SECCOMP,
1676 };
1677
1678 static const char * const ssb_strings[] = {
1679 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1680 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1681 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1682 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1683 };
1684
1685 static const struct {
1686 const char *option;
1687 enum ssb_mitigation_cmd cmd;
1688 } ssb_mitigation_options[] __initconst = {
1689 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1690 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1691 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1692 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1693 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1694 };
1695
ssb_parse_cmdline(void)1696 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1697 {
1698 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1699 char arg[20];
1700 int ret, i;
1701
1702 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1703 cpu_mitigations_off()) {
1704 return SPEC_STORE_BYPASS_CMD_NONE;
1705 } else {
1706 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1707 arg, sizeof(arg));
1708 if (ret < 0)
1709 return SPEC_STORE_BYPASS_CMD_AUTO;
1710
1711 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1712 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1713 continue;
1714
1715 cmd = ssb_mitigation_options[i].cmd;
1716 break;
1717 }
1718
1719 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1720 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1721 return SPEC_STORE_BYPASS_CMD_AUTO;
1722 }
1723 }
1724
1725 return cmd;
1726 }
1727
__ssb_select_mitigation(void)1728 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1729 {
1730 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1731 enum ssb_mitigation_cmd cmd;
1732
1733 if (!boot_cpu_has(X86_FEATURE_SSBD))
1734 return mode;
1735
1736 cmd = ssb_parse_cmdline();
1737 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1738 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1739 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1740 return mode;
1741
1742 switch (cmd) {
1743 case SPEC_STORE_BYPASS_CMD_AUTO:
1744 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1745 /*
1746 * Choose prctl+seccomp as the default mode if seccomp is
1747 * enabled.
1748 */
1749 if (IS_ENABLED(CONFIG_SECCOMP))
1750 mode = SPEC_STORE_BYPASS_SECCOMP;
1751 else
1752 mode = SPEC_STORE_BYPASS_PRCTL;
1753 break;
1754 case SPEC_STORE_BYPASS_CMD_ON:
1755 mode = SPEC_STORE_BYPASS_DISABLE;
1756 break;
1757 case SPEC_STORE_BYPASS_CMD_PRCTL:
1758 mode = SPEC_STORE_BYPASS_PRCTL;
1759 break;
1760 case SPEC_STORE_BYPASS_CMD_NONE:
1761 break;
1762 }
1763
1764 /*
1765 * We have three CPU feature flags that are in play here:
1766 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1767 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1768 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1769 */
1770 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1771 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1772 /*
1773 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1774 * use a completely different MSR and bit dependent on family.
1775 */
1776 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1777 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1778 x86_amd_ssb_disable();
1779 } else {
1780 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1781 update_spec_ctrl(x86_spec_ctrl_base);
1782 }
1783 }
1784
1785 return mode;
1786 }
1787
ssb_select_mitigation(void)1788 static void ssb_select_mitigation(void)
1789 {
1790 ssb_mode = __ssb_select_mitigation();
1791
1792 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1793 pr_info("%s\n", ssb_strings[ssb_mode]);
1794 }
1795
1796 #undef pr_fmt
1797 #define pr_fmt(fmt) "Speculation prctl: " fmt
1798
task_update_spec_tif(struct task_struct * tsk)1799 static void task_update_spec_tif(struct task_struct *tsk)
1800 {
1801 /* Force the update of the real TIF bits */
1802 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1803
1804 /*
1805 * Immediately update the speculation control MSRs for the current
1806 * task, but for a non-current task delay setting the CPU
1807 * mitigation until it is scheduled next.
1808 *
1809 * This can only happen for SECCOMP mitigation. For PRCTL it's
1810 * always the current task.
1811 */
1812 if (tsk == current)
1813 speculation_ctrl_update_current();
1814 }
1815
ssb_prctl_set(struct task_struct * task,unsigned long ctrl)1816 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1817 {
1818 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1819 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1820 return -ENXIO;
1821
1822 switch (ctrl) {
1823 case PR_SPEC_ENABLE:
1824 /* If speculation is force disabled, enable is not allowed */
1825 if (task_spec_ssb_force_disable(task))
1826 return -EPERM;
1827 task_clear_spec_ssb_disable(task);
1828 task_clear_spec_ssb_noexec(task);
1829 task_update_spec_tif(task);
1830 break;
1831 case PR_SPEC_DISABLE:
1832 task_set_spec_ssb_disable(task);
1833 task_clear_spec_ssb_noexec(task);
1834 task_update_spec_tif(task);
1835 break;
1836 case PR_SPEC_FORCE_DISABLE:
1837 task_set_spec_ssb_disable(task);
1838 task_set_spec_ssb_force_disable(task);
1839 task_clear_spec_ssb_noexec(task);
1840 task_update_spec_tif(task);
1841 break;
1842 case PR_SPEC_DISABLE_NOEXEC:
1843 if (task_spec_ssb_force_disable(task))
1844 return -EPERM;
1845 task_set_spec_ssb_disable(task);
1846 task_set_spec_ssb_noexec(task);
1847 task_update_spec_tif(task);
1848 break;
1849 default:
1850 return -ERANGE;
1851 }
1852 return 0;
1853 }
1854
is_spec_ib_user_controlled(void)1855 static bool is_spec_ib_user_controlled(void)
1856 {
1857 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1858 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1859 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1860 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1861 }
1862
ib_prctl_set(struct task_struct * task,unsigned long ctrl)1863 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1864 {
1865 switch (ctrl) {
1866 case PR_SPEC_ENABLE:
1867 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1868 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1869 return 0;
1870
1871 /*
1872 * With strict mode for both IBPB and STIBP, the instruction
1873 * code paths avoid checking this task flag and instead,
1874 * unconditionally run the instruction. However, STIBP and IBPB
1875 * are independent and either can be set to conditionally
1876 * enabled regardless of the mode of the other.
1877 *
1878 * If either is set to conditional, allow the task flag to be
1879 * updated, unless it was force-disabled by a previous prctl
1880 * call. Currently, this is possible on an AMD CPU which has the
1881 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
1882 * kernel is booted with 'spectre_v2_user=seccomp', then
1883 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
1884 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
1885 */
1886 if (!is_spec_ib_user_controlled() ||
1887 task_spec_ib_force_disable(task))
1888 return -EPERM;
1889
1890 task_clear_spec_ib_disable(task);
1891 task_update_spec_tif(task);
1892 break;
1893 case PR_SPEC_DISABLE:
1894 case PR_SPEC_FORCE_DISABLE:
1895 /*
1896 * Indirect branch speculation is always allowed when
1897 * mitigation is force disabled.
1898 */
1899 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1900 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1901 return -EPERM;
1902
1903 if (!is_spec_ib_user_controlled())
1904 return 0;
1905
1906 task_set_spec_ib_disable(task);
1907 if (ctrl == PR_SPEC_FORCE_DISABLE)
1908 task_set_spec_ib_force_disable(task);
1909 task_update_spec_tif(task);
1910 if (task == current)
1911 indirect_branch_prediction_barrier();
1912 break;
1913 default:
1914 return -ERANGE;
1915 }
1916 return 0;
1917 }
1918
arch_prctl_spec_ctrl_set(struct task_struct * task,unsigned long which,unsigned long ctrl)1919 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
1920 unsigned long ctrl)
1921 {
1922 switch (which) {
1923 case PR_SPEC_STORE_BYPASS:
1924 return ssb_prctl_set(task, ctrl);
1925 case PR_SPEC_INDIRECT_BRANCH:
1926 return ib_prctl_set(task, ctrl);
1927 default:
1928 return -ENODEV;
1929 }
1930 }
1931
1932 #ifdef CONFIG_SECCOMP
arch_seccomp_spec_mitigate(struct task_struct * task)1933 void arch_seccomp_spec_mitigate(struct task_struct *task)
1934 {
1935 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
1936 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1937 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1938 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
1939 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
1940 }
1941 #endif
1942
ssb_prctl_get(struct task_struct * task)1943 static int ssb_prctl_get(struct task_struct *task)
1944 {
1945 switch (ssb_mode) {
1946 case SPEC_STORE_BYPASS_DISABLE:
1947 return PR_SPEC_DISABLE;
1948 case SPEC_STORE_BYPASS_SECCOMP:
1949 case SPEC_STORE_BYPASS_PRCTL:
1950 if (task_spec_ssb_force_disable(task))
1951 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1952 if (task_spec_ssb_noexec(task))
1953 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
1954 if (task_spec_ssb_disable(task))
1955 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1956 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1957 default:
1958 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1959 return PR_SPEC_ENABLE;
1960 return PR_SPEC_NOT_AFFECTED;
1961 }
1962 }
1963
ib_prctl_get(struct task_struct * task)1964 static int ib_prctl_get(struct task_struct *task)
1965 {
1966 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
1967 return PR_SPEC_NOT_AFFECTED;
1968
1969 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1970 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1971 return PR_SPEC_ENABLE;
1972 else if (is_spec_ib_user_controlled()) {
1973 if (task_spec_ib_force_disable(task))
1974 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
1975 if (task_spec_ib_disable(task))
1976 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
1977 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
1978 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
1979 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
1980 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
1981 return PR_SPEC_DISABLE;
1982 else
1983 return PR_SPEC_NOT_AFFECTED;
1984 }
1985
arch_prctl_spec_ctrl_get(struct task_struct * task,unsigned long which)1986 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1987 {
1988 switch (which) {
1989 case PR_SPEC_STORE_BYPASS:
1990 return ssb_prctl_get(task);
1991 case PR_SPEC_INDIRECT_BRANCH:
1992 return ib_prctl_get(task);
1993 default:
1994 return -ENODEV;
1995 }
1996 }
1997
x86_spec_ctrl_setup_ap(void)1998 void x86_spec_ctrl_setup_ap(void)
1999 {
2000 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2001 update_spec_ctrl(x86_spec_ctrl_base);
2002
2003 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2004 x86_amd_ssb_disable();
2005 }
2006
2007 bool itlb_multihit_kvm_mitigation;
2008 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2009
2010 #undef pr_fmt
2011 #define pr_fmt(fmt) "L1TF: " fmt
2012
2013 /* Default mitigation for L1TF-affected CPUs */
2014 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2015 #if IS_ENABLED(CONFIG_KVM_INTEL)
2016 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2017 #endif
2018 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2019 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2020
2021 /*
2022 * These CPUs all support 44bits physical address space internally in the
2023 * cache but CPUID can report a smaller number of physical address bits.
2024 *
2025 * The L1TF mitigation uses the top most address bit for the inversion of
2026 * non present PTEs. When the installed memory reaches into the top most
2027 * address bit due to memory holes, which has been observed on machines
2028 * which report 36bits physical address bits and have 32G RAM installed,
2029 * then the mitigation range check in l1tf_select_mitigation() triggers.
2030 * This is a false positive because the mitigation is still possible due to
2031 * the fact that the cache uses 44bit internally. Use the cache bits
2032 * instead of the reported physical bits and adjust them on the affected
2033 * machines to 44bit if the reported bits are less than 44.
2034 */
override_cache_bits(struct cpuinfo_x86 * c)2035 static void override_cache_bits(struct cpuinfo_x86 *c)
2036 {
2037 if (c->x86 != 6)
2038 return;
2039
2040 switch (c->x86_model) {
2041 case INTEL_FAM6_NEHALEM:
2042 case INTEL_FAM6_WESTMERE:
2043 case INTEL_FAM6_SANDYBRIDGE:
2044 case INTEL_FAM6_IVYBRIDGE:
2045 case INTEL_FAM6_HASWELL:
2046 case INTEL_FAM6_HASWELL_L:
2047 case INTEL_FAM6_HASWELL_G:
2048 case INTEL_FAM6_BROADWELL:
2049 case INTEL_FAM6_BROADWELL_G:
2050 case INTEL_FAM6_SKYLAKE_L:
2051 case INTEL_FAM6_SKYLAKE:
2052 case INTEL_FAM6_KABYLAKE_L:
2053 case INTEL_FAM6_KABYLAKE:
2054 if (c->x86_cache_bits < 44)
2055 c->x86_cache_bits = 44;
2056 break;
2057 }
2058 }
2059
l1tf_select_mitigation(void)2060 static void __init l1tf_select_mitigation(void)
2061 {
2062 u64 half_pa;
2063
2064 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2065 return;
2066
2067 if (cpu_mitigations_off())
2068 l1tf_mitigation = L1TF_MITIGATION_OFF;
2069 else if (cpu_mitigations_auto_nosmt())
2070 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2071
2072 override_cache_bits(&boot_cpu_data);
2073
2074 switch (l1tf_mitigation) {
2075 case L1TF_MITIGATION_OFF:
2076 case L1TF_MITIGATION_FLUSH_NOWARN:
2077 case L1TF_MITIGATION_FLUSH:
2078 break;
2079 case L1TF_MITIGATION_FLUSH_NOSMT:
2080 case L1TF_MITIGATION_FULL:
2081 cpu_smt_disable(false);
2082 break;
2083 case L1TF_MITIGATION_FULL_FORCE:
2084 cpu_smt_disable(true);
2085 break;
2086 }
2087
2088 #if CONFIG_PGTABLE_LEVELS == 2
2089 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2090 return;
2091 #endif
2092
2093 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2094 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2095 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2096 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2097 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2098 half_pa);
2099 pr_info("However, doing so will make a part of your RAM unusable.\n");
2100 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2101 return;
2102 }
2103
2104 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2105 }
2106
l1tf_cmdline(char * str)2107 static int __init l1tf_cmdline(char *str)
2108 {
2109 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2110 return 0;
2111
2112 if (!str)
2113 return -EINVAL;
2114
2115 if (!strcmp(str, "off"))
2116 l1tf_mitigation = L1TF_MITIGATION_OFF;
2117 else if (!strcmp(str, "flush,nowarn"))
2118 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2119 else if (!strcmp(str, "flush"))
2120 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2121 else if (!strcmp(str, "flush,nosmt"))
2122 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2123 else if (!strcmp(str, "full"))
2124 l1tf_mitigation = L1TF_MITIGATION_FULL;
2125 else if (!strcmp(str, "full,force"))
2126 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2127
2128 return 0;
2129 }
2130 early_param("l1tf", l1tf_cmdline);
2131
2132 #undef pr_fmt
2133 #define pr_fmt(fmt) fmt
2134
2135 #ifdef CONFIG_SYSFS
2136
2137 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2138
2139 #if IS_ENABLED(CONFIG_KVM_INTEL)
2140 static const char * const l1tf_vmx_states[] = {
2141 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2142 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2143 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2144 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2145 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2146 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2147 };
2148
l1tf_show_state(char * buf)2149 static ssize_t l1tf_show_state(char *buf)
2150 {
2151 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2152 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2153
2154 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2155 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2156 sched_smt_active())) {
2157 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2158 l1tf_vmx_states[l1tf_vmx_mitigation]);
2159 }
2160
2161 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2162 l1tf_vmx_states[l1tf_vmx_mitigation],
2163 sched_smt_active() ? "vulnerable" : "disabled");
2164 }
2165
itlb_multihit_show_state(char * buf)2166 static ssize_t itlb_multihit_show_state(char *buf)
2167 {
2168 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2169 !boot_cpu_has(X86_FEATURE_VMX))
2170 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2171 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2172 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2173 else if (itlb_multihit_kvm_mitigation)
2174 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2175 else
2176 return sprintf(buf, "KVM: Vulnerable\n");
2177 }
2178 #else
l1tf_show_state(char * buf)2179 static ssize_t l1tf_show_state(char *buf)
2180 {
2181 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2182 }
2183
itlb_multihit_show_state(char * buf)2184 static ssize_t itlb_multihit_show_state(char *buf)
2185 {
2186 return sprintf(buf, "Processor vulnerable\n");
2187 }
2188 #endif
2189
mds_show_state(char * buf)2190 static ssize_t mds_show_state(char *buf)
2191 {
2192 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2193 return sprintf(buf, "%s; SMT Host state unknown\n",
2194 mds_strings[mds_mitigation]);
2195 }
2196
2197 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2198 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2199 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2200 sched_smt_active() ? "mitigated" : "disabled"));
2201 }
2202
2203 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2204 sched_smt_active() ? "vulnerable" : "disabled");
2205 }
2206
tsx_async_abort_show_state(char * buf)2207 static ssize_t tsx_async_abort_show_state(char *buf)
2208 {
2209 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2210 (taa_mitigation == TAA_MITIGATION_OFF))
2211 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2212
2213 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2214 return sprintf(buf, "%s; SMT Host state unknown\n",
2215 taa_strings[taa_mitigation]);
2216 }
2217
2218 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2219 sched_smt_active() ? "vulnerable" : "disabled");
2220 }
2221
mmio_stale_data_show_state(char * buf)2222 static ssize_t mmio_stale_data_show_state(char *buf)
2223 {
2224 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2225 return sysfs_emit(buf, "Unknown: No mitigations\n");
2226
2227 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2228 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2229
2230 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2231 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2232 mmio_strings[mmio_mitigation]);
2233 }
2234
2235 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2236 sched_smt_active() ? "vulnerable" : "disabled");
2237 }
2238
stibp_state(void)2239 static char *stibp_state(void)
2240 {
2241 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
2242 return "";
2243
2244 switch (spectre_v2_user_stibp) {
2245 case SPECTRE_V2_USER_NONE:
2246 return ", STIBP: disabled";
2247 case SPECTRE_V2_USER_STRICT:
2248 return ", STIBP: forced";
2249 case SPECTRE_V2_USER_STRICT_PREFERRED:
2250 return ", STIBP: always-on";
2251 case SPECTRE_V2_USER_PRCTL:
2252 case SPECTRE_V2_USER_SECCOMP:
2253 if (static_key_enabled(&switch_to_cond_stibp))
2254 return ", STIBP: conditional";
2255 }
2256 return "";
2257 }
2258
ibpb_state(void)2259 static char *ibpb_state(void)
2260 {
2261 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2262 if (static_key_enabled(&switch_mm_always_ibpb))
2263 return ", IBPB: always-on";
2264 if (static_key_enabled(&switch_mm_cond_ibpb))
2265 return ", IBPB: conditional";
2266 return ", IBPB: disabled";
2267 }
2268 return "";
2269 }
2270
pbrsb_eibrs_state(void)2271 static char *pbrsb_eibrs_state(void)
2272 {
2273 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2274 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2275 boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2276 return ", PBRSB-eIBRS: SW sequence";
2277 else
2278 return ", PBRSB-eIBRS: Vulnerable";
2279 } else {
2280 return ", PBRSB-eIBRS: Not affected";
2281 }
2282 }
2283
spectre_v2_show_state(char * buf)2284 static ssize_t spectre_v2_show_state(char *buf)
2285 {
2286 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2287 return sprintf(buf, "Vulnerable: LFENCE\n");
2288
2289 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2290 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2291
2292 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2293 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2294 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2295
2296 return sprintf(buf, "%s%s%s%s%s%s%s\n",
2297 spectre_v2_strings[spectre_v2_enabled],
2298 ibpb_state(),
2299 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2300 stibp_state(),
2301 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2302 pbrsb_eibrs_state(),
2303 spectre_v2_module_string());
2304 }
2305
srbds_show_state(char * buf)2306 static ssize_t srbds_show_state(char *buf)
2307 {
2308 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2309 }
2310
retbleed_show_state(char * buf)2311 static ssize_t retbleed_show_state(char *buf)
2312 {
2313 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
2314 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2315 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2316 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2317 return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
2318
2319 return sprintf(buf, "%s; SMT %s\n",
2320 retbleed_strings[retbleed_mitigation],
2321 !sched_smt_active() ? "disabled" :
2322 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2323 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2324 "enabled with STIBP protection" : "vulnerable");
2325 }
2326
2327 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2328 }
2329
cpu_show_common(struct device * dev,struct device_attribute * attr,char * buf,unsigned int bug)2330 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2331 char *buf, unsigned int bug)
2332 {
2333 if (!boot_cpu_has_bug(bug))
2334 return sprintf(buf, "Not affected\n");
2335
2336 switch (bug) {
2337 case X86_BUG_CPU_MELTDOWN:
2338 if (boot_cpu_has(X86_FEATURE_PTI))
2339 return sprintf(buf, "Mitigation: PTI\n");
2340
2341 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2342 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2343
2344 break;
2345
2346 case X86_BUG_SPECTRE_V1:
2347 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2348
2349 case X86_BUG_SPECTRE_V2:
2350 return spectre_v2_show_state(buf);
2351
2352 case X86_BUG_SPEC_STORE_BYPASS:
2353 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2354
2355 case X86_BUG_L1TF:
2356 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2357 return l1tf_show_state(buf);
2358 break;
2359
2360 case X86_BUG_MDS:
2361 return mds_show_state(buf);
2362
2363 case X86_BUG_TAA:
2364 return tsx_async_abort_show_state(buf);
2365
2366 case X86_BUG_ITLB_MULTIHIT:
2367 return itlb_multihit_show_state(buf);
2368
2369 case X86_BUG_SRBDS:
2370 return srbds_show_state(buf);
2371
2372 case X86_BUG_MMIO_STALE_DATA:
2373 case X86_BUG_MMIO_UNKNOWN:
2374 return mmio_stale_data_show_state(buf);
2375
2376 case X86_BUG_RETBLEED:
2377 return retbleed_show_state(buf);
2378
2379 default:
2380 break;
2381 }
2382
2383 return sprintf(buf, "Vulnerable\n");
2384 }
2385
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2386 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2387 {
2388 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2389 }
2390
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)2391 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2392 {
2393 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2394 }
2395
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)2396 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2397 {
2398 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2399 }
2400
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)2401 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2402 {
2403 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2404 }
2405
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)2406 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2407 {
2408 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2409 }
2410
cpu_show_mds(struct device * dev,struct device_attribute * attr,char * buf)2411 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2412 {
2413 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2414 }
2415
cpu_show_tsx_async_abort(struct device * dev,struct device_attribute * attr,char * buf)2416 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2417 {
2418 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2419 }
2420
cpu_show_itlb_multihit(struct device * dev,struct device_attribute * attr,char * buf)2421 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2422 {
2423 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2424 }
2425
cpu_show_srbds(struct device * dev,struct device_attribute * attr,char * buf)2426 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2427 {
2428 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2429 }
2430
cpu_show_mmio_stale_data(struct device * dev,struct device_attribute * attr,char * buf)2431 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2432 {
2433 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2434 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2435 else
2436 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2437 }
2438
cpu_show_retbleed(struct device * dev,struct device_attribute * attr,char * buf)2439 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2440 {
2441 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2442 }
2443 #endif
2444