1 /*******************************************************************************
2 // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
3 //
4 // Permission is hereby granted, free of charge, to any person obtaining
5 // a copy of this software and associated documentation files (the
6 // "Software"), to deal in the Software without restriction, including
7 // without limitation the rights to use, copy, modify, merge, publish,
8 // distribute, sublicense, and/or sell copies of the Software, and to
9 // permit persons to whom the Software is furnished to do so, subject to
10 // the following conditions:
11 //
12 // The above copyright notice and this permission notice shall be included
13 // in all copies or substantial portions of the Software.
14 //
15 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18 // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19 // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20 // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21 // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 --------------------------------------------------------------------------------
23 */
24 #include <stdlib.h>
25 #include <string.h>
26 #include <xtensa/config/core.h>
27
28 #include "xtensa_rtos.h"
29
30 #include "soc/cpu.h"
31
32 #include "esp_osal.h"
33 #include "task.h"
34
35 #include "esp_debug_helpers.h"
36 #include "esp_heap_caps.h"
37 #include "esp_heap_caps_init.h"
38 #include "esp_private/crosscore_int.h"
39
40 #include "esp_intr_alloc.h"
41 #include "esp_log.h"
42 #include "sdkconfig.h"
43
44 #include "esp_task_wdt.h"
45 #include "esp_task.h"
46
47 #include "soc/soc_caps.h"
48 #include "soc/efuse_reg.h"
49 #include "soc/dport_access.h"
50 #include "soc/dport_reg.h"
51 #include "esp_int_wdt.h"
52
53
54 #include "sdkconfig.h"
55
56 #if CONFIG_IDF_TARGET_ESP32
57 #include "esp32/spiram.h"
58 #elif CONFIG_IDF_TARGET_ESP32S2
59 #include "esp32s2/spiram.h"
60 #elif CONFIG_IDF_TARGET_ESP32S3
61 #include "esp32s3/spiram.h"
62 #endif
63
64 #include "esp_private/startup_internal.h" // [refactor-todo] for g_spiram_ok
65
66 /* Defined in portasm.h */
67 extern void _frxt_tick_timer_init(void);
68
69 /* Defined in xtensa_context.S */
70 extern void _xt_coproc_init(void);
71
72 static const char* TAG = "cpu_start"; // [refactor-todo]: might be appropriate to change in the future, but
73 // for now maintain the same log output
74
75 #if CONFIG_FREERTOS_CORETIMER_0
76 #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
77 #endif
78 #if CONFIG_FREERTOS_CORETIMER_1
79 #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
80 #endif
81
82 _Static_assert(tskNO_AFFINITY == CONFIG_FREERTOS_NO_AFFINITY, "incorrect tskNO_AFFINITY value");
83
84 /*-----------------------------------------------------------*/
85 extern volatile int port_xSchedulerRunning[portNUM_PROCESSORS];
86 unsigned port_interruptNesting[portNUM_PROCESSORS] = {0}; // Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit
87 BaseType_t port_uxCriticalNesting[portNUM_PROCESSORS] = {0};
88 BaseType_t port_uxOldInterruptState[portNUM_PROCESSORS] = {0};
89 /*-----------------------------------------------------------*/
90
91 // User exception dispatcher when exiting
92 void _xt_user_exit(void);
93
94 #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
95 // Wrapper to allow task functions to return (increases stack overhead by 16 bytes)
vPortTaskWrapper(TaskFunction_t pxCode,void * pvParameters)96 static void vPortTaskWrapper(TaskFunction_t pxCode, void *pvParameters)
97 {
98 pxCode(pvParameters);
99 //FreeRTOS tasks should not return. Log the task name and abort.
100 char * pcTaskName = pcTaskGetTaskName(NULL);
101 ESP_LOGE("FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName);
102 abort();
103 }
104 #endif
105
106 /*
107 * Stack initialization
108 */
109 #if portUSING_MPU_WRAPPERS
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters,BaseType_t xRunPrivileged)110 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
111 #else
112 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
113 #endif
114 {
115 StackType_t *sp, *tp;
116 XtExcFrame *frame;
117 #if XCHAL_CP_NUM > 0
118 uint32_t *p;
119 #endif
120 uint32_t *threadptr;
121 void *task_thread_local_start;
122 extern int _thread_local_start, _thread_local_end, _flash_rodata_start, _flash_rodata_align;
123 // TODO: check that TLS area fits the stack
124 uint32_t thread_local_sz = (uint8_t *)&_thread_local_end - (uint8_t *)&_thread_local_start;
125
126 thread_local_sz = ALIGNUP(0x10, thread_local_sz);
127
128 /* Initialize task's stack so that we have the following structure at the top:
129
130 ----LOW ADDRESSES ----------------------------------------HIGH ADDRESSES----------
131 task stack | interrupt stack frame | thread local vars | co-processor save area |
132 ----------------------------------------------------------------------------------
133 | |
134 SP pxTopOfStack
135
136 All parts are aligned to 16 byte boundary. */
137 sp = (StackType_t *) (((UBaseType_t)(pxTopOfStack + 1) - XT_CP_SIZE - thread_local_sz - XT_STK_FRMSZ) & ~0xf);
138
139 /* Clear the entire frame (do not use memset() because we don't depend on C library) */
140 for (tp = sp; tp <= pxTopOfStack; ++tp)
141 *tp = 0;
142
143 frame = (XtExcFrame *) sp;
144
145 /* Explicitly initialize certain saved registers */
146 #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
147 frame->pc = (UBaseType_t) vPortTaskWrapper; /* task wrapper */
148 #else
149 frame->pc = (UBaseType_t) pxCode; /* task entrypoint */
150 #endif
151 frame->a0 = 0; /* to terminate GDB backtrace */
152 frame->a1 = (UBaseType_t) sp + XT_STK_FRMSZ; /* physical top of stack frame */
153 frame->exit = (UBaseType_t) _xt_user_exit; /* user exception exit dispatcher */
154
155 /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
156 /* Also set entry point argument parameter. */
157 #ifdef __XTENSA_CALL0_ABI__
158 #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
159 frame->a2 = (UBaseType_t) pxCode;
160 frame->a3 = (UBaseType_t) pvParameters;
161 #else
162 frame->a2 = (UBaseType_t) pvParameters;
163 #endif
164 frame->ps = PS_UM | PS_EXCM;
165 #else
166 /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
167 #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
168 frame->a6 = (UBaseType_t) pxCode;
169 frame->a7 = (UBaseType_t) pvParameters;
170 #else
171 frame->a6 = (UBaseType_t) pvParameters;
172 #endif
173 frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
174 #endif
175
176 #ifdef XT_USE_SWPRI
177 /* Set the initial virtual priority mask value to all 1's. */
178 frame->vpri = 0xFFFFFFFF;
179 #endif
180
181 /* Init threadptr register and set up TLS run-time area.
182 * The diagram in port/riscv/port.c illustrates the calculations below.
183 */
184 task_thread_local_start = (void *)(((uint32_t)pxTopOfStack - XT_CP_SIZE - thread_local_sz) & ~0xf);
185 memcpy(task_thread_local_start, &_thread_local_start, thread_local_sz);
186 threadptr = (uint32_t *)(sp + XT_STK_EXTRA);
187 /* Calculate THREADPTR value.
188 * The generated code will add THREADPTR value to a constant value determined at link time,
189 * to get the address of the TLS variable.
190 * The constant value is calculated by the linker as follows
191 * (search for 'tpoff' in elf32-xtensa.c in BFD):
192 * offset = address - tls_section_vma + align_up(TCB_SIZE, tls_section_alignment)
193 * where TCB_SIZE is hardcoded to 8.
194 * Note this is slightly different compared to the RISC-V port, where offset = address - tls_section_vma.
195 */
196 const uint32_t tls_section_alignment = (uint32_t) &_flash_rodata_align; /* ALIGN value of .flash.rodata section */
197 const uint32_t tcb_size = 8; /* Unrelated to FreeRTOS, this is the constant from BFD */
198 const uint32_t base = (tcb_size + tls_section_alignment - 1) & (~(tls_section_alignment - 1));
199 *threadptr = (uint32_t)task_thread_local_start - ((uint32_t)&_thread_local_start - (uint32_t)&_flash_rodata_start) - base;
200
201 #if XCHAL_CP_NUM > 0
202 /* Init the coprocessor save area (see xtensa_context.h) */
203 /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
204 * //p = (uint32_t *) xMPUSettings->coproc_area;
205 */
206 p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf);
207 p[0] = 0;
208 p[1] = 0;
209 p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;
210 #endif
211
212 return sp;
213 }
214
215 /*-----------------------------------------------------------*/
216
vPortEndScheduler(void)217 void vPortEndScheduler( void )
218 {
219 /* It is unlikely that the Xtensa port will get stopped. If required simply
220 disable the tick interrupt here. */
221 abort();
222 }
223
224 /*-----------------------------------------------------------*/
225
xPortStartScheduler(void)226 BaseType_t xPortStartScheduler( void )
227 {
228 // Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
229
230 #if XCHAL_CP_NUM > 0
231 /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
232 _xt_coproc_init();
233 #endif
234
235 /* Init the tick divisor value */
236 _xt_tick_divisor_init();
237
238 /* Setup the hardware to generate the tick. */
239 _frxt_tick_timer_init();
240
241 // port_xSchedulerRunning[xPortGetCoreID()] = 1;
242
243 // Cannot be directly called from C; never returns
244 __asm__ volatile ("call0 _frxt_dispatch\n");
245
246 /* Should not get here. */
247 return pdTRUE;
248 }
249 /*-----------------------------------------------------------*/
vPortYieldOtherCore(BaseType_t coreid)250 void vPortYieldOtherCore( BaseType_t coreid ) {
251 esp_crosscore_int_send_yield( coreid );
252 }
253
254 /*-----------------------------------------------------------*/
255
256 /*
257 * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
258 */
259 #if portUSING_MPU_WRAPPERS
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,uint32_t usStackDepth)260 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth )
261 {
262 #if XCHAL_CP_NUM > 0
263 xMPUSettings->coproc_area = (StackType_t*)((((uint32_t)(pxBottomOfStack + usStackDepth - 1)) - XT_CP_SIZE ) & ~0xf);
264
265
266 /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
267 * clear the stack area after we return. This is done in pxPortInitialiseStack().
268 */
269 #endif
270 }
271
vPortReleaseTaskMPUSettings(xMPU_SETTINGS * xMPUSettings)272 void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings )
273 {
274 /* If task has live floating point registers somewhere, release them */
275 _xt_coproc_release( xMPUSettings->coproc_area );
276 }
277 #else
vPortStoreTaskMPUSettings(xMPU_SETTINGS * xMPUSettings,const struct xMEMORY_REGION * const xRegions,StackType_t * pxBottomOfStack,uint32_t usStackDepth)278 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth ) {;}
vPortReleaseTaskMPUSettings(xMPU_SETTINGS * xMPUSettings)279 void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings ){;}
280 #endif
281
282 /*
283 * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
284 * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
285 */
xPortInIsrContext(void)286 BaseType_t xPortInIsrContext(void)
287 {
288 unsigned int irqStatus;
289 BaseType_t ret;
290 irqStatus=portENTER_CRITICAL_NESTED();
291 ret=(port_interruptNesting[xPortGetCoreID()] != 0);
292 portEXIT_CRITICAL_NESTED(irqStatus);
293 return ret;
294 }
295
296 /*
297 * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
298 * before calling into high prio ISR context.
299 */
xPortInterruptedFromISRContext(void)300 BaseType_t IRAM_ATTR xPortInterruptedFromISRContext(void)
301 {
302 return (port_interruptNesting[xPortGetCoreID()] != 0);
303 }
304
vPortEvaluateYieldFromISR(int argc,...)305 void IRAM_ATTR vPortEvaluateYieldFromISR(int argc, ...)
306 {
307 BaseType_t xYield;
308 va_list ap;
309 va_start(ap, argc);
310
311 if(argc) {
312 xYield = (BaseType_t)va_arg(ap, int);
313 va_end(ap);
314 } else {
315 //it is a empty parameter vPortYieldFromISR macro call:
316 va_end(ap);
317 traceISR_EXIT_TO_SCHEDULER();
318 _frxt_setup_switch();
319 return;
320 }
321
322 //Yield exists, so need evaluate it first then switch:
323 if(xYield == pdTRUE) {
324 traceISR_EXIT_TO_SCHEDULER();
325 _frxt_setup_switch();
326 }
327 }
328
vPortAssertIfInISR(void)329 void vPortAssertIfInISR(void)
330 {
331 configASSERT(xPortInIsrContext());
332 }
333
334 #define STACK_WATCH_AREA_SIZE 32
335 #define STACK_WATCH_POINT_NUMBER (SOC_CPU_WATCHPOINTS_NUM - 1)
336
vPortSetStackWatchpoint(void * pxStackStart)337 void vPortSetStackWatchpoint( void* pxStackStart ) {
338 //Set watchpoint 1 to watch the last 32 bytes of the stack.
339 //Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because
340 //the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32
341 //bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most
342 //28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes.
343 //This way, we make sure we trigger before/when the stack canary is corrupted, not after.
344 int addr=(int)pxStackStart;
345 addr=(addr+31)&(~31);
346 esp_set_watchpoint(STACK_WATCH_POINT_NUMBER, (char*)addr, 32, ESP_WATCHPOINT_STORE);
347 }
348
xPortGetTickRateHz(void)349 uint32_t xPortGetTickRateHz(void) {
350 return (uint32_t)configTICK_RATE_HZ;
351 }
352
vPortEnterCritical(portMUX_TYPE * mux)353 void __attribute__((optimize("-O3"))) vPortEnterCritical(portMUX_TYPE *mux)
354 {
355 BaseType_t oldInterruptLevel = portENTER_CRITICAL_NESTED();
356 /* Interrupts may already be disabled (because we're doing this recursively)
357 * but we can't get the interrupt level after
358 * vPortCPUAquireMutex, because it also may mess with interrupts.
359 * Get it here first, then later figure out if we're nesting
360 * and save for real there.
361 */
362 vPortCPUAcquireMutex( mux );
363 BaseType_t coreID = 0;// xPortGetCoreID();
364 BaseType_t newNesting = port_uxCriticalNesting[coreID] + 1;
365 port_uxCriticalNesting[coreID] = newNesting;
366
367 if( newNesting == 1 )
368 {
369 //This is the first time we get called. Save original interrupt level.
370 port_uxOldInterruptState[coreID] = oldInterruptLevel;
371 }
372 }
373
vPortExitCritical(portMUX_TYPE * mux)374 void __attribute__((optimize("-O3"))) vPortExitCritical(portMUX_TYPE *mux)
375 {
376 vPortCPUReleaseMutex( mux );
377 BaseType_t coreID = 0;// xPortGetCoreID();
378 BaseType_t nesting = port_uxCriticalNesting[coreID];
379
380 if(nesting > 0)
381 {
382 nesting--;
383 port_uxCriticalNesting[coreID] = nesting;
384
385 if( nesting == 0 )
386 {
387 portEXIT_CRITICAL_NESTED(port_uxOldInterruptState[coreID]);
388 }
389 }
390 }
391
vApplicationStackOverflowHook(TaskHandle_t xTask,char * pcTaskName)392 void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName )
393 {
394 #define ERR_STR1 "***ERROR*** A stack overflow in task "
395 #define ERR_STR2 " has been detected."
396 const char *str[] = {ERR_STR1, pcTaskName, ERR_STR2};
397
398 char buf[sizeof(ERR_STR1) + CONFIG_FREERTOS_MAX_TASK_NAME_LEN + sizeof(ERR_STR2) + 1 /* null char */] = { 0 };
399
400 char *dest = buf;
401 for (size_t i = 0 ; i < sizeof(str)/ sizeof(str[0]); i++) {
402 dest = strcat(dest, str[i]);
403 }
404 esp_system_abort(buf);
405 }
406
407 #if !CONFIG_FREERTOS_UNICORE
esp_startup_start_app_other_cores(void)408 void esp_startup_start_app_other_cores(void)
409 {
410 // For now, we only support up to two core: 0 and 1.
411 if (xPortGetCoreID() >= 2) {
412 abort();
413 }
414
415 // Wait for FreeRTOS initialization to finish on PRO CPU
416 while (port_xSchedulerRunning[0] == 0) {
417 ;
418 }
419
420 #if CONFIG_APPTRACE_ENABLE
421 // [refactor-todo] move to esp_system initialization
422 esp_err_t err = esp_apptrace_init();
423 assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
424 #endif
425
426 #if CONFIG_ESP_INT_WDT
427 //Initialize the interrupt watch dog for CPU1.
428 esp_int_wdt_cpu_init();
429 #endif
430
431 esp_crosscore_int_init();
432 #if CONFIG_IDF_TARGET_ESP32
433 esp_dport_access_int_init();
434 #endif
435
436 ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
437 xPortStartScheduler();
438 abort(); /* Only get to here if FreeRTOS somehow very broken */
439 }
440 #endif // !CONFIG_FREERTOS_UNICORE
441
442 extern void esp_startup_start_app_common(void);
443
esp_startup_start_app(void)444 void esp_startup_start_app(void)
445 {
446 #if !CONFIG_ESP_INT_WDT
447 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
448 assert(!soc_has_cache_lock_bug() && "ESP32 Rev 3 + Dual Core + PSRAM requires INT WDT enabled in project config!");
449 #endif
450 #endif
451
452 // ESP32 has single core variants. Check that FreeRTOS has been configured properly.
453 #if CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
454 if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_DIS_APP_CPU)) {
455 ESP_EARLY_LOGE(TAG, "Running on single core chip, but FreeRTOS is built with dual core support.");
456 ESP_EARLY_LOGE(TAG, "Please enable CONFIG_FREERTOS_UNICORE option in menuconfig.");
457 abort();
458 }
459 #endif // CONFIG_IDF_TARGET_ESP32 && !CONFIG_FREERTOS_UNICORE
460
461 esp_startup_start_app_common();
462
463 ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
464 // vTaskStartScheduler();
465 }
466