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1 /*
2  * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
17  */
18 
19 #ifndef __MIPI_RX_HAL_H__
20 #define __MIPI_RX_HAL_H__
21 
22 #include "hi_mipi.h"
23 
24 #define MIPI_RX_MAX_PHY_NUM                    1
25 #define MIPI_RX_MAX_EXT_DATA_TYPE_BIT_WIDTH    16
26 #define MIPI_RX_MIN_EXT_DATA_TYPE_BIT_WIDTH    8
27 
28 #define MIPI_CIL_INT_MASK   0x00003f3f
29 #define MIPI_CTRL_INT_MASK  0x00030003
30 #define LVDS_CTRL_INT_MASK  0x0f110000 /* lvds_vsync_msk and lane0~3_sync_err_msk ignore, not err int */
31 #define MIPI_FRAME_INT_MASK 0x000f0000
32 #define MIPI_PKT_INT1_MASK  0x0001000f
33 #define MIPI_PKT_INT2_MASK  0x000f000f
34 #define ALIGN0_INT_MASK     0x0000001f
35 
36 typedef struct {
37     unsigned int clk1_fsm_timeout_err_cnt;
38     unsigned int clk0_fsm_timeout_err_cnt;
39     unsigned int d0_fsm_timeout_err_cnt;
40     unsigned int d1_fsm_timeout_err_cnt;
41     unsigned int d2_fsm_timeout_err_cnt;
42     unsigned int d3_fsm_timeout_err_cnt;
43 
44     unsigned int clk1_fsm_escape_err_cnt;
45     unsigned int clk0_fsm_escape_err_cnt;
46     unsigned int d0_fsm_escape_err_cnt;
47     unsigned int d1_fsm_escape_err_cnt;
48     unsigned int d2_fsm_escape_err_cnt;
49     unsigned int d3_fsm_escape_err_cnt;
50 } phy_err_int_cnt_t;
51 
52 typedef struct {
53     /* Packet err */
54     unsigned int err_ecc_double_cnt;
55     unsigned int vc3_err_crc_cnt;
56     unsigned int vc2_err_crc_cnt;
57     unsigned int vc1_err_crc_cnt;
58     unsigned int vc0_err_crc_cnt;
59     unsigned int vc3_err_ecc_corrected_cnt;
60     unsigned int vc2_err_ecc_corrected_cnt;
61     unsigned int vc1_err_ecc_corrected_cnt;
62     unsigned int vc0_err_ecc_corrected_cnt;
63     unsigned int err_id_vc3_cnt;
64     unsigned int err_id_vc2_cnt;
65     unsigned int err_id_vc1_cnt;
66     unsigned int err_id_vc0_cnt;
67 
68     /* Frame err */
69     unsigned int err_frame_data_vc3_cnt;
70     unsigned int err_frame_data_vc2_cnt;
71     unsigned int err_frame_data_vc1_cnt;
72     unsigned int err_frame_data_vc0_cnt;
73     unsigned int err_f_seq_vc3_cnt;
74     unsigned int err_f_seq_vc2_cnt;
75     unsigned int err_f_seq_vc1_cnt;
76     unsigned int err_f_seq_vc0_cnt;
77     unsigned int err_f_bndry_match_vc3_cnt;
78     unsigned int err_f_bndry_match_vc2_cnt;
79     unsigned int err_f_bndry_match_vc1_cnt;
80     unsigned int err_f_bndry_match_vc0_cnt;
81 
82     /* Ctrl err */
83     unsigned int data_fifo_rderr_cnt;
84     unsigned int cmd_fifo_rderr_cnt;
85     unsigned int data_fifo_wrerr_cnt;
86     unsigned int cmd_fifo_wrerr_cnt;
87 } mipi_err_int_cnt_t;
88 
89 typedef struct {
90     unsigned int cmd_rd_err_cnt;
91     unsigned int cmd_wr_err_cnt;
92     unsigned int pop_err_cnt;
93     unsigned int lvds_state_err_cnt;
94     unsigned int link0_rd_err_cnt;
95     unsigned int link0_wr_err_cnt;
96 } lvds_err_int_cnt_t;
97 
98 typedef struct {
99     unsigned int lane3_align_err_cnt;
100     unsigned int lane2_align_err_cnt;
101     unsigned int lane1_align_err_cnt;
102     unsigned int lane0_align_err_cnt;
103     unsigned int fifo_full_err_cnt;
104 } align_err_int_cnt_t;
105 
106 phy_err_int_cnt_t *mipi_rx_hal_get_phy_err_int_cnt(unsigned int phy_id);
107 mipi_err_int_cnt_t *mipi_rx_hal_get_mipi_err_int(unsigned int phy_id);
108 lvds_err_int_cnt_t *mipi_rx_hal_get_lvds_err_int_cnt(unsigned int phy_id);
109 align_err_int_cnt_t *mipi_rx_hal_get_align_err_int_cnt(unsigned int phy_id);
110 
111 /* sensor function */
112 void sensor_drv_enable_clock(sns_clk_source_t sns_clk_source);
113 void sensor_drv_disable_clock(sns_clk_source_t sns_clk_source);
114 
115 void sensor_drv_reset(sns_rst_source_t sns_reset_source);
116 void sensor_drv_unreset(sns_rst_source_t sns_reset_source);
117 
118 /* mipi_rx function */
119 void mipi_rx_drv_set_work_mode(combo_dev_t devno, input_mode_t input_mode);
120 void mipi_rx_drv_set_mipi_image_rect(combo_dev_t devno, img_rect_t *p_img_rect);
121 void mipi_rx_drv_set_mipi_crop_en(combo_dev_t devno, int enable);
122 void mipi_rx_drv_set_di_dt(combo_dev_t devno, data_type_t input_data_type);
123 void mipi_rx_drv_set_mipi_yuv_dt(combo_dev_t devno, data_type_t input_data_type);
124 void mipi_rx_drv_set_mipi_wdr_user_dt(combo_dev_t devno, data_type_t input_data_type,
125     const short data_type[WDR_VC_NUM]);
126 void mipi_rx_drv_set_mipi_dol_id(combo_dev_t devno, data_type_t input_data_type, short dol_id[]);
127 void mipi_rx_drv_set_mipi_wdr_mode(combo_dev_t devno, mipi_wdr_mode_t wdr_mode);
128 unsigned int mipi_rx_drv_get_phy_data(int phy_id, int lane_id);
129 unsigned int mipi_rx_drv_get_phy_mipi_link_data(int phy_id, int lane_id);
130 unsigned int mipi_rx_drv_get_phy_lvds_link_data(int phy_id, int lane_id);
131 
132 void mipi_rx_drv_set_data_rate(combo_dev_t devno, mipi_data_rate_t data_rate);
133 void mipi_rx_drv_set_link_lane_id(combo_dev_t devno, input_mode_t input_mode, const short *p_lane_id,
134     unsigned int lane_bitmap, lane_divide_mode_t mode);
135 void mipi_rx_drv_set_mem_cken(combo_dev_t devno, int enable);
136 void mipi_rx_drv_set_clr_cken(combo_dev_t devno, int enable);
137 void mipi_rx_drv_set_lane_num(combo_dev_t devno, unsigned int lane_num);
138 void mipi_rx_drv_set_phy_config(input_mode_t input_mode, unsigned int lane_bitmap);
139 void mipi_rx_drv_set_phy_cmvmode(input_mode_t input_mode, phy_cmv_mode_t cmv_mode, unsigned int lane_bitmap);
140 
141 void mipi_rx_drv_set_phy_en(unsigned int lane_bitmap);
142 void mipi_rx_drv_set_cmos_en(unsigned int phy_id, int enable);
143 void mipi_rx_drv_set_lane_en(unsigned int lane_bitmap);
144 void mipi_rx_drv_set_phy_cil_en(unsigned int lane_bitmap, int enable);
145 void mipi_rx_drv_set_phy_cfg_mode(input_mode_t input_mode, unsigned int lane_bitmap);
146 void mipi_rx_drv_set_phy_cfg_en(unsigned int lane_bitmap, int enable);
147 void mipi_rx_set_phy_rg_lp0_mode_en(unsigned int phy_id, int enable);
148 void mipi_rx_set_phy_rg_lp1_mode_en(unsigned int phy_id, int enable);
149 void mipi_rx_drv_set_ext_data_type(ext_data_type_t* data_type, data_type_t input_data_type);
150 
151 void mipi_rx_drv_set_lvds_image_rect(combo_dev_t devno, img_rect_t *p_img_rect, short total_lane_num);
152 void mipi_rx_drv_set_lvds_crop_en(combo_dev_t devno, int enable);
153 
154 int mipi_rx_drv_set_lvds_wdr_mode(combo_dev_t devno, wdr_mode_t wdr_mode,
155                                   lvds_vsync_attr_t *vsync_attr, lvds_fid_attr_t *fid_attr);
156 void mipi_rx_drv_set_lvds_ctrl_mode(combo_dev_t devno, lvds_sync_mode_t sync_mode,
157                                     data_type_t input_data_type,
158                                     lvds_bit_endian_t data_endian,
159                                     lvds_bit_endian_t sync_code_endian);
160 
161 void mipi_rx_drv_set_lvds_data_rate(combo_dev_t devno, mipi_data_rate_t data_rate);
162 
163 void mipi_rx_drv_set_dol_line_information(combo_dev_t devno, wdr_mode_t wdr_mode);
164 void mipi_rx_drv_set_lvds_sync_code(combo_dev_t devno, unsigned int lane_cnt,
165                                     const short lane_id[LVDS_LANE_NUM],
166                                     unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM]);
167 
168 void mipi_rx_drv_set_lvds_nxt_sync_code(combo_dev_t devno, unsigned int lane_cnt,
169                                         const short lane_id[LVDS_LANE_NUM],
170                                         unsigned short sync_code[][WDR_VC_NUM][SYNC_CODE_NUM]);
171 
172 void mipi_rx_drv_set_phy_sync_config(lvds_dev_attr_t *p_attr, unsigned int lane_bitmap,
173                                      unsigned short nxt_sync_code[][WDR_VC_NUM][SYNC_CODE_NUM]);
174 
175 int mipi_rx_drv_is_lane_valid(combo_dev_t devno, short lane_id, lane_divide_mode_t mode);
176 void mipi_rx_drv_set_hs_mode(lane_divide_mode_t lane_divide_mode);
177 
178 void mipi_rx_drv_get_mipi_imgsize_statis(combo_dev_t devno, short vc, img_size_t *p_size);
179 void mipi_rx_drv_get_lvds_imgsize_statis(combo_dev_t devno, short vc, img_size_t *p_size);
180 void mipi_rx_drv_get_lvds_lane_imgsize_statis(combo_dev_t devno, short lane, img_size_t *p_size);
181 
182 void mipi_rx_drv_set_mipi_int_mask(combo_dev_t devno);
183 void mipi_rx_drv_set_lvds_ctrl_int_mask(combo_dev_t devno, unsigned int mask);
184 void mipi_rx_drv_set_mipi_ctrl_int_mask(combo_dev_t devno, unsigned int mask);
185 void mipi_rx_drv_set_mipi_pkt1_int_mask(combo_dev_t devno, unsigned int mask);
186 void mipi_rx_drv_set_mipi_pkt2_int_mask(combo_dev_t devno, unsigned int mask);
187 void mipi_rx_drv_set_mipi_frame_int_mask(combo_dev_t devno, unsigned int mask);
188 void mipi_rx_drv_set_align_int_mask(combo_dev_t devno, unsigned int mask);
189 
190 void mipi_rx_drv_enable_clock(combo_dev_t combo_dev);
191 void mipi_rx_drv_disable_clock(combo_dev_t combo_dev);
192 
193 void mipi_rx_drv_core_reset(combo_dev_t combo_dev);
194 void mipi_rx_drv_core_unreset(combo_dev_t combo_dev);
195 
196 int mipi_rx_drv_init(void);
197 void mipi_rx_drv_exit(void);
198 
199 #endif
200