1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Broadcom
4 */
5
6 /**
7 * DOC: VC4 plane module
8 *
9 * Each DRM plane is a layer of pixels being scanned out by the HVS.
10 *
11 * At atomic modeset check time, we compute the HVS display element
12 * state that would be necessary for displaying the plane (giving us a
13 * chance to figure out if a plane configuration is invalid), then at
14 * atomic flush time the CRTC will ask us to write our element state
15 * into the region of the HVS that it has allocated for us.
16 */
17
18 #include <drm/drm_atomic.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_atomic_uapi.h>
21 #include <drm/drm_fb_cma_helper.h>
22 #include <drm/drm_fourcc.h>
23 #include <drm/drm_gem_framebuffer_helper.h>
24 #include <drm/drm_plane_helper.h>
25
26 #include "uapi/drm/vc4_drm.h"
27
28 #include "vc4_drv.h"
29 #include "vc4_regs.h"
30
31 static const struct hvs_format {
32 u32 drm; /* DRM_FORMAT_* */
33 u32 hvs; /* HVS_FORMAT_* */
34 u32 pixel_order;
35 u32 pixel_order_hvs5;
36 } hvs_formats[] = {
37 {
38 .drm = DRM_FORMAT_XRGB8888,
39 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
40 .pixel_order = HVS_PIXEL_ORDER_ABGR,
41 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
42 },
43 {
44 .drm = DRM_FORMAT_ARGB8888,
45 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
46 .pixel_order = HVS_PIXEL_ORDER_ABGR,
47 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
48 },
49 {
50 .drm = DRM_FORMAT_ABGR8888,
51 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
52 .pixel_order = HVS_PIXEL_ORDER_ARGB,
53 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
54 },
55 {
56 .drm = DRM_FORMAT_XBGR8888,
57 .hvs = HVS_PIXEL_FORMAT_RGBA8888,
58 .pixel_order = HVS_PIXEL_ORDER_ARGB,
59 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
60 },
61 {
62 .drm = DRM_FORMAT_RGB565,
63 .hvs = HVS_PIXEL_FORMAT_RGB565,
64 .pixel_order = HVS_PIXEL_ORDER_XRGB,
65 },
66 {
67 .drm = DRM_FORMAT_BGR565,
68 .hvs = HVS_PIXEL_FORMAT_RGB565,
69 .pixel_order = HVS_PIXEL_ORDER_XBGR,
70 },
71 {
72 .drm = DRM_FORMAT_ARGB1555,
73 .hvs = HVS_PIXEL_FORMAT_RGBA5551,
74 .pixel_order = HVS_PIXEL_ORDER_ABGR,
75 },
76 {
77 .drm = DRM_FORMAT_XRGB1555,
78 .hvs = HVS_PIXEL_FORMAT_RGBA5551,
79 .pixel_order = HVS_PIXEL_ORDER_ABGR,
80 },
81 {
82 .drm = DRM_FORMAT_RGB888,
83 .hvs = HVS_PIXEL_FORMAT_RGB888,
84 .pixel_order = HVS_PIXEL_ORDER_XRGB,
85 },
86 {
87 .drm = DRM_FORMAT_BGR888,
88 .hvs = HVS_PIXEL_FORMAT_RGB888,
89 .pixel_order = HVS_PIXEL_ORDER_XBGR,
90 },
91 {
92 .drm = DRM_FORMAT_YUV422,
93 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
94 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
95 },
96 {
97 .drm = DRM_FORMAT_YVU422,
98 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
99 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
100 },
101 {
102 .drm = DRM_FORMAT_YUV420,
103 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
104 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
105 },
106 {
107 .drm = DRM_FORMAT_YVU420,
108 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
109 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
110 },
111 {
112 .drm = DRM_FORMAT_NV12,
113 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
114 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
115 },
116 {
117 .drm = DRM_FORMAT_NV21,
118 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
119 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
120 },
121 {
122 .drm = DRM_FORMAT_NV16,
123 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
124 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
125 },
126 {
127 .drm = DRM_FORMAT_NV61,
128 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
129 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
130 },
131 };
132
vc4_get_hvs_format(u32 drm_format)133 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
134 {
135 unsigned i;
136
137 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
138 if (hvs_formats[i].drm == drm_format)
139 return &hvs_formats[i];
140 }
141
142 return NULL;
143 }
144
vc4_get_scaling_mode(u32 src,u32 dst)145 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
146 {
147 if (dst == src)
148 return VC4_SCALING_NONE;
149 if (3 * dst >= 2 * src)
150 return VC4_SCALING_PPF;
151 else
152 return VC4_SCALING_TPZ;
153 }
154
plane_enabled(struct drm_plane_state * state)155 static bool plane_enabled(struct drm_plane_state *state)
156 {
157 return state->fb && !WARN_ON(!state->crtc);
158 }
159
vc4_plane_duplicate_state(struct drm_plane * plane)160 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
161 {
162 struct vc4_plane_state *vc4_state;
163
164 if (WARN_ON(!plane->state))
165 return NULL;
166
167 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
168 if (!vc4_state)
169 return NULL;
170
171 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
172 vc4_state->dlist_initialized = 0;
173
174 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
175
176 if (vc4_state->dlist) {
177 vc4_state->dlist = kmemdup(vc4_state->dlist,
178 vc4_state->dlist_count * 4,
179 GFP_KERNEL);
180 if (!vc4_state->dlist) {
181 kfree(vc4_state);
182 return NULL;
183 }
184 vc4_state->dlist_size = vc4_state->dlist_count;
185 }
186
187 return &vc4_state->base;
188 }
189
vc4_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)190 static void vc4_plane_destroy_state(struct drm_plane *plane,
191 struct drm_plane_state *state)
192 {
193 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
194 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
195
196 if (drm_mm_node_allocated(&vc4_state->lbm)) {
197 unsigned long irqflags;
198
199 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
200 drm_mm_remove_node(&vc4_state->lbm);
201 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
202 }
203
204 kfree(vc4_state->dlist);
205 __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
206 kfree(state);
207 }
208
209 /* Called during init to allocate the plane's atomic state. */
vc4_plane_reset(struct drm_plane * plane)210 static void vc4_plane_reset(struct drm_plane *plane)
211 {
212 struct vc4_plane_state *vc4_state;
213
214 WARN_ON(plane->state);
215
216 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
217 if (!vc4_state)
218 return;
219
220 __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
221 }
222
vc4_dlist_counter_increment(struct vc4_plane_state * vc4_state)223 static void vc4_dlist_counter_increment(struct vc4_plane_state *vc4_state)
224 {
225 if (vc4_state->dlist_count == vc4_state->dlist_size) {
226 u32 new_size = max(4u, vc4_state->dlist_count * 2);
227 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
228
229 if (!new_dlist)
230 return;
231 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
232
233 kfree(vc4_state->dlist);
234 vc4_state->dlist = new_dlist;
235 vc4_state->dlist_size = new_size;
236 }
237
238 vc4_state->dlist_count++;
239 }
240
vc4_dlist_write(struct vc4_plane_state * vc4_state,u32 val)241 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
242 {
243 unsigned int idx = vc4_state->dlist_count;
244
245 vc4_dlist_counter_increment(vc4_state);
246 vc4_state->dlist[idx] = val;
247 }
248
249 /* Returns the scl0/scl1 field based on whether the dimensions need to
250 * be up/down/non-scaled.
251 *
252 * This is a replication of a table from the spec.
253 */
vc4_get_scl_field(struct drm_plane_state * state,int plane)254 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
255 {
256 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
257
258 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
259 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
260 return SCALER_CTL0_SCL_H_PPF_V_PPF;
261 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
262 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
263 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
264 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
265 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
266 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
267 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
268 return SCALER_CTL0_SCL_H_PPF_V_NONE;
269 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
270 return SCALER_CTL0_SCL_H_NONE_V_PPF;
271 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
272 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
273 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
274 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
275 default:
276 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
277 /* The unity case is independently handled by
278 * SCALER_CTL0_UNITY.
279 */
280 return 0;
281 }
282 }
283
vc4_plane_margins_adj(struct drm_plane_state * pstate)284 static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
285 {
286 struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
287 unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay;
288 struct drm_crtc_state *crtc_state;
289
290 crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
291 pstate->crtc);
292
293 vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
294 if (!left && !right && !top && !bottom)
295 return 0;
296
297 if (left + right >= crtc_state->mode.hdisplay ||
298 top + bottom >= crtc_state->mode.vdisplay)
299 return -EINVAL;
300
301 adjhdisplay = crtc_state->mode.hdisplay - (left + right);
302 vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
303 adjhdisplay,
304 crtc_state->mode.hdisplay);
305 vc4_pstate->crtc_x += left;
306 if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - right)
307 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - right;
308
309 adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
310 vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
311 adjvdisplay,
312 crtc_state->mode.vdisplay);
313 vc4_pstate->crtc_y += top;
314 if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - bottom)
315 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - bottom;
316
317 vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
318 adjhdisplay,
319 crtc_state->mode.hdisplay);
320 vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
321 adjvdisplay,
322 crtc_state->mode.vdisplay);
323
324 if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
325 return -EINVAL;
326
327 return 0;
328 }
329
vc4_plane_setup_clipping_and_scaling(struct drm_plane_state * state)330 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
331 {
332 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
333 struct drm_framebuffer *fb = state->fb;
334 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
335 int num_planes = fb->format->num_planes;
336 struct drm_crtc_state *crtc_state;
337 u32 h_subsample = fb->format->hsub;
338 u32 v_subsample = fb->format->vsub;
339 int i, ret;
340
341 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
342 state->crtc);
343 if (!crtc_state) {
344 DRM_DEBUG_KMS("Invalid crtc state\n");
345 return -EINVAL;
346 }
347
348 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,
349 INT_MAX, true, true);
350 if (ret)
351 return ret;
352
353 for (i = 0; i < num_planes; i++)
354 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
355
356 /*
357 * We don't support subpixel source positioning for scaling,
358 * but fractional coordinates can be generated by clipping
359 * so just round for now
360 */
361 vc4_state->src_x = DIV_ROUND_CLOSEST(state->src.x1, 1 << 16);
362 vc4_state->src_y = DIV_ROUND_CLOSEST(state->src.y1, 1 << 16);
363 vc4_state->src_w[0] = DIV_ROUND_CLOSEST(state->src.x2, 1 << 16) - vc4_state->src_x;
364 vc4_state->src_h[0] = DIV_ROUND_CLOSEST(state->src.y2, 1 << 16) - vc4_state->src_y;
365
366 vc4_state->crtc_x = state->dst.x1;
367 vc4_state->crtc_y = state->dst.y1;
368 vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
369 vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
370
371 ret = vc4_plane_margins_adj(state);
372 if (ret)
373 return ret;
374
375 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
376 vc4_state->crtc_w);
377 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
378 vc4_state->crtc_h);
379
380 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
381 vc4_state->y_scaling[0] == VC4_SCALING_NONE);
382
383 if (num_planes > 1) {
384 vc4_state->is_yuv = true;
385
386 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
387 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
388
389 vc4_state->x_scaling[1] =
390 vc4_get_scaling_mode(vc4_state->src_w[1],
391 vc4_state->crtc_w);
392 vc4_state->y_scaling[1] =
393 vc4_get_scaling_mode(vc4_state->src_h[1],
394 vc4_state->crtc_h);
395
396 /* YUV conversion requires that horizontal scaling be enabled
397 * on the UV plane even if vc4_get_scaling_mode() returned
398 * VC4_SCALING_NONE (which can happen when the down-scaling
399 * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
400 * case.
401 */
402 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
403 vc4_state->x_scaling[1] = VC4_SCALING_PPF;
404 } else {
405 vc4_state->is_yuv = false;
406 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
407 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
408 }
409
410 return 0;
411 }
412
vc4_write_tpz(struct vc4_plane_state * vc4_state,u32 src,u32 dst)413 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
414 {
415 u32 scale, recip;
416
417 scale = (1 << 16) * src / dst;
418
419 /* The specs note that while the reciprocal would be defined
420 * as (1<<32)/scale, ~0 is close enough.
421 */
422 recip = ~0 / scale;
423
424 vc4_dlist_write(vc4_state,
425 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
426 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
427 vc4_dlist_write(vc4_state,
428 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
429 }
430
vc4_write_ppf(struct vc4_plane_state * vc4_state,u32 src,u32 dst)431 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
432 {
433 u32 scale = (1 << 16) * src / dst;
434
435 vc4_dlist_write(vc4_state,
436 SCALER_PPF_AGC |
437 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
438 VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
439 }
440
vc4_lbm_size(struct drm_plane_state * state)441 static u32 vc4_lbm_size(struct drm_plane_state *state)
442 {
443 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
444 struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
445 u32 pix_per_line;
446 u32 lbm;
447
448 /* LBM is not needed when there's no vertical scaling. */
449 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
450 vc4_state->y_scaling[1] == VC4_SCALING_NONE)
451 return 0;
452
453 /*
454 * This can be further optimized in the RGB/YUV444 case if the PPF
455 * decimation factor is between 0.5 and 1.0 by using crtc_w.
456 *
457 * It's not an issue though, since in that case since src_w[0] is going
458 * to be greater than or equal to crtc_w.
459 */
460 if (vc4_state->x_scaling[0] == VC4_SCALING_TPZ)
461 pix_per_line = vc4_state->crtc_w;
462 else
463 pix_per_line = vc4_state->src_w[0];
464
465 if (!vc4_state->is_yuv) {
466 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
467 lbm = pix_per_line * 8;
468 else {
469 /* In special cases, this multiplier might be 12. */
470 lbm = pix_per_line * 16;
471 }
472 } else {
473 /* There are cases for this going down to a multiplier
474 * of 2, but according to the firmware source, the
475 * table in the docs is somewhat wrong.
476 */
477 lbm = pix_per_line * 16;
478 }
479
480 /* Align it to 64 or 128 (hvs5) bytes */
481 lbm = roundup(lbm, vc4->hvs->hvs5 ? 128 : 64);
482
483 /* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
484 lbm /= vc4->hvs->hvs5 ? 4 : 2;
485
486 return lbm;
487 }
488
vc4_write_scaling_parameters(struct drm_plane_state * state,int channel)489 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
490 int channel)
491 {
492 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
493
494 /* Ch0 H-PPF Word 0: Scaling Parameters */
495 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
496 vc4_write_ppf(vc4_state,
497 vc4_state->src_w[channel], vc4_state->crtc_w);
498 }
499
500 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
501 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
502 vc4_write_ppf(vc4_state,
503 vc4_state->src_h[channel], vc4_state->crtc_h);
504 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
505 }
506
507 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
508 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
509 vc4_write_tpz(vc4_state,
510 vc4_state->src_w[channel], vc4_state->crtc_w);
511 }
512
513 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
514 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
515 vc4_write_tpz(vc4_state,
516 vc4_state->src_h[channel], vc4_state->crtc_h);
517 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
518 }
519 }
520
vc4_plane_calc_load(struct drm_plane_state * state)521 static void vc4_plane_calc_load(struct drm_plane_state *state)
522 {
523 unsigned int hvs_load_shift, vrefresh, i;
524 struct drm_framebuffer *fb = state->fb;
525 struct vc4_plane_state *vc4_state;
526 struct drm_crtc_state *crtc_state;
527 unsigned int vscale_factor;
528 struct vc4_dev *vc4;
529
530 vc4 = to_vc4_dev(state->plane->dev);
531 if (!vc4->load_tracker_available)
532 return;
533
534 vc4_state = to_vc4_plane_state(state);
535 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
536 state->crtc);
537 vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode);
538
539 /* The HVS is able to process 2 pixels/cycle when scaling the source,
540 * 4 pixels/cycle otherwise.
541 * Alpha blending step seems to be pipelined and it's always operating
542 * at 4 pixels/cycle, so the limiting aspect here seems to be the
543 * scaler block.
544 * HVS load is expressed in clk-cycles/sec (AKA Hz).
545 */
546 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
547 vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
548 vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
549 vc4_state->y_scaling[1] != VC4_SCALING_NONE)
550 hvs_load_shift = 1;
551 else
552 hvs_load_shift = 2;
553
554 vc4_state->membus_load = 0;
555 vc4_state->hvs_load = 0;
556 for (i = 0; i < fb->format->num_planes; i++) {
557 /* Even if the bandwidth/plane required for a single frame is
558 *
559 * vc4_state->src_w[i] * vc4_state->src_h[i] * cpp * vrefresh
560 *
561 * when downscaling, we have to read more pixels per line in
562 * the time frame reserved for a single line, so the bandwidth
563 * demand can be punctually higher. To account for that, we
564 * calculate the down-scaling factor and multiply the plane
565 * load by this number. We're likely over-estimating the read
566 * demand, but that's better than under-estimating it.
567 */
568 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i],
569 vc4_state->crtc_h);
570 vc4_state->membus_load += vc4_state->src_w[i] *
571 vc4_state->src_h[i] * vscale_factor *
572 fb->format->cpp[i];
573 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
574 }
575
576 vc4_state->hvs_load *= vrefresh;
577 vc4_state->hvs_load >>= hvs_load_shift;
578 vc4_state->membus_load *= vrefresh;
579 }
580
vc4_plane_allocate_lbm(struct drm_plane_state * state)581 static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
582 {
583 struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
584 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
585 unsigned long irqflags;
586 u32 lbm_size;
587
588 lbm_size = vc4_lbm_size(state);
589 if (!lbm_size)
590 return 0;
591
592 if (WARN_ON(!vc4_state->lbm_offset))
593 return -EINVAL;
594
595 /* Allocate the LBM memory that the HVS will use for temporary
596 * storage due to our scaling/format conversion.
597 */
598 if (!drm_mm_node_allocated(&vc4_state->lbm)) {
599 int ret;
600
601 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
602 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
603 &vc4_state->lbm,
604 lbm_size,
605 vc4->hvs->hvs5 ? 64 : 32,
606 0, 0);
607 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
608
609 if (ret)
610 return ret;
611 } else {
612 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
613 }
614
615 vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
616
617 return 0;
618 }
619
620 /* Writes out a full display list for an active plane to the plane's
621 * private dlist state.
622 */
vc4_plane_mode_set(struct drm_plane * plane,struct drm_plane_state * state)623 static int vc4_plane_mode_set(struct drm_plane *plane,
624 struct drm_plane_state *state)
625 {
626 struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
627 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
628 struct drm_framebuffer *fb = state->fb;
629 u32 ctl0_offset = vc4_state->dlist_count;
630 const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
631 u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
632 int num_planes = fb->format->num_planes;
633 u32 h_subsample = fb->format->hsub;
634 u32 v_subsample = fb->format->vsub;
635 bool mix_plane_alpha;
636 bool covers_screen;
637 u32 scl0, scl1, pitch0;
638 u32 tiling, src_y;
639 u32 hvs_format = format->hvs;
640 unsigned int rotation;
641 int ret, i;
642
643 if (vc4_state->dlist_initialized)
644 return 0;
645
646 ret = vc4_plane_setup_clipping_and_scaling(state);
647 if (ret)
648 return ret;
649
650 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB
651 * and 4:4:4, scl1 should be set to scl0 so both channels of
652 * the scaler do the same thing. For YUV, the Y plane needs
653 * to be put in channel 1 and Cb/Cr in channel 0, so we swap
654 * the scl fields here.
655 */
656 if (num_planes == 1) {
657 scl0 = vc4_get_scl_field(state, 0);
658 scl1 = scl0;
659 } else {
660 scl0 = vc4_get_scl_field(state, 1);
661 scl1 = vc4_get_scl_field(state, 0);
662 }
663
664 rotation = drm_rotation_simplify(state->rotation,
665 DRM_MODE_ROTATE_0 |
666 DRM_MODE_REFLECT_X |
667 DRM_MODE_REFLECT_Y);
668
669 /* We must point to the last line when Y reflection is enabled. */
670 src_y = vc4_state->src_y;
671 if (rotation & DRM_MODE_REFLECT_Y)
672 src_y += vc4_state->src_h[0] - 1;
673
674 switch (base_format_mod) {
675 case DRM_FORMAT_MOD_LINEAR:
676 tiling = SCALER_CTL0_TILING_LINEAR;
677 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
678
679 /* Adjust the base pointer to the first pixel to be scanned
680 * out.
681 */
682 for (i = 0; i < num_planes; i++) {
683 vc4_state->offsets[i] += src_y /
684 (i ? v_subsample : 1) *
685 fb->pitches[i];
686
687 vc4_state->offsets[i] += vc4_state->src_x /
688 (i ? h_subsample : 1) *
689 fb->format->cpp[i];
690 }
691
692 break;
693
694 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
695 u32 tile_size_shift = 12; /* T tiles are 4kb */
696 /* Whole-tile offsets, mostly for setting the pitch. */
697 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
698 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
699 u32 tile_w_mask = (1 << tile_w_shift) - 1;
700 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
701 * the height (in pixels) of a 4k tile.
702 */
703 u32 tile_h_mask = (2 << tile_h_shift) - 1;
704 /* For T-tiled, the FB pitch is "how many bytes from one row to
705 * the next, such that
706 *
707 * pitch * tile_h == tile_size * tiles_per_row
708 */
709 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
710 u32 tiles_l = vc4_state->src_x >> tile_w_shift;
711 u32 tiles_r = tiles_w - tiles_l;
712 u32 tiles_t = src_y >> tile_h_shift;
713 /* Intra-tile offsets, which modify the base address (the
714 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
715 * base address).
716 */
717 u32 tile_y = (src_y >> 4) & 1;
718 u32 subtile_y = (src_y >> 2) & 3;
719 u32 utile_y = src_y & 3;
720 u32 x_off = vc4_state->src_x & tile_w_mask;
721 u32 y_off = src_y & tile_h_mask;
722
723 /* When Y reflection is requested we must set the
724 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
725 * after the initial one should be fetched in descending order,
726 * which makes sense since we start from the last line and go
727 * backward.
728 * Don't know why we need y_off = max_y_off - y_off, but it's
729 * definitely required (I guess it's also related to the "going
730 * backward" situation).
731 */
732 if (rotation & DRM_MODE_REFLECT_Y) {
733 y_off = tile_h_mask - y_off;
734 pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
735 } else {
736 pitch0 = 0;
737 }
738
739 tiling = SCALER_CTL0_TILING_256B_OR_T;
740 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
741 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
742 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
743 VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
744 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
745 vc4_state->offsets[0] += subtile_y << 8;
746 vc4_state->offsets[0] += utile_y << 4;
747
748 /* Rows of tiles alternate left-to-right and right-to-left. */
749 if (tiles_t & 1) {
750 pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
751 vc4_state->offsets[0] += (tiles_w - tiles_l) <<
752 tile_size_shift;
753 vc4_state->offsets[0] -= (1 + !tile_y) << 10;
754 } else {
755 vc4_state->offsets[0] += tiles_l << tile_size_shift;
756 vc4_state->offsets[0] += tile_y << 10;
757 }
758
759 break;
760 }
761
762 case DRM_FORMAT_MOD_BROADCOM_SAND64:
763 case DRM_FORMAT_MOD_BROADCOM_SAND128:
764 case DRM_FORMAT_MOD_BROADCOM_SAND256: {
765 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
766 u32 tile_w, tile, x_off, pix_per_tile;
767
768 hvs_format = HVS_PIXEL_FORMAT_H264;
769
770 switch (base_format_mod) {
771 case DRM_FORMAT_MOD_BROADCOM_SAND64:
772 tiling = SCALER_CTL0_TILING_64B;
773 tile_w = 64;
774 break;
775 case DRM_FORMAT_MOD_BROADCOM_SAND128:
776 tiling = SCALER_CTL0_TILING_128B;
777 tile_w = 128;
778 break;
779 case DRM_FORMAT_MOD_BROADCOM_SAND256:
780 tiling = SCALER_CTL0_TILING_256B_OR_T;
781 tile_w = 256;
782 break;
783 default:
784 break;
785 }
786
787 if (param > SCALER_TILE_HEIGHT_MASK) {
788 DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
789 return -EINVAL;
790 }
791
792 pix_per_tile = tile_w / fb->format->cpp[0];
793 tile = vc4_state->src_x / pix_per_tile;
794 x_off = vc4_state->src_x % pix_per_tile;
795
796 /* Adjust the base pointer to the first pixel to be scanned
797 * out.
798 */
799 for (i = 0; i < num_planes; i++) {
800 vc4_state->offsets[i] += param * tile_w * tile;
801 vc4_state->offsets[i] += src_y /
802 (i ? v_subsample : 1) *
803 tile_w;
804 vc4_state->offsets[i] += x_off /
805 (i ? h_subsample : 1) *
806 fb->format->cpp[i];
807 }
808
809 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
810 break;
811 }
812
813 default:
814 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
815 (long long)fb->modifier);
816 return -EINVAL;
817 }
818
819 /* Don't waste cycles mixing with plane alpha if the set alpha
820 * is opaque or there is no per-pixel alpha information.
821 * In any case we use the alpha property value as the fixed alpha.
822 */
823 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
824 fb->format->has_alpha;
825
826 if (!vc4->hvs->hvs5) {
827 /* Control word */
828 vc4_dlist_write(vc4_state,
829 SCALER_CTL0_VALID |
830 (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
831 (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
832 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
833 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
834 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
835 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
836 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
837 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
838 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
839
840 /* Position Word 0: Image Positions and Alpha Value */
841 vc4_state->pos0_offset = vc4_state->dlist_count;
842 vc4_dlist_write(vc4_state,
843 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
844 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
845 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
846
847 /* Position Word 1: Scaled Image Dimensions. */
848 if (!vc4_state->is_unity) {
849 vc4_dlist_write(vc4_state,
850 VC4_SET_FIELD(vc4_state->crtc_w,
851 SCALER_POS1_SCL_WIDTH) |
852 VC4_SET_FIELD(vc4_state->crtc_h,
853 SCALER_POS1_SCL_HEIGHT));
854 }
855
856 /* Position Word 2: Source Image Size, Alpha */
857 vc4_state->pos2_offset = vc4_state->dlist_count;
858 vc4_dlist_write(vc4_state,
859 VC4_SET_FIELD(fb->format->has_alpha ?
860 SCALER_POS2_ALPHA_MODE_PIPELINE :
861 SCALER_POS2_ALPHA_MODE_FIXED,
862 SCALER_POS2_ALPHA_MODE) |
863 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
864 (fb->format->has_alpha ?
865 SCALER_POS2_ALPHA_PREMULT : 0) |
866 VC4_SET_FIELD(vc4_state->src_w[0],
867 SCALER_POS2_WIDTH) |
868 VC4_SET_FIELD(vc4_state->src_h[0],
869 SCALER_POS2_HEIGHT));
870
871 /* Position Word 3: Context. Written by the HVS. */
872 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
873
874 } else {
875 u32 hvs_pixel_order = format->pixel_order;
876
877 if (format->pixel_order_hvs5)
878 hvs_pixel_order = format->pixel_order_hvs5;
879
880 /* Control word */
881 vc4_dlist_write(vc4_state,
882 SCALER_CTL0_VALID |
883 (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
884 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
885 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
886 (vc4_state->is_unity ?
887 SCALER5_CTL0_UNITY : 0) |
888 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
889 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
890 SCALER5_CTL0_ALPHA_EXPAND |
891 SCALER5_CTL0_RGB_EXPAND);
892
893 /* Position Word 0: Image Positions and Alpha Value */
894 vc4_state->pos0_offset = vc4_state->dlist_count;
895 vc4_dlist_write(vc4_state,
896 (rotation & DRM_MODE_REFLECT_Y ?
897 SCALER5_POS0_VFLIP : 0) |
898 VC4_SET_FIELD(vc4_state->crtc_x,
899 SCALER_POS0_START_X) |
900 (rotation & DRM_MODE_REFLECT_X ?
901 SCALER5_POS0_HFLIP : 0) |
902 VC4_SET_FIELD(vc4_state->crtc_y,
903 SCALER5_POS0_START_Y)
904 );
905
906 /* Control Word 2 */
907 vc4_dlist_write(vc4_state,
908 VC4_SET_FIELD(state->alpha >> 4,
909 SCALER5_CTL2_ALPHA) |
910 (fb->format->has_alpha ?
911 SCALER5_CTL2_ALPHA_PREMULT : 0) |
912 (mix_plane_alpha ?
913 SCALER5_CTL2_ALPHA_MIX : 0) |
914 VC4_SET_FIELD(fb->format->has_alpha ?
915 SCALER5_CTL2_ALPHA_MODE_PIPELINE :
916 SCALER5_CTL2_ALPHA_MODE_FIXED,
917 SCALER5_CTL2_ALPHA_MODE)
918 );
919
920 /* Position Word 1: Scaled Image Dimensions. */
921 if (!vc4_state->is_unity) {
922 vc4_dlist_write(vc4_state,
923 VC4_SET_FIELD(vc4_state->crtc_w,
924 SCALER5_POS1_SCL_WIDTH) |
925 VC4_SET_FIELD(vc4_state->crtc_h,
926 SCALER5_POS1_SCL_HEIGHT));
927 }
928
929 /* Position Word 2: Source Image Size */
930 vc4_state->pos2_offset = vc4_state->dlist_count;
931 vc4_dlist_write(vc4_state,
932 VC4_SET_FIELD(vc4_state->src_w[0],
933 SCALER5_POS2_WIDTH) |
934 VC4_SET_FIELD(vc4_state->src_h[0],
935 SCALER5_POS2_HEIGHT));
936
937 /* Position Word 3: Context. Written by the HVS. */
938 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
939 }
940
941
942 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
943 *
944 * The pointers may be any byte address.
945 */
946 vc4_state->ptr0_offset = vc4_state->dlist_count;
947 for (i = 0; i < num_planes; i++)
948 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
949
950 /* Pointer Context Word 0/1/2: Written by the HVS */
951 for (i = 0; i < num_planes; i++)
952 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
953
954 /* Pitch word 0 */
955 vc4_dlist_write(vc4_state, pitch0);
956
957 /* Pitch word 1/2 */
958 for (i = 1; i < num_planes; i++) {
959 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
960 vc4_dlist_write(vc4_state,
961 VC4_SET_FIELD(fb->pitches[i],
962 SCALER_SRC_PITCH));
963 } else {
964 vc4_dlist_write(vc4_state, pitch0);
965 }
966 }
967
968 /* Colorspace conversion words */
969 if (vc4_state->is_yuv) {
970 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
971 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
972 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
973 }
974
975 vc4_state->lbm_offset = 0;
976
977 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
978 vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
979 vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
980 vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
981 /* Reserve a slot for the LBM Base Address. The real value will
982 * be set when calling vc4_plane_allocate_lbm().
983 */
984 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
985 vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
986 vc4_state->lbm_offset = vc4_state->dlist_count;
987 vc4_dlist_counter_increment(vc4_state);
988 }
989
990 if (num_planes > 1) {
991 /* Emit Cb/Cr as channel 0 and Y as channel
992 * 1. This matches how we set up scl0/scl1
993 * above.
994 */
995 vc4_write_scaling_parameters(state, 1);
996 }
997 vc4_write_scaling_parameters(state, 0);
998
999 /* If any PPF setup was done, then all the kernel
1000 * pointers get uploaded.
1001 */
1002 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
1003 vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
1004 vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
1005 vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
1006 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
1007 SCALER_PPF_KERNEL_OFFSET);
1008
1009 /* HPPF plane 0 */
1010 vc4_dlist_write(vc4_state, kernel);
1011 /* VPPF plane 0 */
1012 vc4_dlist_write(vc4_state, kernel);
1013 /* HPPF plane 1 */
1014 vc4_dlist_write(vc4_state, kernel);
1015 /* VPPF plane 1 */
1016 vc4_dlist_write(vc4_state, kernel);
1017 }
1018 }
1019
1020 vc4_state->dlist[ctl0_offset] |=
1021 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
1022
1023 /* crtc_* are already clipped coordinates. */
1024 covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
1025 vc4_state->crtc_w == state->crtc->mode.hdisplay &&
1026 vc4_state->crtc_h == state->crtc->mode.vdisplay;
1027 /* Background fill might be necessary when the plane has per-pixel
1028 * alpha content or a non-opaque plane alpha and could blend from the
1029 * background or does not cover the entire screen.
1030 */
1031 vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
1032 state->alpha != DRM_BLEND_ALPHA_OPAQUE;
1033
1034 /* Flag the dlist as initialized to avoid checking it twice in case
1035 * the async update check already called vc4_plane_mode_set() and
1036 * decided to fallback to sync update because async update was not
1037 * possible.
1038 */
1039 vc4_state->dlist_initialized = 1;
1040
1041 vc4_plane_calc_load(state);
1042
1043 return 0;
1044 }
1045
1046 /* If a modeset involves changing the setup of a plane, the atomic
1047 * infrastructure will call this to validate a proposed plane setup.
1048 * However, if a plane isn't getting updated, this (and the
1049 * corresponding vc4_plane_atomic_update) won't get called. Thus, we
1050 * compute the dlist here and have all active plane dlists get updated
1051 * in the CRTC's flush.
1052 */
vc4_plane_atomic_check(struct drm_plane * plane,struct drm_plane_state * state)1053 static int vc4_plane_atomic_check(struct drm_plane *plane,
1054 struct drm_plane_state *state)
1055 {
1056 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
1057 int ret;
1058
1059 vc4_state->dlist_count = 0;
1060
1061 if (!plane_enabled(state))
1062 return 0;
1063
1064 ret = vc4_plane_mode_set(plane, state);
1065 if (ret)
1066 return ret;
1067
1068 return vc4_plane_allocate_lbm(state);
1069 }
1070
vc4_plane_atomic_update(struct drm_plane * plane,struct drm_plane_state * old_state)1071 static void vc4_plane_atomic_update(struct drm_plane *plane,
1072 struct drm_plane_state *old_state)
1073 {
1074 /* No contents here. Since we don't know where in the CRTC's
1075 * dlist we should be stored, our dlist is uploaded to the
1076 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
1077 * time.
1078 */
1079 }
1080
vc4_plane_write_dlist(struct drm_plane * plane,u32 __iomem * dlist)1081 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
1082 {
1083 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
1084 int i;
1085
1086 vc4_state->hw_dlist = dlist;
1087
1088 /* Can't memcpy_toio() because it needs to be 32-bit writes. */
1089 for (i = 0; i < vc4_state->dlist_count; i++)
1090 writel(vc4_state->dlist[i], &dlist[i]);
1091
1092 return vc4_state->dlist_count;
1093 }
1094
vc4_plane_dlist_size(const struct drm_plane_state * state)1095 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
1096 {
1097 const struct vc4_plane_state *vc4_state =
1098 container_of(state, typeof(*vc4_state), base);
1099
1100 return vc4_state->dlist_count;
1101 }
1102
1103 /* Updates the plane to immediately (well, once the FIFO needs
1104 * refilling) scan out from at a new framebuffer.
1105 */
vc4_plane_async_set_fb(struct drm_plane * plane,struct drm_framebuffer * fb)1106 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
1107 {
1108 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
1109 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
1110 uint32_t addr;
1111
1112 /* We're skipping the address adjustment for negative origin,
1113 * because this is only called on the primary plane.
1114 */
1115 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
1116 addr = bo->paddr + fb->offsets[0];
1117
1118 /* Write the new address into the hardware immediately. The
1119 * scanout will start from this address as soon as the FIFO
1120 * needs to refill with pixels.
1121 */
1122 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1123
1124 /* Also update the CPU-side dlist copy, so that any later
1125 * atomic updates that don't do a new modeset on our plane
1126 * also use our updated address.
1127 */
1128 vc4_state->dlist[vc4_state->ptr0_offset] = addr;
1129 }
1130
vc4_plane_atomic_async_update(struct drm_plane * plane,struct drm_plane_state * state)1131 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
1132 struct drm_plane_state *state)
1133 {
1134 struct vc4_plane_state *vc4_state, *new_vc4_state;
1135
1136 swap(plane->state->fb, state->fb);
1137 plane->state->crtc_x = state->crtc_x;
1138 plane->state->crtc_y = state->crtc_y;
1139 plane->state->crtc_w = state->crtc_w;
1140 plane->state->crtc_h = state->crtc_h;
1141 plane->state->src_x = state->src_x;
1142 plane->state->src_y = state->src_y;
1143 plane->state->src_w = state->src_w;
1144 plane->state->src_h = state->src_h;
1145 plane->state->src_h = state->src_h;
1146 plane->state->alpha = state->alpha;
1147 plane->state->pixel_blend_mode = state->pixel_blend_mode;
1148 plane->state->rotation = state->rotation;
1149 plane->state->zpos = state->zpos;
1150 plane->state->normalized_zpos = state->normalized_zpos;
1151 plane->state->color_encoding = state->color_encoding;
1152 plane->state->color_range = state->color_range;
1153 plane->state->src = state->src;
1154 plane->state->dst = state->dst;
1155 plane->state->visible = state->visible;
1156
1157 new_vc4_state = to_vc4_plane_state(state);
1158 vc4_state = to_vc4_plane_state(plane->state);
1159
1160 vc4_state->crtc_x = new_vc4_state->crtc_x;
1161 vc4_state->crtc_y = new_vc4_state->crtc_y;
1162 vc4_state->crtc_h = new_vc4_state->crtc_h;
1163 vc4_state->crtc_w = new_vc4_state->crtc_w;
1164 vc4_state->src_x = new_vc4_state->src_x;
1165 vc4_state->src_y = new_vc4_state->src_y;
1166 memcpy(vc4_state->src_w, new_vc4_state->src_w,
1167 sizeof(vc4_state->src_w));
1168 memcpy(vc4_state->src_h, new_vc4_state->src_h,
1169 sizeof(vc4_state->src_h));
1170 memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
1171 sizeof(vc4_state->x_scaling));
1172 memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
1173 sizeof(vc4_state->y_scaling));
1174 vc4_state->is_unity = new_vc4_state->is_unity;
1175 vc4_state->is_yuv = new_vc4_state->is_yuv;
1176 memcpy(vc4_state->offsets, new_vc4_state->offsets,
1177 sizeof(vc4_state->offsets));
1178 vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
1179
1180 /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
1181 vc4_state->dlist[vc4_state->pos0_offset] =
1182 new_vc4_state->dlist[vc4_state->pos0_offset];
1183 vc4_state->dlist[vc4_state->pos2_offset] =
1184 new_vc4_state->dlist[vc4_state->pos2_offset];
1185 vc4_state->dlist[vc4_state->ptr0_offset] =
1186 new_vc4_state->dlist[vc4_state->ptr0_offset];
1187
1188 /* Note that we can't just call vc4_plane_write_dlist()
1189 * because that would smash the context data that the HVS is
1190 * currently using.
1191 */
1192 writel(vc4_state->dlist[vc4_state->pos0_offset],
1193 &vc4_state->hw_dlist[vc4_state->pos0_offset]);
1194 writel(vc4_state->dlist[vc4_state->pos2_offset],
1195 &vc4_state->hw_dlist[vc4_state->pos2_offset]);
1196 writel(vc4_state->dlist[vc4_state->ptr0_offset],
1197 &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1198 }
1199
vc4_plane_atomic_async_check(struct drm_plane * plane,struct drm_plane_state * state)1200 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
1201 struct drm_plane_state *state)
1202 {
1203 struct vc4_plane_state *old_vc4_state, *new_vc4_state;
1204 int ret;
1205 u32 i;
1206
1207 ret = vc4_plane_mode_set(plane, state);
1208 if (ret)
1209 return ret;
1210
1211 old_vc4_state = to_vc4_plane_state(plane->state);
1212 new_vc4_state = to_vc4_plane_state(state);
1213 if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1214 old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1215 old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
1216 old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
1217 vc4_lbm_size(plane->state) != vc4_lbm_size(state))
1218 return -EINVAL;
1219
1220 /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update
1221 * if anything else has changed, fallback to a sync update.
1222 */
1223 for (i = 0; i < new_vc4_state->dlist_count; i++) {
1224 if (i == new_vc4_state->pos0_offset ||
1225 i == new_vc4_state->pos2_offset ||
1226 i == new_vc4_state->ptr0_offset ||
1227 (new_vc4_state->lbm_offset &&
1228 i == new_vc4_state->lbm_offset))
1229 continue;
1230
1231 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i])
1232 return -EINVAL;
1233 }
1234
1235 return 0;
1236 }
1237
vc4_prepare_fb(struct drm_plane * plane,struct drm_plane_state * state)1238 static int vc4_prepare_fb(struct drm_plane *plane,
1239 struct drm_plane_state *state)
1240 {
1241 struct vc4_bo *bo;
1242 int ret;
1243
1244 if (!state->fb)
1245 return 0;
1246
1247 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1248
1249 drm_gem_fb_prepare_fb(plane, state);
1250
1251 if (plane->state->fb == state->fb)
1252 return 0;
1253
1254 ret = vc4_bo_inc_usecnt(bo);
1255 if (ret)
1256 return ret;
1257
1258 return 0;
1259 }
1260
vc4_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)1261 static void vc4_cleanup_fb(struct drm_plane *plane,
1262 struct drm_plane_state *state)
1263 {
1264 struct vc4_bo *bo;
1265
1266 if (plane->state->fb == state->fb || !state->fb)
1267 return;
1268
1269 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1270 vc4_bo_dec_usecnt(bo);
1271 }
1272
1273 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
1274 .atomic_check = vc4_plane_atomic_check,
1275 .atomic_update = vc4_plane_atomic_update,
1276 .prepare_fb = vc4_prepare_fb,
1277 .cleanup_fb = vc4_cleanup_fb,
1278 .atomic_async_check = vc4_plane_atomic_async_check,
1279 .atomic_async_update = vc4_plane_atomic_async_update,
1280 };
1281
vc4_plane_destroy(struct drm_plane * plane)1282 static void vc4_plane_destroy(struct drm_plane *plane)
1283 {
1284 drm_plane_cleanup(plane);
1285 }
1286
vc4_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)1287 static bool vc4_format_mod_supported(struct drm_plane *plane,
1288 uint32_t format,
1289 uint64_t modifier)
1290 {
1291 /* Support T_TILING for RGB formats only. */
1292 switch (format) {
1293 case DRM_FORMAT_XRGB8888:
1294 case DRM_FORMAT_ARGB8888:
1295 case DRM_FORMAT_ABGR8888:
1296 case DRM_FORMAT_XBGR8888:
1297 case DRM_FORMAT_RGB565:
1298 case DRM_FORMAT_BGR565:
1299 case DRM_FORMAT_ARGB1555:
1300 case DRM_FORMAT_XRGB1555:
1301 switch (fourcc_mod_broadcom_mod(modifier)) {
1302 case DRM_FORMAT_MOD_LINEAR:
1303 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
1304 return true;
1305 default:
1306 return false;
1307 }
1308 case DRM_FORMAT_NV12:
1309 case DRM_FORMAT_NV21:
1310 switch (fourcc_mod_broadcom_mod(modifier)) {
1311 case DRM_FORMAT_MOD_LINEAR:
1312 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1313 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1314 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1315 return true;
1316 default:
1317 return false;
1318 }
1319 case DRM_FORMAT_RGBX1010102:
1320 case DRM_FORMAT_BGRX1010102:
1321 case DRM_FORMAT_RGBA1010102:
1322 case DRM_FORMAT_BGRA1010102:
1323 case DRM_FORMAT_YUV422:
1324 case DRM_FORMAT_YVU422:
1325 case DRM_FORMAT_YUV420:
1326 case DRM_FORMAT_YVU420:
1327 case DRM_FORMAT_NV16:
1328 case DRM_FORMAT_NV61:
1329 default:
1330 return (modifier == DRM_FORMAT_MOD_LINEAR);
1331 }
1332 }
1333
1334 static const struct drm_plane_funcs vc4_plane_funcs = {
1335 .update_plane = drm_atomic_helper_update_plane,
1336 .disable_plane = drm_atomic_helper_disable_plane,
1337 .destroy = vc4_plane_destroy,
1338 .set_property = NULL,
1339 .reset = vc4_plane_reset,
1340 .atomic_duplicate_state = vc4_plane_duplicate_state,
1341 .atomic_destroy_state = vc4_plane_destroy_state,
1342 .format_mod_supported = vc4_format_mod_supported,
1343 };
1344
vc4_plane_init(struct drm_device * dev,enum drm_plane_type type)1345 struct drm_plane *vc4_plane_init(struct drm_device *dev,
1346 enum drm_plane_type type)
1347 {
1348 struct drm_plane *plane = NULL;
1349 struct vc4_plane *vc4_plane;
1350 u32 formats[ARRAY_SIZE(hvs_formats)];
1351 int ret = 0;
1352 unsigned i;
1353 static const uint64_t modifiers[] = {
1354 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1355 DRM_FORMAT_MOD_BROADCOM_SAND128,
1356 DRM_FORMAT_MOD_BROADCOM_SAND64,
1357 DRM_FORMAT_MOD_BROADCOM_SAND256,
1358 DRM_FORMAT_MOD_LINEAR,
1359 DRM_FORMAT_MOD_INVALID
1360 };
1361
1362 vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
1363 GFP_KERNEL);
1364 if (!vc4_plane)
1365 return ERR_PTR(-ENOMEM);
1366
1367 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
1368 formats[i] = hvs_formats[i].drm;
1369
1370 plane = &vc4_plane->base;
1371 ret = drm_universal_plane_init(dev, plane, 0,
1372 &vc4_plane_funcs,
1373 formats, ARRAY_SIZE(formats),
1374 modifiers, type, NULL);
1375 if (ret)
1376 return ERR_PTR(ret);
1377
1378 drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1379
1380 drm_plane_create_alpha_property(plane);
1381 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1382 DRM_MODE_ROTATE_0 |
1383 DRM_MODE_ROTATE_180 |
1384 DRM_MODE_REFLECT_X |
1385 DRM_MODE_REFLECT_Y);
1386
1387 return plane;
1388 }
1389
vc4_plane_create_additional_planes(struct drm_device * drm)1390 int vc4_plane_create_additional_planes(struct drm_device *drm)
1391 {
1392 struct drm_plane *cursor_plane;
1393 struct drm_crtc *crtc;
1394 unsigned int i;
1395
1396 /* Set up some arbitrary number of planes. We're not limited
1397 * by a set number of physical registers, just the space in
1398 * the HVS (16k) and how small an plane can be (28 bytes).
1399 * However, each plane we set up takes up some memory, and
1400 * increases the cost of looping over planes, which atomic
1401 * modesetting does quite a bit. As a result, we pick a
1402 * modest number of planes to expose, that should hopefully
1403 * still cover any sane usecase.
1404 */
1405 for (i = 0; i < 16; i++) {
1406 struct drm_plane *plane =
1407 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1408
1409 if (IS_ERR(plane))
1410 continue;
1411
1412 plane->possible_crtcs =
1413 GENMASK(drm->mode_config.num_crtc - 1, 0);
1414 }
1415
1416 drm_for_each_crtc(crtc, drm) {
1417 /* Set up the legacy cursor after overlay initialization,
1418 * since we overlay planes on the CRTC in the order they were
1419 * initialized.
1420 */
1421 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1422 if (!IS_ERR(cursor_plane)) {
1423 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1424 crtc->cursor = cursor_plane;
1425 }
1426 }
1427
1428 return 0;
1429 }
1430