1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <drm/drm_drv.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_vcn.h"
29 #include "soc15.h"
30 #include "soc15d.h"
31 #include "amdgpu_pm.h"
32 #include "amdgpu_psp.h"
33 #include "mmsch_v2_0.h"
34 #include "vcn_v2_0.h"
35
36 #include "vcn/vcn_2_0_0_offset.h"
37 #include "vcn/vcn_2_0_0_sh_mask.h"
38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39
40 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd
41 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503
42 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504
43 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505
44 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f
45 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a
46 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
47
48 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1
49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6
50 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7
51 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2
52
53 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
54 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
55 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
56 static int vcn_v2_0_set_powergating_state(void *handle,
57 enum amd_powergating_state state);
58 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
59 int inst_idx, struct dpg_pause_state *new_state);
60 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
61 /**
62 * vcn_v2_0_early_init - set function pointers
63 *
64 * @handle: amdgpu_device pointer
65 *
66 * Set ring and irq function pointers
67 */
vcn_v2_0_early_init(void * handle)68 static int vcn_v2_0_early_init(void *handle)
69 {
70 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
71
72 adev->vcn.num_vcn_inst = 1;
73 if (amdgpu_sriov_vf(adev))
74 adev->vcn.num_enc_rings = 1;
75 else
76 adev->vcn.num_enc_rings = 2;
77
78 vcn_v2_0_set_dec_ring_funcs(adev);
79 vcn_v2_0_set_enc_ring_funcs(adev);
80 vcn_v2_0_set_irq_funcs(adev);
81
82 return 0;
83 }
84
85 /**
86 * vcn_v2_0_sw_init - sw init for VCN block
87 *
88 * @handle: amdgpu_device pointer
89 *
90 * Load firmware and sw initialization
91 */
vcn_v2_0_sw_init(void * handle)92 static int vcn_v2_0_sw_init(void *handle)
93 {
94 struct amdgpu_ring *ring;
95 int i, r;
96 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
97 volatile struct amdgpu_fw_shared *fw_shared;
98
99 /* VCN DEC TRAP */
100 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
101 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
102 &adev->vcn.inst->irq);
103 if (r)
104 return r;
105
106 /* VCN ENC TRAP */
107 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
108 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
109 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
110 &adev->vcn.inst->irq);
111 if (r)
112 return r;
113 }
114
115 r = amdgpu_vcn_sw_init(adev);
116 if (r)
117 return r;
118
119 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
120 const struct common_firmware_header *hdr;
121 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
122 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
123 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
124 adev->firmware.fw_size +=
125 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
126 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
127 }
128
129 r = amdgpu_vcn_resume(adev);
130 if (r)
131 return r;
132
133 ring = &adev->vcn.inst->ring_dec;
134
135 ring->use_doorbell = true;
136 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
137
138 sprintf(ring->name, "vcn_dec");
139 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
140 AMDGPU_RING_PRIO_DEFAULT);
141 if (r)
142 return r;
143
144 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
145 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
146 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
147 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
148 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
149 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
150
151 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
152 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
153 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
154 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
155 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
156 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
157 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
158 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
159 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
160 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
161
162 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
163 ring = &adev->vcn.inst->ring_enc[i];
164 ring->use_doorbell = true;
165 if (!amdgpu_sriov_vf(adev))
166 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i;
167 else
168 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i;
169 sprintf(ring->name, "vcn_enc%d", i);
170 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
171 AMDGPU_RING_PRIO_DEFAULT);
172 if (r)
173 return r;
174 }
175
176 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
177
178 r = amdgpu_virt_alloc_mm_table(adev);
179 if (r)
180 return r;
181
182 fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
183 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
184 return 0;
185 }
186
187 /**
188 * vcn_v2_0_sw_fini - sw fini for VCN block
189 *
190 * @handle: amdgpu_device pointer
191 *
192 * VCN suspend and free up sw allocation
193 */
vcn_v2_0_sw_fini(void * handle)194 static int vcn_v2_0_sw_fini(void *handle)
195 {
196 int r, idx;
197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
198 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
199
200 if (drm_dev_enter(&adev->ddev, &idx)) {
201 fw_shared->present_flag_0 = 0;
202 drm_dev_exit(idx);
203 }
204
205 amdgpu_virt_free_mm_table(adev);
206
207 r = amdgpu_vcn_suspend(adev);
208 if (r)
209 return r;
210
211 r = amdgpu_vcn_sw_fini(adev);
212
213 return r;
214 }
215
216 /**
217 * vcn_v2_0_hw_init - start and test VCN block
218 *
219 * @handle: amdgpu_device pointer
220 *
221 * Initialize the hardware, boot up the VCPU and do some testing
222 */
vcn_v2_0_hw_init(void * handle)223 static int vcn_v2_0_hw_init(void *handle)
224 {
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
226 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
227 int i, r;
228
229 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
230 ring->doorbell_index, 0);
231
232 if (amdgpu_sriov_vf(adev))
233 vcn_v2_0_start_sriov(adev);
234
235 r = amdgpu_ring_test_helper(ring);
236 if (r)
237 goto done;
238
239 //Disable vcn decode for sriov
240 if (amdgpu_sriov_vf(adev))
241 ring->sched.ready = false;
242
243 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
244 ring = &adev->vcn.inst->ring_enc[i];
245 r = amdgpu_ring_test_helper(ring);
246 if (r)
247 goto done;
248 }
249
250 done:
251 if (!r)
252 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
253 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
254
255 return r;
256 }
257
258 /**
259 * vcn_v2_0_hw_fini - stop the hardware block
260 *
261 * @handle: amdgpu_device pointer
262 *
263 * Stop the VCN block, mark ring as not ready any more
264 */
vcn_v2_0_hw_fini(void * handle)265 static int vcn_v2_0_hw_fini(void *handle)
266 {
267 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
268
269 cancel_delayed_work_sync(&adev->vcn.idle_work);
270
271 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
272 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
273 RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
274 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
275
276 return 0;
277 }
278
279 /**
280 * vcn_v2_0_suspend - suspend VCN block
281 *
282 * @handle: amdgpu_device pointer
283 *
284 * HW fini and suspend VCN block
285 */
vcn_v2_0_suspend(void * handle)286 static int vcn_v2_0_suspend(void *handle)
287 {
288 int r;
289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
290
291 r = vcn_v2_0_hw_fini(adev);
292 if (r)
293 return r;
294
295 r = amdgpu_vcn_suspend(adev);
296
297 return r;
298 }
299
300 /**
301 * vcn_v2_0_resume - resume VCN block
302 *
303 * @handle: amdgpu_device pointer
304 *
305 * Resume firmware and hw init VCN block
306 */
vcn_v2_0_resume(void * handle)307 static int vcn_v2_0_resume(void *handle)
308 {
309 int r;
310 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
311
312 r = amdgpu_vcn_resume(adev);
313 if (r)
314 return r;
315
316 r = vcn_v2_0_hw_init(adev);
317
318 return r;
319 }
320
321 /**
322 * vcn_v2_0_mc_resume - memory controller programming
323 *
324 * @adev: amdgpu_device pointer
325 *
326 * Let the VCN memory controller know it's offsets
327 */
vcn_v2_0_mc_resume(struct amdgpu_device * adev)328 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
329 {
330 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
331 uint32_t offset;
332
333 if (amdgpu_sriov_vf(adev))
334 return;
335
336 /* cache window 0: fw */
337 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
339 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
340 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
341 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
342 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
343 offset = 0;
344 } else {
345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
346 lower_32_bits(adev->vcn.inst->gpu_addr));
347 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
348 upper_32_bits(adev->vcn.inst->gpu_addr));
349 offset = size;
350 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
351 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
352 }
353
354 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
355
356 /* cache window 1: stack */
357 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
358 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
359 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
360 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
361 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
362 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
363
364 /* cache window 2: context */
365 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
366 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
367 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
368 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
369 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
370 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
371
372 /* non-cache window */
373 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
374 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
375 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
376 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr));
377 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
378 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0,
379 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
380
381 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
382 }
383
vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device * adev,bool indirect)384 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect)
385 {
386 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
387 uint32_t offset;
388
389 /* cache window 0: fw */
390 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
391 if (!indirect) {
392 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
393 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
394 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
395 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
396 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
397 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
398 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
399 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
400 } else {
401 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
402 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
403 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
404 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
405 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
406 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
407 }
408 offset = 0;
409 } else {
410 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
411 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
412 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
413 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
414 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
415 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
416 offset = size;
417 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
418 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
420 }
421
422 if (!indirect)
423 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
424 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
425 else
426 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
427 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
428
429 /* cache window 1: stack */
430 if (!indirect) {
431 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
432 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
433 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
434 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
435 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
436 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
437 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
438 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
439 } else {
440 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
441 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
442 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
443 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
444 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
445 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
446 }
447 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
448 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
449
450 /* cache window 2: context */
451 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
452 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
453 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
454 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
455 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
456 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
458 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
459 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
460 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
461
462 /* non-cache window */
463 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
464 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
465 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
466 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
467 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
468 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect);
469 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
470 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
471 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
472 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0),
473 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
474
475 /* VCN global tiling registers */
476 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
477 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
478 }
479
480 /**
481 * vcn_v2_0_disable_clock_gating - disable VCN clock gating
482 *
483 * @adev: amdgpu_device pointer
484 * @sw: enable SW clock gating
485 *
486 * Disable clock gating for VCN block
487 */
vcn_v2_0_disable_clock_gating(struct amdgpu_device * adev)488 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev)
489 {
490 uint32_t data;
491
492 if (amdgpu_sriov_vf(adev))
493 return;
494
495 /* UVD disable CGC */
496 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
497 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
498 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
499 else
500 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
501 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
502 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
503 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
504
505 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
506 data &= ~(UVD_CGC_GATE__SYS_MASK
507 | UVD_CGC_GATE__UDEC_MASK
508 | UVD_CGC_GATE__MPEG2_MASK
509 | UVD_CGC_GATE__REGS_MASK
510 | UVD_CGC_GATE__RBC_MASK
511 | UVD_CGC_GATE__LMI_MC_MASK
512 | UVD_CGC_GATE__LMI_UMC_MASK
513 | UVD_CGC_GATE__IDCT_MASK
514 | UVD_CGC_GATE__MPRD_MASK
515 | UVD_CGC_GATE__MPC_MASK
516 | UVD_CGC_GATE__LBSI_MASK
517 | UVD_CGC_GATE__LRBBM_MASK
518 | UVD_CGC_GATE__UDEC_RE_MASK
519 | UVD_CGC_GATE__UDEC_CM_MASK
520 | UVD_CGC_GATE__UDEC_IT_MASK
521 | UVD_CGC_GATE__UDEC_DB_MASK
522 | UVD_CGC_GATE__UDEC_MP_MASK
523 | UVD_CGC_GATE__WCB_MASK
524 | UVD_CGC_GATE__VCPU_MASK
525 | UVD_CGC_GATE__SCPU_MASK);
526 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
527
528 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
529 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
530 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
531 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
532 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
533 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
534 | UVD_CGC_CTRL__SYS_MODE_MASK
535 | UVD_CGC_CTRL__UDEC_MODE_MASK
536 | UVD_CGC_CTRL__MPEG2_MODE_MASK
537 | UVD_CGC_CTRL__REGS_MODE_MASK
538 | UVD_CGC_CTRL__RBC_MODE_MASK
539 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
540 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
541 | UVD_CGC_CTRL__IDCT_MODE_MASK
542 | UVD_CGC_CTRL__MPRD_MODE_MASK
543 | UVD_CGC_CTRL__MPC_MODE_MASK
544 | UVD_CGC_CTRL__LBSI_MODE_MASK
545 | UVD_CGC_CTRL__LRBBM_MODE_MASK
546 | UVD_CGC_CTRL__WCB_MODE_MASK
547 | UVD_CGC_CTRL__VCPU_MODE_MASK
548 | UVD_CGC_CTRL__SCPU_MODE_MASK);
549 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
550
551 /* turn on */
552 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
553 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
554 | UVD_SUVD_CGC_GATE__SIT_MASK
555 | UVD_SUVD_CGC_GATE__SMP_MASK
556 | UVD_SUVD_CGC_GATE__SCM_MASK
557 | UVD_SUVD_CGC_GATE__SDB_MASK
558 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
559 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
560 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
561 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
562 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
563 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
564 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
565 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
566 | UVD_SUVD_CGC_GATE__SCLR_MASK
567 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
568 | UVD_SUVD_CGC_GATE__ENT_MASK
569 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
570 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
571 | UVD_SUVD_CGC_GATE__SITE_MASK
572 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
573 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
574 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
575 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
576 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
577 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
578
579 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
580 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
581 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
582 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
583 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
584 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
585 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
586 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
587 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
588 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
589 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
590 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
591 }
592
vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device * adev,uint8_t sram_sel,uint8_t indirect)593 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
594 uint8_t sram_sel, uint8_t indirect)
595 {
596 uint32_t reg_data = 0;
597
598 /* enable sw clock gating control */
599 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
600 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
601 else
602 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
603 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
604 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
605 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
606 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
607 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
608 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
609 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
610 UVD_CGC_CTRL__SYS_MODE_MASK |
611 UVD_CGC_CTRL__UDEC_MODE_MASK |
612 UVD_CGC_CTRL__MPEG2_MODE_MASK |
613 UVD_CGC_CTRL__REGS_MODE_MASK |
614 UVD_CGC_CTRL__RBC_MODE_MASK |
615 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
616 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
617 UVD_CGC_CTRL__IDCT_MODE_MASK |
618 UVD_CGC_CTRL__MPRD_MODE_MASK |
619 UVD_CGC_CTRL__MPC_MODE_MASK |
620 UVD_CGC_CTRL__LBSI_MODE_MASK |
621 UVD_CGC_CTRL__LRBBM_MODE_MASK |
622 UVD_CGC_CTRL__WCB_MODE_MASK |
623 UVD_CGC_CTRL__VCPU_MODE_MASK |
624 UVD_CGC_CTRL__SCPU_MODE_MASK);
625 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
626 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
627
628 /* turn off clock gating */
629 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
630 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
631
632 /* turn on SUVD clock gating */
633 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
634 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
635
636 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
637 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
638 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
639 }
640
641 /**
642 * vcn_v2_0_enable_clock_gating - enable VCN clock gating
643 *
644 * @adev: amdgpu_device pointer
645 * @sw: enable SW clock gating
646 *
647 * Enable clock gating for VCN block
648 */
vcn_v2_0_enable_clock_gating(struct amdgpu_device * adev)649 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev)
650 {
651 uint32_t data = 0;
652
653 if (amdgpu_sriov_vf(adev))
654 return;
655
656 /* enable UVD CGC */
657 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
658 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
659 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
660 else
661 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
662 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
663 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
664 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
665
666 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
667 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
668 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
669 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
670 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
671 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
672 | UVD_CGC_CTRL__SYS_MODE_MASK
673 | UVD_CGC_CTRL__UDEC_MODE_MASK
674 | UVD_CGC_CTRL__MPEG2_MODE_MASK
675 | UVD_CGC_CTRL__REGS_MODE_MASK
676 | UVD_CGC_CTRL__RBC_MODE_MASK
677 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
678 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
679 | UVD_CGC_CTRL__IDCT_MODE_MASK
680 | UVD_CGC_CTRL__MPRD_MODE_MASK
681 | UVD_CGC_CTRL__MPC_MODE_MASK
682 | UVD_CGC_CTRL__LBSI_MODE_MASK
683 | UVD_CGC_CTRL__LRBBM_MODE_MASK
684 | UVD_CGC_CTRL__WCB_MODE_MASK
685 | UVD_CGC_CTRL__VCPU_MODE_MASK
686 | UVD_CGC_CTRL__SCPU_MODE_MASK);
687 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
688
689 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
690 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
691 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
692 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
693 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
694 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
695 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
696 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
697 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
698 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
699 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
700 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
701 }
702
vcn_v2_0_disable_static_power_gating(struct amdgpu_device * adev)703 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
704 {
705 uint32_t data = 0;
706
707 if (amdgpu_sriov_vf(adev))
708 return;
709
710 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
711 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
712 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
713 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
714 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
715 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
716 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
717 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
718 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
719 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
720 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
721
722 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
723 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
724 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF);
725 } else {
726 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
727 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
728 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
729 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
730 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
731 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
732 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
733 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
734 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
735 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
736 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
737 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF);
738 }
739
740 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
741 * UVDU_PWR_STATUS are 0 (power on) */
742
743 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
744 data &= ~0x103;
745 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
746 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
747 UVD_POWER_STATUS__UVD_PG_EN_MASK;
748
749 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
750 }
751
vcn_v2_0_enable_static_power_gating(struct amdgpu_device * adev)752 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
753 {
754 uint32_t data = 0;
755
756 if (amdgpu_sriov_vf(adev))
757 return;
758
759 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
760 /* Before power off, this indicator has to be turned on */
761 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
762 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
763 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
764 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
765
766
767 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
768 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
769 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
770 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
771 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
772 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
773 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
774 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
775 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
776 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
777
778 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
779
780 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
781 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
782 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
783 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
784 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
785 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
786 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
787 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
788 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
789 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
790 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF);
791 }
792 }
793
vcn_v2_0_start_dpg_mode(struct amdgpu_device * adev,bool indirect)794 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
795 {
796 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
797 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
798 uint32_t rb_bufsz, tmp;
799
800 vcn_v2_0_enable_static_power_gating(adev);
801
802 /* enable dynamic power gating mode */
803 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
804 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
805 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
806 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
807
808 if (indirect)
809 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr;
810
811 /* enable clock gating */
812 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect);
813
814 /* enable VCPU clock */
815 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
816 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
817 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
818 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
819 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
820
821 /* disable master interupt */
822 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
823 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
824
825 /* setup mmUVD_LMI_CTRL */
826 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
827 UVD_LMI_CTRL__REQ_MODE_MASK |
828 UVD_LMI_CTRL__CRC_RESET_MASK |
829 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
830 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
831 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
832 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
833 0x00100000L);
834 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
835 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
836
837 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
838 UVD, 0, mmUVD_MPC_CNTL),
839 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
840
841 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
842 UVD, 0, mmUVD_MPC_SET_MUXA0),
843 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
844 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
845 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
846 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
847
848 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
849 UVD, 0, mmUVD_MPC_SET_MUXB0),
850 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
851 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
852 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
853 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
854
855 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
856 UVD, 0, mmUVD_MPC_SET_MUX),
857 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
858 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
859 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
860
861 vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
862
863 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
864 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
865 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
866 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
867
868 /* release VCPU reset to boot */
869 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
870 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
871
872 /* enable LMI MC and UMC channels */
873 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
874 UVD, 0, mmUVD_LMI_CTRL2),
875 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
876
877 /* enable master interrupt */
878 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
879 UVD, 0, mmUVD_MASTINT_EN),
880 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
881
882 if (indirect)
883 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr,
884 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr -
885 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr));
886
887 /* force RBC into idle state */
888 rb_bufsz = order_base_2(ring->ring_size);
889 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
890 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
891 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
892 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
893 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
894 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
895
896 /* Stall DPG before WPTR/RPTR reset */
897 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
898 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
899 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
900 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
901
902 /* set the write pointer delay */
903 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
904
905 /* set the wb address */
906 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
907 (upper_32_bits(ring->gpu_addr) >> 2));
908
909 /* program the RB_BASE for ring buffer */
910 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
911 lower_32_bits(ring->gpu_addr));
912 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
913 upper_32_bits(ring->gpu_addr));
914
915 /* Initialize the ring buffer's read and write pointers */
916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
917
918 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
919
920 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
921 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
922 lower_32_bits(ring->wptr));
923
924 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
925 /* Unstall DPG */
926 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
927 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
928 return 0;
929 }
930
vcn_v2_0_start(struct amdgpu_device * adev)931 static int vcn_v2_0_start(struct amdgpu_device *adev)
932 {
933 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
934 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
935 uint32_t rb_bufsz, tmp;
936 uint32_t lmi_swap_cntl;
937 int i, j, r;
938
939 if (adev->pm.dpm_enabled)
940 amdgpu_dpm_enable_uvd(adev, true);
941
942 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
943 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
944
945 vcn_v2_0_disable_static_power_gating(adev);
946
947 /* set uvd status busy */
948 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
949 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
950
951 /*SW clock gating */
952 vcn_v2_0_disable_clock_gating(adev);
953
954 /* enable VCPU clock */
955 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL),
956 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
957
958 /* disable master interrupt */
959 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
960 ~UVD_MASTINT_EN__VCPU_EN_MASK);
961
962 /* setup mmUVD_LMI_CTRL */
963 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
964 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
965 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
966 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
967 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
968 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
969
970 /* setup mmUVD_MPC_CNTL */
971 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
972 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
973 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
974 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp);
975
976 /* setup UVD_MPC_SET_MUXA0 */
977 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
978 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
979 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
980 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
981 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
982
983 /* setup UVD_MPC_SET_MUXB0 */
984 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
985 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
986 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
987 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
988 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
989
990 /* setup mmUVD_MPC_SET_MUX */
991 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
992 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
993 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
994 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
995
996 vcn_v2_0_mc_resume(adev);
997
998 /* release VCPU reset to boot */
999 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1000 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1001
1002 /* enable LMI MC and UMC channels */
1003 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
1004 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1005
1006 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET);
1007 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1008 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1009 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp);
1010
1011 /* disable byte swapping */
1012 lmi_swap_cntl = 0;
1013 #ifdef __BIG_ENDIAN
1014 /* swap (8 in 32) RB and IB */
1015 lmi_swap_cntl = 0xa;
1016 #endif
1017 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
1018
1019 for (i = 0; i < 10; ++i) {
1020 uint32_t status;
1021
1022 for (j = 0; j < 100; ++j) {
1023 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
1024 if (status & 2)
1025 break;
1026 mdelay(10);
1027 }
1028 r = 0;
1029 if (status & 2)
1030 break;
1031
1032 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
1033 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1034 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1035 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1036 mdelay(10);
1037 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
1038 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1039 mdelay(10);
1040 r = -1;
1041 }
1042
1043 if (r) {
1044 DRM_ERROR("VCN decode not responding, giving up!!!\n");
1045 return r;
1046 }
1047
1048 /* enable master interrupt */
1049 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
1050 UVD_MASTINT_EN__VCPU_EN_MASK,
1051 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1052
1053 /* clear the busy bit of VCN_STATUS */
1054 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
1055 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1056
1057 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0);
1058
1059 /* force RBC into idle state */
1060 rb_bufsz = order_base_2(ring->ring_size);
1061 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1062 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1063 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1064 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1065 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1066 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1067
1068 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1069 /* program the RB_BASE for ring buffer */
1070 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1071 lower_32_bits(ring->gpu_addr));
1072 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1073 upper_32_bits(ring->gpu_addr));
1074
1075 /* Initialize the ring buffer's read and write pointers */
1076 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1077
1078 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1079 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1080 lower_32_bits(ring->wptr));
1081 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1082
1083 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1084 ring = &adev->vcn.inst->ring_enc[0];
1085 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1086 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1087 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1088 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1089 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1090 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1091
1092 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1093 ring = &adev->vcn.inst->ring_enc[1];
1094 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1095 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1096 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1097 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1098 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1099 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1100
1101 return 0;
1102 }
1103
vcn_v2_0_stop_dpg_mode(struct amdgpu_device * adev)1104 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)
1105 {
1106 uint32_t tmp;
1107
1108 /* Wait for power status to be 1 */
1109 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1110 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1111
1112 /* wait for read ptr to be equal to write ptr */
1113 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1114 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1115
1116 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1117 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1118
1119 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1120 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1121
1122 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
1123 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1124
1125 /* disable dynamic power gating mode */
1126 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1127 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1128
1129 return 0;
1130 }
1131
vcn_v2_0_stop(struct amdgpu_device * adev)1132 static int vcn_v2_0_stop(struct amdgpu_device *adev)
1133 {
1134 uint32_t tmp;
1135 int r;
1136
1137 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1138 r = vcn_v2_0_stop_dpg_mode(adev);
1139 if (r)
1140 return r;
1141 goto power_off;
1142 }
1143
1144 /* wait for uvd idle */
1145 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1146 if (r)
1147 return r;
1148
1149 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1150 UVD_LMI_STATUS__READ_CLEAN_MASK |
1151 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1152 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1153 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1154 if (r)
1155 return r;
1156
1157 /* stall UMC channel */
1158 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2);
1159 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1160 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp);
1161
1162 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1163 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1164 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp);
1165 if (r)
1166 return r;
1167
1168 /* disable VCPU clock */
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1170 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1171
1172 /* reset LMI UMC */
1173 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1174 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1175 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1176
1177 /* reset LMI */
1178 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1179 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1180 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1181
1182 /* reset VCPU */
1183 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1184 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1185 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1186
1187 /* clear status */
1188 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
1189
1190 vcn_v2_0_enable_clock_gating(adev);
1191 vcn_v2_0_enable_static_power_gating(adev);
1192
1193 power_off:
1194 if (adev->pm.dpm_enabled)
1195 amdgpu_dpm_enable_uvd(adev, false);
1196
1197 return 0;
1198 }
1199
vcn_v2_0_pause_dpg_mode(struct amdgpu_device * adev,int inst_idx,struct dpg_pause_state * new_state)1200 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
1201 int inst_idx, struct dpg_pause_state *new_state)
1202 {
1203 struct amdgpu_ring *ring;
1204 uint32_t reg_data = 0;
1205 int ret_code;
1206
1207 /* pause/unpause if state is changed */
1208 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1209 DRM_DEBUG("dpg pause state changed %d -> %d",
1210 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1211 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1212 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1213
1214 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1215 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
1216 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1217
1218 if (!ret_code) {
1219 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr;
1220 /* pause DPG */
1221 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1222 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1223
1224 /* wait for ACK */
1225 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1226 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1227 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1228
1229 /* Stall DPG before WPTR/RPTR reset */
1230 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1231 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1232 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1233 /* Restore */
1234 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1235 ring = &adev->vcn.inst->ring_enc[0];
1236 ring->wptr = 0;
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1238 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1240 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1241 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1242 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1243
1244 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1245 ring = &adev->vcn.inst->ring_enc[1];
1246 ring->wptr = 0;
1247 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1250 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1251 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1252 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1253
1254 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1255 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1256 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1257 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1258 /* Unstall DPG */
1259 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
1260 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1261
1262 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1263 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1264 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1265 }
1266 } else {
1267 /* unpause dpg, no need to wait */
1268 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1269 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1270 }
1271 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1272 }
1273
1274 return 0;
1275 }
1276
vcn_v2_0_is_idle(void * handle)1277 static bool vcn_v2_0_is_idle(void *handle)
1278 {
1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1282 }
1283
vcn_v2_0_wait_for_idle(void * handle)1284 static int vcn_v2_0_wait_for_idle(void *handle)
1285 {
1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1287 int ret;
1288
1289 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1290 UVD_STATUS__IDLE);
1291
1292 return ret;
1293 }
1294
vcn_v2_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1295 static int vcn_v2_0_set_clockgating_state(void *handle,
1296 enum amd_clockgating_state state)
1297 {
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299 bool enable = (state == AMD_CG_STATE_GATE);
1300
1301 if (amdgpu_sriov_vf(adev))
1302 return 0;
1303
1304 if (enable) {
1305 /* wait for STATUS to clear */
1306 if (!vcn_v2_0_is_idle(handle))
1307 return -EBUSY;
1308 vcn_v2_0_enable_clock_gating(adev);
1309 } else {
1310 /* disable HW gating and enable Sw gating */
1311 vcn_v2_0_disable_clock_gating(adev);
1312 }
1313 return 0;
1314 }
1315
1316 /**
1317 * vcn_v2_0_dec_ring_get_rptr - get read pointer
1318 *
1319 * @ring: amdgpu_ring pointer
1320 *
1321 * Returns the current hardware read pointer
1322 */
vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring * ring)1323 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1324 {
1325 struct amdgpu_device *adev = ring->adev;
1326
1327 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1328 }
1329
1330 /**
1331 * vcn_v2_0_dec_ring_get_wptr - get write pointer
1332 *
1333 * @ring: amdgpu_ring pointer
1334 *
1335 * Returns the current hardware write pointer
1336 */
vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring * ring)1337 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1338 {
1339 struct amdgpu_device *adev = ring->adev;
1340
1341 if (ring->use_doorbell)
1342 return adev->wb.wb[ring->wptr_offs];
1343 else
1344 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1345 }
1346
1347 /**
1348 * vcn_v2_0_dec_ring_set_wptr - set write pointer
1349 *
1350 * @ring: amdgpu_ring pointer
1351 *
1352 * Commits the write pointer to the hardware
1353 */
vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring * ring)1354 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1355 {
1356 struct amdgpu_device *adev = ring->adev;
1357
1358 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1359 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1360 lower_32_bits(ring->wptr) | 0x80000000);
1361
1362 if (ring->use_doorbell) {
1363 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1364 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1365 } else {
1366 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1367 }
1368 }
1369
1370 /**
1371 * vcn_v2_0_dec_ring_insert_start - insert a start command
1372 *
1373 * @ring: amdgpu_ring pointer
1374 *
1375 * Write a start command to the ring.
1376 */
vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring * ring)1377 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1378 {
1379 struct amdgpu_device *adev = ring->adev;
1380
1381 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1382 amdgpu_ring_write(ring, 0);
1383 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1384 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1385 }
1386
1387 /**
1388 * vcn_v2_0_dec_ring_insert_end - insert a end command
1389 *
1390 * @ring: amdgpu_ring pointer
1391 *
1392 * Write a end command to the ring.
1393 */
vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring * ring)1394 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1395 {
1396 struct amdgpu_device *adev = ring->adev;
1397
1398 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1399 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1400 }
1401
1402 /**
1403 * vcn_v2_0_dec_ring_insert_nop - insert a nop command
1404 *
1405 * @ring: amdgpu_ring pointer
1406 *
1407 * Write a nop command to the ring.
1408 */
vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)1409 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1410 {
1411 struct amdgpu_device *adev = ring->adev;
1412 int i;
1413
1414 WARN_ON(ring->wptr % 2 || count % 2);
1415
1416 for (i = 0; i < count / 2; i++) {
1417 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1418 amdgpu_ring_write(ring, 0);
1419 }
1420 }
1421
1422 /**
1423 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command
1424 *
1425 * @ring: amdgpu_ring pointer
1426 * @fence: fence to emit
1427 *
1428 * Write a fence and a trap command to the ring.
1429 */
vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1430 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1431 unsigned flags)
1432 {
1433 struct amdgpu_device *adev = ring->adev;
1434
1435 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1436 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1437 amdgpu_ring_write(ring, seq);
1438
1439 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1440 amdgpu_ring_write(ring, addr & 0xffffffff);
1441
1442 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1443 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1444
1445 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1446 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1));
1447
1448 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1449 amdgpu_ring_write(ring, 0);
1450
1451 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1452 amdgpu_ring_write(ring, 0);
1453
1454 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1455
1456 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1));
1457 }
1458
1459 /**
1460 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer
1461 *
1462 * @ring: amdgpu_ring pointer
1463 * @ib: indirect buffer to execute
1464 *
1465 * Write ring commands to execute the indirect buffer
1466 */
vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1467 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1468 struct amdgpu_job *job,
1469 struct amdgpu_ib *ib,
1470 uint32_t flags)
1471 {
1472 struct amdgpu_device *adev = ring->adev;
1473 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1474
1475 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0));
1476 amdgpu_ring_write(ring, vmid);
1477
1478 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0));
1479 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1480 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0));
1481 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1482 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0));
1483 amdgpu_ring_write(ring, ib->length_dw);
1484 }
1485
vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1486 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1487 uint32_t val, uint32_t mask)
1488 {
1489 struct amdgpu_device *adev = ring->adev;
1490
1491 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1492 amdgpu_ring_write(ring, reg << 2);
1493
1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1495 amdgpu_ring_write(ring, val);
1496
1497 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0));
1498 amdgpu_ring_write(ring, mask);
1499
1500 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1501
1502 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1));
1503 }
1504
vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1505 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1506 unsigned vmid, uint64_t pd_addr)
1507 {
1508 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1509 uint32_t data0, data1, mask;
1510
1511 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1512
1513 /* wait for register write */
1514 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1515 data1 = lower_32_bits(pd_addr);
1516 mask = 0xffffffff;
1517 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1518 }
1519
vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1520 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1521 uint32_t reg, uint32_t val)
1522 {
1523 struct amdgpu_device *adev = ring->adev;
1524
1525 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1526 amdgpu_ring_write(ring, reg << 2);
1527
1528 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1529 amdgpu_ring_write(ring, val);
1530
1531 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1532
1533 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1));
1534 }
1535
1536 /**
1537 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer
1538 *
1539 * @ring: amdgpu_ring pointer
1540 *
1541 * Returns the current hardware enc read pointer
1542 */
vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring * ring)1543 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1544 {
1545 struct amdgpu_device *adev = ring->adev;
1546
1547 if (ring == &adev->vcn.inst->ring_enc[0])
1548 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1549 else
1550 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1551 }
1552
1553 /**
1554 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer
1555 *
1556 * @ring: amdgpu_ring pointer
1557 *
1558 * Returns the current hardware enc write pointer
1559 */
vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring * ring)1560 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1561 {
1562 struct amdgpu_device *adev = ring->adev;
1563
1564 if (ring == &adev->vcn.inst->ring_enc[0]) {
1565 if (ring->use_doorbell)
1566 return adev->wb.wb[ring->wptr_offs];
1567 else
1568 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1569 } else {
1570 if (ring->use_doorbell)
1571 return adev->wb.wb[ring->wptr_offs];
1572 else
1573 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1574 }
1575 }
1576
1577 /**
1578 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer
1579 *
1580 * @ring: amdgpu_ring pointer
1581 *
1582 * Commits the enc write pointer to the hardware
1583 */
vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring * ring)1584 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1585 {
1586 struct amdgpu_device *adev = ring->adev;
1587
1588 if (ring == &adev->vcn.inst->ring_enc[0]) {
1589 if (ring->use_doorbell) {
1590 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1591 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1592 } else {
1593 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1594 }
1595 } else {
1596 if (ring->use_doorbell) {
1597 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1598 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1599 } else {
1600 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1601 }
1602 }
1603 }
1604
1605 /**
1606 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command
1607 *
1608 * @ring: amdgpu_ring pointer
1609 * @fence: fence to emit
1610 *
1611 * Write enc a fence and a trap command to the ring.
1612 */
vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)1613 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1614 u64 seq, unsigned flags)
1615 {
1616 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1617
1618 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1619 amdgpu_ring_write(ring, addr);
1620 amdgpu_ring_write(ring, upper_32_bits(addr));
1621 amdgpu_ring_write(ring, seq);
1622 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1623 }
1624
vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring * ring)1625 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1626 {
1627 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1628 }
1629
1630 /**
1631 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer
1632 *
1633 * @ring: amdgpu_ring pointer
1634 * @ib: indirect buffer to execute
1635 *
1636 * Write enc ring commands to execute the indirect buffer
1637 */
vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)1638 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1639 struct amdgpu_job *job,
1640 struct amdgpu_ib *ib,
1641 uint32_t flags)
1642 {
1643 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1644
1645 amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1646 amdgpu_ring_write(ring, vmid);
1647 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1648 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1649 amdgpu_ring_write(ring, ib->length_dw);
1650 }
1651
vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1652 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1653 uint32_t val, uint32_t mask)
1654 {
1655 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1656 amdgpu_ring_write(ring, reg << 2);
1657 amdgpu_ring_write(ring, mask);
1658 amdgpu_ring_write(ring, val);
1659 }
1660
vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)1661 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1662 unsigned int vmid, uint64_t pd_addr)
1663 {
1664 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1665
1666 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1667
1668 /* wait for reg writes */
1669 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1670 vmid * hub->ctx_addr_distance,
1671 lower_32_bits(pd_addr), 0xffffffff);
1672 }
1673
vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1674 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1675 {
1676 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1677 amdgpu_ring_write(ring, reg << 2);
1678 amdgpu_ring_write(ring, val);
1679 }
1680
vcn_v2_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1681 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev,
1682 struct amdgpu_irq_src *source,
1683 unsigned type,
1684 enum amdgpu_interrupt_state state)
1685 {
1686 return 0;
1687 }
1688
vcn_v2_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1689 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
1690 struct amdgpu_irq_src *source,
1691 struct amdgpu_iv_entry *entry)
1692 {
1693 DRM_DEBUG("IH: VCN TRAP\n");
1694
1695 switch (entry->src_id) {
1696 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
1697 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1698 break;
1699 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1700 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1701 break;
1702 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
1703 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1704 break;
1705 default:
1706 DRM_ERROR("Unhandled interrupt: %d %d\n",
1707 entry->src_id, entry->src_data[0]);
1708 break;
1709 }
1710
1711 return 0;
1712 }
1713
vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring * ring)1714 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
1715 {
1716 struct amdgpu_device *adev = ring->adev;
1717 uint32_t tmp = 0;
1718 unsigned i;
1719 int r;
1720
1721 if (amdgpu_sriov_vf(adev))
1722 return 0;
1723
1724 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
1725 r = amdgpu_ring_alloc(ring, 4);
1726 if (r)
1727 return r;
1728 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1729 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1730 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
1731 amdgpu_ring_write(ring, 0xDEADBEEF);
1732 amdgpu_ring_commit(ring);
1733 for (i = 0; i < adev->usec_timeout; i++) {
1734 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
1735 if (tmp == 0xDEADBEEF)
1736 break;
1737 udelay(1);
1738 }
1739
1740 if (i >= adev->usec_timeout)
1741 r = -ETIMEDOUT;
1742
1743 return r;
1744 }
1745
1746
vcn_v2_0_set_powergating_state(void * handle,enum amd_powergating_state state)1747 static int vcn_v2_0_set_powergating_state(void *handle,
1748 enum amd_powergating_state state)
1749 {
1750 /* This doesn't actually powergate the VCN block.
1751 * That's done in the dpm code via the SMC. This
1752 * just re-inits the block as necessary. The actual
1753 * gating still happens in the dpm code. We should
1754 * revisit this when there is a cleaner line between
1755 * the smc and the hw blocks
1756 */
1757 int ret;
1758 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1759
1760 if (amdgpu_sriov_vf(adev)) {
1761 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1762 return 0;
1763 }
1764
1765 if (state == adev->vcn.cur_state)
1766 return 0;
1767
1768 if (state == AMD_PG_STATE_GATE)
1769 ret = vcn_v2_0_stop(adev);
1770 else
1771 ret = vcn_v2_0_start(adev);
1772
1773 if (!ret)
1774 adev->vcn.cur_state = state;
1775 return ret;
1776 }
1777
vcn_v2_0_start_mmsch(struct amdgpu_device * adev,struct amdgpu_mm_table * table)1778 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev,
1779 struct amdgpu_mm_table *table)
1780 {
1781 uint32_t data = 0, loop;
1782 uint64_t addr = table->gpu_addr;
1783 struct mmsch_v2_0_init_header *header;
1784 uint32_t size;
1785 int i;
1786
1787 header = (struct mmsch_v2_0_init_header *)table->cpu_addr;
1788 size = header->header_size + header->vcn_table_size;
1789
1790 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1791 * of memory descriptor location
1792 */
1793 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
1794 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
1795
1796 /* 2, update vmid of descriptor */
1797 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID);
1798 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1799 /* use domain0 for MM scheduler */
1800 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1801 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data);
1802
1803 /* 3, notify mmsch about the size of this descriptor */
1804 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size);
1805
1806 /* 4, set resp to zero */
1807 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1808
1809 adev->vcn.inst->ring_dec.wptr = 0;
1810 adev->vcn.inst->ring_dec.wptr_old = 0;
1811 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec);
1812
1813 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1814 adev->vcn.inst->ring_enc[i].wptr = 0;
1815 adev->vcn.inst->ring_enc[i].wptr_old = 0;
1816 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]);
1817 }
1818
1819 /* 5, kick off the initialization and wait until
1820 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1821 */
1822 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001);
1823
1824 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1825 loop = 1000;
1826 while ((data & 0x10000002) != 0x10000002) {
1827 udelay(10);
1828 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP);
1829 loop--;
1830 if (!loop)
1831 break;
1832 }
1833
1834 if (!loop) {
1835 DRM_ERROR("failed to init MMSCH, " \
1836 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data);
1837 return -EBUSY;
1838 }
1839
1840 return 0;
1841 }
1842
vcn_v2_0_start_sriov(struct amdgpu_device * adev)1843 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
1844 {
1845 int r;
1846 uint32_t tmp;
1847 struct amdgpu_ring *ring;
1848 uint32_t offset, size;
1849 uint32_t table_size = 0;
1850 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} };
1851 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
1852 struct mmsch_v2_0_cmd_end end = { {0} };
1853 struct mmsch_v2_0_init_header *header;
1854 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1855 uint8_t i = 0;
1856
1857 header = (struct mmsch_v2_0_init_header *)init_table;
1858 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1859 direct_rd_mod_wt.cmd_header.command_type =
1860 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1861 end.cmd_header.command_type = MMSCH_COMMAND__END;
1862
1863 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) {
1864 header->version = MMSCH_VERSION;
1865 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2;
1866
1867 header->vcn_table_offset = header->header_size;
1868
1869 init_table += header->vcn_table_offset;
1870
1871 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1872
1873 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT(
1874 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
1875 0xFFFFFFFF, 0x00000004);
1876
1877 /* mc resume*/
1878 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1879 tmp = AMDGPU_UCODE_ID_VCN;
1880 MMSCH_V2_0_INSERT_DIRECT_WT(
1881 SOC15_REG_OFFSET(UVD, i,
1882 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1883 adev->firmware.ucode[tmp].tmr_mc_addr_lo);
1884 MMSCH_V2_0_INSERT_DIRECT_WT(
1885 SOC15_REG_OFFSET(UVD, i,
1886 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1887 adev->firmware.ucode[tmp].tmr_mc_addr_hi);
1888 offset = 0;
1889 } else {
1890 MMSCH_V2_0_INSERT_DIRECT_WT(
1891 SOC15_REG_OFFSET(UVD, i,
1892 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1893 lower_32_bits(adev->vcn.inst->gpu_addr));
1894 MMSCH_V2_0_INSERT_DIRECT_WT(
1895 SOC15_REG_OFFSET(UVD, i,
1896 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1897 upper_32_bits(adev->vcn.inst->gpu_addr));
1898 offset = size;
1899 }
1900
1901 MMSCH_V2_0_INSERT_DIRECT_WT(
1902 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
1903 0);
1904 MMSCH_V2_0_INSERT_DIRECT_WT(
1905 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0),
1906 size);
1907
1908 MMSCH_V2_0_INSERT_DIRECT_WT(
1909 SOC15_REG_OFFSET(UVD, i,
1910 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1911 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
1912 MMSCH_V2_0_INSERT_DIRECT_WT(
1913 SOC15_REG_OFFSET(UVD, i,
1914 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1915 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
1916 MMSCH_V2_0_INSERT_DIRECT_WT(
1917 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1),
1918 0);
1919 MMSCH_V2_0_INSERT_DIRECT_WT(
1920 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1),
1921 AMDGPU_VCN_STACK_SIZE);
1922
1923 MMSCH_V2_0_INSERT_DIRECT_WT(
1924 SOC15_REG_OFFSET(UVD, i,
1925 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1926 lower_32_bits(adev->vcn.inst->gpu_addr + offset +
1927 AMDGPU_VCN_STACK_SIZE));
1928 MMSCH_V2_0_INSERT_DIRECT_WT(
1929 SOC15_REG_OFFSET(UVD, i,
1930 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1931 upper_32_bits(adev->vcn.inst->gpu_addr + offset +
1932 AMDGPU_VCN_STACK_SIZE));
1933 MMSCH_V2_0_INSERT_DIRECT_WT(
1934 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2),
1935 0);
1936 MMSCH_V2_0_INSERT_DIRECT_WT(
1937 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
1938 AMDGPU_VCN_CONTEXT_SIZE);
1939
1940 for (r = 0; r < adev->vcn.num_enc_rings; ++r) {
1941 ring = &adev->vcn.inst->ring_enc[r];
1942 ring->wptr = 0;
1943 MMSCH_V2_0_INSERT_DIRECT_WT(
1944 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO),
1945 lower_32_bits(ring->gpu_addr));
1946 MMSCH_V2_0_INSERT_DIRECT_WT(
1947 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI),
1948 upper_32_bits(ring->gpu_addr));
1949 MMSCH_V2_0_INSERT_DIRECT_WT(
1950 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE),
1951 ring->ring_size / 4);
1952 }
1953
1954 ring = &adev->vcn.inst->ring_dec;
1955 ring->wptr = 0;
1956 MMSCH_V2_0_INSERT_DIRECT_WT(
1957 SOC15_REG_OFFSET(UVD, i,
1958 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1959 lower_32_bits(ring->gpu_addr));
1960 MMSCH_V2_0_INSERT_DIRECT_WT(
1961 SOC15_REG_OFFSET(UVD, i,
1962 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1963 upper_32_bits(ring->gpu_addr));
1964 /* force RBC into idle state */
1965 tmp = order_base_2(ring->ring_size);
1966 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1967 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1968 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1969 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1970 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1971 MMSCH_V2_0_INSERT_DIRECT_WT(
1972 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
1973
1974 /* add end packet */
1975 tmp = sizeof(struct mmsch_v2_0_cmd_end);
1976 memcpy((void *)init_table, &end, tmp);
1977 table_size += (tmp / 4);
1978 header->vcn_table_size = table_size;
1979
1980 }
1981 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
1982 }
1983
1984 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
1985 .name = "vcn_v2_0",
1986 .early_init = vcn_v2_0_early_init,
1987 .late_init = NULL,
1988 .sw_init = vcn_v2_0_sw_init,
1989 .sw_fini = vcn_v2_0_sw_fini,
1990 .hw_init = vcn_v2_0_hw_init,
1991 .hw_fini = vcn_v2_0_hw_fini,
1992 .suspend = vcn_v2_0_suspend,
1993 .resume = vcn_v2_0_resume,
1994 .is_idle = vcn_v2_0_is_idle,
1995 .wait_for_idle = vcn_v2_0_wait_for_idle,
1996 .check_soft_reset = NULL,
1997 .pre_soft_reset = NULL,
1998 .soft_reset = NULL,
1999 .post_soft_reset = NULL,
2000 .set_clockgating_state = vcn_v2_0_set_clockgating_state,
2001 .set_powergating_state = vcn_v2_0_set_powergating_state,
2002 };
2003
2004 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
2005 .type = AMDGPU_RING_TYPE_VCN_DEC,
2006 .align_mask = 0xf,
2007 .vmhub = AMDGPU_MMHUB_0,
2008 .get_rptr = vcn_v2_0_dec_ring_get_rptr,
2009 .get_wptr = vcn_v2_0_dec_ring_get_wptr,
2010 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2011 .emit_frame_size =
2012 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
2013 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
2014 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
2015 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
2016 6,
2017 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
2018 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
2019 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
2020 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
2021 .test_ring = vcn_v2_0_dec_ring_test_ring,
2022 .test_ib = amdgpu_vcn_dec_ring_test_ib,
2023 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
2024 .insert_start = vcn_v2_0_dec_ring_insert_start,
2025 .insert_end = vcn_v2_0_dec_ring_insert_end,
2026 .pad_ib = amdgpu_ring_generic_pad_ib,
2027 .begin_use = amdgpu_vcn_ring_begin_use,
2028 .end_use = amdgpu_vcn_ring_end_use,
2029 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2030 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2031 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2032 };
2033
2034 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = {
2035 .type = AMDGPU_RING_TYPE_VCN_ENC,
2036 .align_mask = 0x3f,
2037 .nop = VCN_ENC_CMD_NO_OP,
2038 .vmhub = AMDGPU_MMHUB_0,
2039 .get_rptr = vcn_v2_0_enc_ring_get_rptr,
2040 .get_wptr = vcn_v2_0_enc_ring_get_wptr,
2041 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
2042 .emit_frame_size =
2043 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2044 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2045 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2046 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2047 1, /* vcn_v2_0_enc_ring_insert_end */
2048 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2049 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2050 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2051 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2052 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2053 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2054 .insert_nop = amdgpu_ring_insert_nop,
2055 .insert_end = vcn_v2_0_enc_ring_insert_end,
2056 .pad_ib = amdgpu_ring_generic_pad_ib,
2057 .begin_use = amdgpu_vcn_ring_begin_use,
2058 .end_use = amdgpu_vcn_ring_end_use,
2059 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2060 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2061 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2062 };
2063
vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device * adev)2064 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2065 {
2066 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs;
2067 DRM_INFO("VCN decode is enabled in VM mode\n");
2068 }
2069
vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device * adev)2070 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2071 {
2072 int i;
2073
2074 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
2075 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs;
2076
2077 DRM_INFO("VCN encode is enabled in VM mode\n");
2078 }
2079
2080 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = {
2081 .set = vcn_v2_0_set_interrupt_state,
2082 .process = vcn_v2_0_process_interrupt,
2083 };
2084
vcn_v2_0_set_irq_funcs(struct amdgpu_device * adev)2085 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev)
2086 {
2087 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1;
2088 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs;
2089 }
2090
2091 const struct amdgpu_ip_block_version vcn_v2_0_ip_block =
2092 {
2093 .type = AMD_IP_BLOCK_TYPE_VCN,
2094 .major = 2,
2095 .minor = 0,
2096 .rev = 0,
2097 .funcs = &vcn_v2_0_ip_funcs,
2098 };
2099