1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef _DRM_HAL_COMMON_H__ 20 #define _DRM_HAL_COMMON_H__ 21 22 #ifdef __cplusplus 23 #if __cplusplus 24 extern "C"{ 25 #endif 26 #endif /* __cplusplus */ 27 28 #define drm_hal_print(level, fmt...) do { \ 29 printk("[DRM-HAL][%s][%s][%u] ", level, __FUNCTION__, __LINE__); \ 30 printk(fmt); \ 31 } while (0) 32 33 /* DRM HAL log system */ 34 #define drm_hal_err(fmt...) drm_hal_print("ERROR", fmt) 35 #define drm_hal_warn(fmt...) drm_hal_print("WARN", fmt) 36 #define drm_hal_info(fmt...) drm_hal_print("INFO", fmt) 37 38 /* define the display channel enum */ 39 enum drm_hal_disp_chn { 40 DRM_HAL_DISP_0, 41 DRM_HAL_DISP_1, 42 DRM_HAL_DISP_MAX 43 }; 44 45 /* define the hdmitx channel enum */ 46 enum drm_hal_hdmitx_id { 47 DRM_HAL_HDMITX_0, 48 DRM_HAL_HDMITX_1, 49 DRM_HAL_HDMITX_MAX 50 }; 51 52 /* define the graphics layer enum */ 53 enum drm_hal_gfx_layer { 54 DRM_HAL_GFX_G0, 55 DRM_HAL_GFX_G1, 56 DRM_HAL_GFX_G2, 57 DRM_HAL_GFX_G3, 58 DRM_HAL_GFX_MAX 59 }; 60 61 /* define the color format enum */ 62 enum drm_hal_color_fmt { 63 DRM_HAL_FMT_RGB565 = 0, /* RGB565 16bpp */ 64 DRM_HAL_FMT_RGB888, /* RGB888 24bpp */ 65 DRM_HAL_FMT_KRGB444, /* RGB444 16bpp */ 66 DRM_HAL_FMT_KRGB555, /* RGB555 16bpp */ 67 68 DRM_HAL_FMT_KRGB888, /* RGB888 32bpp */ 69 DRM_HAL_FMT_ARGB4444, /* ARGB4444 */ 70 DRM_HAL_FMT_ARGB1555, /* ARGB1555 */ 71 DRM_HAL_FMT_ARGB8888, /* ARGB8888 */ 72 73 DRM_HAL_FMT_ARGB8565, /* ARGB8565 */ 74 DRM_HAL_FMT_RGBA4444, /* ARGB4444 */ 75 DRM_HAL_FMT_RGBA5551, /* RGBA5551 */ 76 DRM_HAL_FMT_RGBA5658, /* RGBA5658 */ 77 78 DRM_HAL_FMT_RGBA8888, /* RGBA8888 */ 79 DRM_HAL_FMT_BGR565, /* BGR565 */ 80 DRM_HAL_FMT_BGR888, /* BGR888 */ 81 DRM_HAL_FMT_ABGR4444, /* ABGR4444 */ 82 83 DRM_HAL_FMT_ABGR1555, /* ABGR1555 */ 84 DRM_HAL_FMT_ABGR8888, /* ABGR8888 */ 85 DRM_HAL_FMT_ABGR8565, /* ABGR8565 */ 86 DRM_HAL_FMT_KBGR444, /* BGR444 16bpp */ 87 88 DRM_HAL_FMT_KBGR555, /* BGR555 16bpp */ 89 DRM_HAL_FMT_KBGR888, /* BGR888 32bpp */ 90 DRM_HAL_FMT_1BPP, /* clut1 */ 91 DRM_HAL_FMT_2BPP, /* clut2 */ 92 93 DRM_HAL_FMT_MAX 94 }; 95 96 /* define the display rect struct */ 97 struct drm_hal_rect { 98 int x; 99 int y; 100 int w; 101 int h; 102 }; 103 104 /* define the display timing fmt */ 105 enum drm_hal_timing_fmt { 106 DRM_HAL_TIMING_FMT_1080P_60, 107 DRM_HAL_TIMING_FMT_1080P_50, 108 DRM_HAL_TIMING_FMT_1080P_59_94, 109 DRM_HAL_TIMING_FMT_1080P_30, 110 DRM_HAL_TIMING_FMT_1080P_25, 111 DRM_HAL_TIMING_FMT_1080P_24, 112 DRM_HAL_TIMING_FMT_1080I_60, 113 DRM_HAL_TIMING_FMT_1080I_50, 114 DRM_HAL_TIMING_FMT_720P_60, 115 DRM_HAL_TIMING_FMT_720P_50, 116 DRM_HAL_TIMING_FMT_720P_30, 117 DRM_HAL_TIMING_FMT_720P_24, 118 DRM_HAL_TIMING_FMT_576P_50, 119 DRM_HAL_TIMING_FMT_480P_60, 120 DRM_HAL_TIMING_FMT_PAL, 121 DRM_HAL_TIMING_FMT_NTSC, 122 DRM_HAL_TIMING_FMT_861D_640X480_60, 123 DRM_HAL_TIMING_FMT_VESA_800X600_60, 124 DRM_HAL_TIMING_FMT_VESA_1024X768_60, 125 DRM_HAL_TIMING_FMT_VESA_1280X800_60, 126 DRM_HAL_TIMING_FMT_VESA_1280X1024_60, 127 DRM_HAL_TIMING_FMT_VESA_1366X768_60, 128 DRM_HAL_TIMING_FMT_VESA_1440X900_60, 129 DRM_HAL_TIMING_FMT_VESA_1600X1200_60, 130 DRM_HAL_TIMING_FMT_VESA_1680X1050_60, 131 DRM_HAL_TIMING_FMT_VESA_1920X1200_60, 132 DRM_HAL_TIMING_FMT_2560X1440_30, 133 DRM_HAL_TIMING_FMT_2560X1440_60, 134 DRM_HAL_TIMING_FMT_2560X1600_60, 135 DRM_HAL_TIMING_FMT_1920X2160_30, 136 DRM_HAL_TIMING_FMT_3840X2160P_24, 137 DRM_HAL_TIMING_FMT_3840X2160P_25, 138 DRM_HAL_TIMING_FMT_3840X2160P_30, 139 DRM_HAL_TIMING_FMT_3840X2160P_50, 140 DRM_HAL_TIMING_FMT_3840X2160P_60, 141 DRM_HAL_TIMING_FMT_4096X2160P_24, 142 DRM_HAL_TIMING_FMT_4096X2160P_25, 143 DRM_HAL_TIMING_FMT_4096X2160P_30, 144 DRM_HAL_TIMING_FMT_4096X2160P_50, 145 DRM_HAL_TIMING_FMT_4096X2160P_60, 146 DRM_HAL_TIMING_FMT_USER, 147 DRM_HAL_TIMING_FMT_MAX 148 }; 149 150 /* define the display timing struct */ 151 struct drm_hal_timing { 152 int clock; /* in kHz */ 153 int hdisplay; 154 int hsync_start; 155 int hsync_end; 156 int htotal; 157 int hskew; 158 int vdisplay; 159 int vsync_start; 160 int vsync_end; 161 int vtotal; 162 int vscan; 163 }; 164 165 #ifdef __cplusplus 166 #if __cplusplus 167 } 168 #endif 169 #endif /* __cplusplus */ 170 171 #endif /* _DRM_HAL_COMMON_H__ */ 172