1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_TIMG_STRUCT_H_ 15 #define _SOC_TIMG_STRUCT_H_ 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 typedef volatile struct timg_dev_s { 24 struct{ 25 union { 26 struct { 27 uint32_t reserved0: 10; 28 uint32_t alarm_en: 1; /*When set alarm is enabled*/ 29 uint32_t level_int_en: 1; /*When set level type interrupt will be generated during alarm*/ 30 uint32_t edge_int_en: 1; /*When set edge type interrupt will be generated during alarm*/ 31 uint32_t divider: 16; /*Timer clock (T0/1_clk) pre-scale value.*/ 32 uint32_t autoreload: 1; /*When set timer 0/1 auto-reload at alarming is enabled*/ 33 uint32_t increase: 1; /*When set timer 0/1 time-base counter increment. When cleared timer 0 time-base counter decrement.*/ 34 uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/ 35 }; 36 uint32_t val; 37 } config; 38 uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/ 39 uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/ 40 uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/ 41 uint32_t alarm_low; /*Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ 42 uint32_t alarm_high; /*Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ 43 uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/ 44 uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/ 45 uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/ 46 } hw_timer[2]; 47 union { 48 struct { 49 uint32_t reserved0: 14; 50 uint32_t flashboot_mod_en: 1; /*When set flash boot protection is enabled*/ 51 uint32_t sys_reset_length: 3; /*length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ 52 uint32_t cpu_reset_length: 3; /*length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ 53 uint32_t level_int_en: 1; /*When set level type interrupt generation is enabled*/ 54 uint32_t edge_int_en: 1; /*When set edge type interrupt generation is enabled*/ 55 uint32_t stg3: 2; /*Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 56 uint32_t stg2: 2; /*Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 57 uint32_t stg1: 2; /*Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 58 uint32_t stg0: 2; /*Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 59 uint32_t en: 1; /*When set SWDT is enabled*/ 60 }; 61 uint32_t val; 62 } wdt_config0; 63 union { 64 struct { 65 uint32_t reserved0: 16; 66 uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ 67 }; 68 uint32_t val; 69 } wdt_config1; 70 uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/ 71 uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/ 72 uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/ 73 uint32_t wdt_config5; /*Stage 3 timeout value in SWDT clock cycles*/ 74 uint32_t wdt_feed; /*Write any value will feed SWDT*/ 75 uint32_t wdt_wprotect; /*If change its value from default then write protection is on.*/ 76 union { 77 struct { 78 uint32_t reserved0: 12; 79 uint32_t start_cycling: 1; 80 uint32_t clk_sel: 2; 81 uint32_t rdy: 1; 82 uint32_t max: 15; 83 uint32_t start: 1; 84 }; 85 uint32_t val; 86 } rtc_cali_cfg; 87 union { 88 struct { 89 uint32_t reserved0: 7; 90 uint32_t value:25; 91 }; 92 uint32_t val; 93 } rtc_cali_cfg1; 94 union { 95 struct { 96 uint32_t reserved0: 7; 97 uint32_t rtc_only: 1; 98 uint32_t cpst_en: 1; 99 uint32_t lac_en: 1; 100 uint32_t alarm_en: 1; 101 uint32_t level_int_en: 1; 102 uint32_t edge_int_en: 1; 103 uint32_t divider: 16; 104 uint32_t autoreload: 1; 105 uint32_t increase: 1; 106 uint32_t en: 1; 107 }; 108 uint32_t val; 109 } lactconfig; 110 union { 111 struct { 112 uint32_t reserved0: 6; 113 uint32_t step_len:26; 114 }; 115 uint32_t val; 116 } lactrtc; 117 uint32_t lactlo; /**/ 118 uint32_t lacthi; /**/ 119 uint32_t lactupdate; /**/ 120 uint32_t lactalarmlo; /**/ 121 uint32_t lactalarmhi; /**/ 122 uint32_t lactloadlo; /**/ 123 uint32_t lactloadhi; /**/ 124 uint32_t lactload; /**/ 125 union { 126 struct { 127 uint32_t t0: 1; /*interrupt when timer0 alarm*/ 128 uint32_t t1: 1; /*interrupt when timer1 alarm*/ 129 uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ 130 uint32_t lact: 1; 131 uint32_t reserved4: 28; 132 }; 133 uint32_t val; 134 } int_ena; 135 union { 136 struct { 137 uint32_t t0: 1; /*interrupt when timer0 alarm*/ 138 uint32_t t1: 1; /*interrupt when timer1 alarm*/ 139 uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ 140 uint32_t lact: 1; 141 uint32_t reserved4:28; 142 }; 143 uint32_t val; 144 } int_raw; 145 union { 146 struct { 147 uint32_t t0: 1; /*interrupt when timer0 alarm*/ 148 uint32_t t1: 1; /*interrupt when timer1 alarm*/ 149 uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ 150 uint32_t lact: 1; 151 uint32_t reserved4: 28; 152 }; 153 uint32_t val; 154 } int_st_timers; 155 union { 156 struct { 157 uint32_t t0: 1; /*interrupt when timer0 alarm*/ 158 uint32_t t1: 1; /*interrupt when timer1 alarm*/ 159 uint32_t wdt: 1; /*Interrupt when an interrupt stage timeout*/ 160 uint32_t lact: 1; 161 uint32_t reserved4: 28; 162 }; 163 uint32_t val; 164 } int_clr_timers; 165 uint32_t reserved_a8; 166 uint32_t reserved_ac; 167 uint32_t reserved_b0; 168 uint32_t reserved_b4; 169 uint32_t reserved_b8; 170 uint32_t reserved_bc; 171 uint32_t reserved_c0; 172 uint32_t reserved_c4; 173 uint32_t reserved_c8; 174 uint32_t reserved_cc; 175 uint32_t reserved_d0; 176 uint32_t reserved_d4; 177 uint32_t reserved_d8; 178 uint32_t reserved_dc; 179 uint32_t reserved_e0; 180 uint32_t reserved_e4; 181 uint32_t reserved_e8; 182 uint32_t reserved_ec; 183 uint32_t reserved_f0; 184 uint32_t reserved_f4; 185 union { 186 struct { 187 uint32_t date:28; /*Version of this regfile*/ 188 uint32_t reserved28: 4; 189 }; 190 uint32_t val; 191 } timg_date; 192 union { 193 struct { 194 uint32_t reserved0: 31; 195 uint32_t en: 1; /*Force clock enable for this regfile*/ 196 }; 197 uint32_t val; 198 } clk; 199 } timg_dev_t; 200 extern timg_dev_t TIMERG0; 201 extern timg_dev_t TIMERG1; 202 203 #ifdef __cplusplus 204 } 205 #endif 206 207 #endif /* _SOC_TIMG_STRUCT_H_ */ 208