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/kernel/linux/linux-5.10/sound/soc/codecs/
Dmt6351.h12 #define MT6351_AFE_UL_DL_CON0 (0x2000 + 0x0000)
13 #define MT6351_AFE_DL_SRC2_CON0_H (0x2000 + 0x0002)
14 #define MT6351_AFE_DL_SRC2_CON0_L (0x2000 + 0x0004)
15 #define MT6351_AFE_DL_SDM_CON0 (0x2000 + 0x0006)
16 #define MT6351_AFE_DL_SDM_CON1 (0x2000 + 0x0008)
17 #define MT6351_AFE_UL_SRC_CON0_H (0x2000 + 0x000a)
18 #define MT6351_AFE_UL_SRC_CON0_L (0x2000 + 0x000c)
19 #define MT6351_AFE_UL_SRC_CON1_H (0x2000 + 0x000e)
20 #define MT6351_AFE_UL_SRC_CON1_L (0x2000 + 0x0010)
21 #define MT6351_AFE_TOP_CON0 (0x2000 + 0x0012)
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0 14 20 0
75 reg = <0x80008000 0x2000>;
83 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 87 86 0 0>;
98 reg = <0x80006000 0x800>;
[all …]
Dowl-s500.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
37 reg = <0x1>;
44 reg = <0x2>;
52 reg = <0x3>;
70 #clock-cells = <0>;
81 reg = <0xb0020000 0x100>;
86 reg = <0xb0020200 0x100>;
93 reg = <0xb0020600 0x20>;
[all …]
Ddm816x.dtsi31 #size-cells = <0>;
32 cpu@0 {
35 reg = <0>;
65 reg = <0x44000000 0x10000>;
73 reg = <0x48180000 0x4000>;
76 ranges = <0 0x48180000 0x4000>;
80 #size-cells = <0>;
89 reg = <0x48140000 0x21000>;
93 ranges = <0 0x48140000 0x21000>;
97 reg = <0x800 0x50a>;
[all …]
Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/kernel/linux/linux-5.10/drivers/clk/axs10x/
Di2s_pll_clock.c22 #define PLL_IDIV_REG 0x0
23 #define PLL_FBDIV_REG 0x4
24 #define PLL_ODIV0_REG 0x8
25 #define PLL_ODIV1_REG 0xC
37 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
38 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
39 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
40 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
41 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
42 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/event/
Dexynos-ppmu.txt34 reg = <0x106a0000 0x2000>;
40 reg = <0x106b0000 0x2000>;
46 reg = <0x106c0000 0x2000>;
52 reg = <0x112a0000 0x2000>;
60 reg = <0x116a0000 0x2000>;
124 reg = <0x10480000 0x2000>;
130 reg = <0x10490000 0x2000>;
136 reg = <0x104a0000 0x2000>;
142 reg = <0x104b0000 0x2000>;
148 reg = <0x104c0000 0x2000>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddpp.h52 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
54 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
56 {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
57 0, 0x2000, 0x38b4, 0xe3a6} },
59 {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
60 0, 0x2568, 0x40de, 0xdd3a} },
62 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
63 0x2000, 0x3b61, 0xe24f} },
66 {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
67 0x2568, 0x43ee, 0xdbb2} }
[all …]
/kernel/linux/linux-5.10/drivers/reset/
Dreset-uniphier.c20 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
45 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
46 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
51 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
52 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
53 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
54 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
55 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
56 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
57 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-db1x00/
Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv40.c43 ret = nvbios_pll_parse(bios, 0x04, &pll); in nv40_ram_calc()
50 if (ret < 0) in nv40_ram_calc()
53 ram->ctrl = 0x80000000 | (log2P << 16); in nv40_ram_calc()
56 ram->ctrl |= 0x00000100; in nv40_ram_calc()
59 ram->ctrl |= 0x40000000; in nv40_ram_calc()
63 return 0; in nv40_ram_calc()
74 u32 crtc_mask = 0; in nv40_ram_prog()
79 for (i = 0; i < 2; i++) { in nv40_ram_prog()
80 u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
81 u32 cnt = 0; in nv40_ram_prog()
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dhaps_hs.dts19 reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
20 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
24 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
41 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
71 reg = <0xf0100000 0x2000>;
77 reg = <0xf0102000 0x2000>;
83 reg = <0xf0104000 0x2000>;
89 reg = <0xf0106000 0x2000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/actions/
Ds700.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
56 reg = <0x0 0x1f000000 0x0 0x1000000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
107 reg = <0x0 0xe00f1000 0x0 0x1000>,
[all …]
Ds900.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
38 reg = <0x0 0x2>;
45 reg = <0x0 0x3>;
56 reg = <0x0 0x1f000000 0x0 0x1000000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
102 #clock-cells = <0>;
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Dmii.h10 #define MII_BMCR 0x00
11 #define MII_BMSR 0x01
12 #define MII_PHYSID1 0x02
13 #define MII_PHYSID2 0x03
14 #define MII_ADVERTISE 0x04
15 #define MII_LPA 0x05
16 #define MII_EXPANSION 0x06
17 #define MII_CTRL1000 0x09
18 #define MII_STAT1000 0x0a
19 #define MII_MMD_CTRL 0x0d
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.txt23 - port0: contains the resources for ethernet port 0
59 reg = <0x60000000 0x4000>, /* Global registers, queue */
60 <0x60004000 0x2000>, /* V-bit */
61 <0x60006000 0x2000>; /* A-bit */
67 gmac0: ethernet-port@0 {
69 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
70 <0x6000a000 0x2000>; /* Port 0 GMAC */
82 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
83 <0x6000e000 0x2000>; /* Port 1 GMAC */
/kernel/linux/linux-5.10/drivers/crypto/inside-secure/
Dsafexcel.h19 #define EIP197_HIA_VERSION_BE 0xca35
20 #define EIP197_HIA_VERSION_LE 0x35ca
21 #define EIP97_VERSION_LE 0x9e61
22 #define EIP196_VERSION_LE 0x3bc4
23 #define EIP197_VERSION_LE 0x3ac5
24 #define EIP96_VERSION_LE 0x9f60
25 #define EIP201_VERSION_LE 0x36c9
26 #define EIP206_VERSION_LE 0x31ce
27 #define EIP207_VERSION_LE 0x30cf
28 #define EIP197_REG_LO16(reg) (reg & 0xffff)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
155 const: 0
169 const: 0
203 const: 0
294 "^(pru|rtu|txpru)@[0-9a-f]+$":
335 pruss: pruss@0 {
337 reg = <0x0 0x80000>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_opp_csc_v.c39 /* constrast:0 - 2.0, default 1.0 */
42 #define UNDERLAY_CONTRAST_MIN 0
46 /* Saturation: 0 - 2.0; default 1.0 */
48 #define UNDERLAY_SATURATION_MIN 0
56 #define UNDERLAY_HUE_DEFAULT 0
71 #define UNDERLAY_BRIGHTNESS_DEFAULT 0
79 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
81 { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
83 { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
84 0xF6B9, 0xE00, 0x1000} },
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/wm8350/
Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/
Dfoundation-v8-gicv2.dtsi13 reg = <0x0 0x2c001000 0 0x1000>,
14 <0x0 0x2c002000 0 0x2000>,
15 <0x0 0x2c004000 0 0x2000>,
16 <0x0 0x2c006000 0 0x2000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/kernel/linux/patches/linux-5.10/prebuilts/usr/include/linux/
Dmii.h23 #define MII_BMCR 0x00
24 #define MII_BMSR 0x01
25 #define MII_PHYSID1 0x02
26 #define MII_PHYSID2 0x03
27 #define MII_ADVERTISE 0x04
28 #define MII_LPA 0x05
29 #define MII_EXPANSION 0x06
30 #define MII_CTRL1000 0x09
31 #define MII_STAT1000 0x0a
32 #define MII_MMD_CTRL 0x0d
[all …]

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