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/arkcompiler/runtime_core/compiler/optimizer/ir/
Dinstructions.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 Opcode of the instruction
19 Describes signature of the instruction. Properties of the operands are separated by '-' symbol.
26 …C++ base that represent this opcode. In far future if we managed to generate also instruction clas…
30 Properties of the instruction, such as: arithmetic, binop, throw, etc
33 Modes which the instruction can be used in
36 # Templates aim to reduce boilerplate in instruction description.
39 - equal_common_types
40 - float_src_eq_dst_size
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/arkcompiler/runtime_core/compiler/optimizer/ir_builder/
Dinst_templates.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 binop: |-
18 % raise "Wrong binop instruction" unless opc
20 …auto inst = graph_->CreateInst<%= opc %>(<%= get_type(inst.dtype) %>, GetPc(instruction->GetAddres…
21 <%=template('operands', inst, '')-%>
23 binop_z: |-
25 auto inst_save_state = CreateSaveState(Opcode::SaveState, GetPc(instruction->GetAddress()));
26 …auto inst_check = graph_->CreateInstZeroCheck(<%= get_type(inst.dtype) %>, GetPc(instruction->GetA…
28 if (graph_->IsBytecodeOptimizer()) {
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/arkcompiler/ets_frontend/testTs/instype/
Drecordthis-expected.txt2 (instruction order, type): (-2, 111), (-1, 106),
4 (instruction order, type): (-2, 111), (-1, 102),
6 (instruction order, type): (-2, 111), (-1, 103),
8 (instruction order, type): (-2, 111), (-1, 104),
10 (instruction order, type): (-2, 111), (-1, 105),
12 (instruction order, type): (-2, 111), (-1, 107), (16, 4),
14 (instruction order, type): (-2, 101), (-1, 108),
16 (instruction order, type): (-2, 111), (-1, 109),
18 (instruction order, type): (-2, 111), (-1, 110),
20 (instruction order, type): (-1, 112), (9, 1),
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Drecordimport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
12 (instruction order, type): (5, 101), (8, 105), (19, 107), (22, 102), (25, 103), (31, 104), (37, 106…
Drecordexport-expected.txt2 (instruction order, type): (-1, 101),
4 (instruction order, type): (-2, 105),
6 (instruction order, type): (-1, 103),
8 (instruction order, type): (-1, 104),
10 (instruction order, type): (8, 101), (10, 1), (12, 103), (14, 104), (16, 1), (18, 1), (20, 1), (22,…
/arkcompiler/runtime_core/docs/
Dir_format.md7 * Compiler overhead about 100000 native instructions per a bytecode instruction(standard for JIT co…
60 * Supporting side exits for de-optimizations and removing cold code.
65 ## Instruction set
76 …ble to do arm specific optimizations. For this, need to support ARMv8-M Instruction Set(only those…
80 IR contains high- and low-level instructions with a single interface.
81 In the first step, Panda bytecode is converted to high level instruction and architecturally indepe…
87 …f 'native' instructions(ARM) that are spent compiling a single 'guest' instruction(from Bytecode).…
90 In Ahead-Of-Time(AOT) mode the overhead is less critical for us, so we can do more optimizations.
91 In Just-In-Time(JIT) mode need to strictly control the overhead to get the overall performance incr…
104 …e Assignment) form(used in LLVM, WebKit, HHVM, CoreCLR, IonMonkey) and Sea-of-Nodes(Hotspot, V8 Tu…
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Drationale-for-bytecode.md10 Before discussing bytecode per se, let's take a look at an over-simplified picture of a real
40 Just as real CPUs can expose different instruction set architectures, there is no universal way of
47 In _stack-based_ approach, operands are implicitly encoded in the operation, which results in
54 add ; remove two top-most values from the stack, add them and put the result at the top
60 In _register-based approach_, operands are explicitly encoded in the operation, which results in
71 This example demonstrates a fundamental difference between two approaches. Stack-based approach
72 operates with smaller instructions. Indeed, each instruction `push_arg1`, `push_arg1`, and `add`
73 can be represented with a single byte, while register-based `add reg_dst, reg_src1, reg_src2` may
76 At the same time, to execute a stack-based addition we need to run 3 instructions compared to
77 just a single register-based instruction. Since the interpreter has an extra work to do to read
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/arkcompiler/runtime_core/tests/cts-generator/cts-template/
Djnez.obj.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jnez.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
28 - x_none
30 - sig: jnez.obj imm:i32
35 - file-name: "invalid_offset"
38 - branch_target
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Djeqz.obj.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jeqz.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
28 - x_none
30 - sig: jeqz.obj imm:i32
35 - file-name: "invalid_offset"
38 - branch_target
[all …]
Djne.obj.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jne.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
28 - x_none
30 - branch_target
31 - acc_obj_or_null
32 - v1_obj_or_null
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Djeq.obj.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - name: PandaAssembly
20 - file-name: "jeq.obj"
24 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
26 instruction address.
28 - x_none
30 - branch_target
31 - acc_obj_or_null
32 - v1_obj_or_null
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Djeq.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - file-name: "jeq"
19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
20 …32-bit integers in accumulator and register compare as specified. Offset is sign extended to the s…
21 instruction address.
23 - x_none
25 - sig: jeq v:in:i32, imm:i32
30 - file-name: "invalid_v_reg"
33 - v1_type
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Djgt.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - file-name: "jgt"
19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
20 …32-bit integers in accumulator and register compare as specified. Offset is sign extended to the s…
21 instruction address.
23 - x_none
25 - sig: jgt v:in:i32, imm:i32
30 - file-name: "invalid_v_reg"
33 - v1_type
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Djle.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - file-name: "jle"
19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
20 …32-bit integers in accumulator and register compare as specified. Offset is sign extended to the s…
21 instruction address.
23 - x_none
25 - sig: jle v:in:i32, imm:i32
30 - file-name: "invalid_v_reg"
33 - v1_type
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Djlt.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - file-name: "jlt"
19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
20 …32-bit integers in accumulator and register compare as specified. Offset is sign extended to the s…
21 instruction address.
23 - x_none
25 - sig: jlt v:in:i32, imm:i32
30 - file-name: "invalid_v_reg"
33 - v1_type
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Djge.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - file-name: "jge"
19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
20 …32-bit integers in accumulator and register compare as specified. Offset is sign extended to the s…
21 instruction address.
23 - x_none
25 - sig: jge v:in:i32, imm:i32
30 - file-name: "invalid_v_reg"
33 - v1_type
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Djne.yaml1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
15 - file-name: "jne"
19 …Transfer execution to an instruction at offset bytes from the beginning of the current instruction
20 …32-bit integers in accumulator and register compare as specified. Offset is sign extended to the s…
21 instruction address.
23 - x_none
25 - sig: jne v:in:i32, imm:i32
30 - file-name: "invalid_v_reg"
33 - v1_type
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/arkcompiler/runtime_core/compiler/docs/
Dir_builder.md18 - some instructions don't specify its type, f.e. `mov` instruction may produce int32 as well as flo…
20 - constant hasn't type as well and if one constant is used in integer and float operations, it must…
22 - if constant is `0` and it is used in instruction that expects object(f.e. `mov.obj`), we need to …
23 constant instruction `NullPtr` to handle this situation.
53 4. Get next bytecode instruction from the current basic block.
54 5. Build the Panda IR instruction from the bytecode instruction:
55 - create auxiliary instructions (SaveState, NullCheck, etc) if needed
56 - set inputs from the virtual register map
57 - if has destination, update virtual register definition in the vreg map
58 6. If instruction is a terminator, goto 1, else goto 4.
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Dvn_doc.md5 Value numbering sets special numbers(`vn`) to all instructions. If two instruction has equal VN, so…
6 At the case we move users from second instruction to first instructions(first instruction is domina…
19 We pass through all instructions in PRO order. If the instruction has attribute NO_Cse, we set next…
20 For other instructions we save information: opcode, type, `vn` of instruction inputs, advanced prop…
24 …a. If some equivalent instruction dominates current instruction, we move users from current instru…
25 …e current instruction, we insert the instruction in the equivalent instructions vector, and also g…
26 …weren't found, we set next `vn` to the current instruction field and add information about the ins…
34 for (auto bb : GetGraph()->GetBlocksRPO()) {
35 for (auto inst : bb->AllInsts()) {
43 if (inst->IsNotCseApplicable()) {
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Ddeoptimize_elimination_doc.md3 **Deoptimize Elimination** - optimization which try to reduce number of DeoptimizeIf instructions.
6 Reduce number of instructions and removes unnecessary data-flow dependencies.
17 If `SaveStateDeoptimize` didn't have users, this instruction is replaced by `NOP`.
21 * Constant is equal 0 -> `DeoptimizeIf` is replaced by `NOP`.
22 * Other constant -> `DeoptimizeIf` is replaced by `Deoptimize` instruction.
29 …rithm try to replaced by `NOP` all `DeoptimizeIf` instruction which is dominated by current instru…
/arkcompiler/runtime_core/bytecode_optimizer/
Dbytecode_optimizer_isapi.rb1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
16 Instruction.class_eval do
48 @instruction_hash = Hash.new { |_, key| raise "No instruction with '#{key}' mnemonic" }
63 LOG(ERROR, BYTECODE_OPTIMIZER) << \"Codegen for \" << compiler::GetOpcodeString(inst->GetOpcode()) …
64 enc->success_ = false;
75 LOG(ERROR, BYTECODE_OPTIMIZER) << \"CheckWidth for \" << compiler::GetOpcodeString(inst->GetOpcode(…
76 re->success_ = false;
100 Leaf = Struct.new(:instruction, :args) do
104 if instruction.acc_read?
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/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
Dassembler_aarch64_constants.h7 * http://www.apache.org/licenses/LICENSE-2.0
219 /* Aarch64 Instruction MOVZ Field Defines
222 Aarch64 Instruction MOVN Field Defines
225 Aarch64 Instruction MOVK Field Defines
233 /* Aarch64 Instruction AddImm Field Defines
236 Aarch64 Instruction AddShift Field Defines
239 Aarch64 Instruction AddExtend Field Defines
253 Aarch64 Instruction OrrImm Field Defines
256 Aarch64 Instruction ORRShift Field Defines
268 Aarch64 Instruction CMP Instruction is aliase of Subs
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/arkcompiler/runtime_core/tests/checked/
DREADME.md4 For example, check some event was raised or some IR instruction is appeared after specific optimiza…
18 - *force_jit: bool* - run jit compilation for every executed method
19 - *options: string* - additional options for Panda VM
20 - *entry: string* - entry point, default - `_GLOBAL::main`
21 - *result: int* - expected value to be returned by the `panda` application
22 - *abort: int* - expected terminal signal
32 * **INST** (inst: pattern) search specified instruction in the ir dump file specified by commands `…
33 * **INST_NOT** (inst: pattern) equal to `NOT INST`, i.e. check that instruction is not exist
34 * **INST_NEXT_NOT** (event: pattern) ensure instruction is not occurred after current position
40 …st: pattern) select a specified instruction in disasm file, next "ASM*" checks will be applied onl…
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/arkcompiler/runtime_core/isa/
DChangeLog.md4 + Removed builtins and API for template-based generation for builtins
5 + ISAPI: removed acc_none, acc_read, acc_write properties in favor of Instruction::acc_none?,
6 Instruction::acc_read?, Instruction::acc_write? properties
/arkcompiler/runtime_core/tests/cts-generator/generator/
Dtest_case.rb1 # Copyright (c) 2021-2022 Huawei Device Co., Ltd.
6 # http://www.apache.org/licenses/LICENSE-2.0
22 … def initialize(command, current_case, instruction, definitions, predefined, template, skip_header) argument
23 super instruction, command, definitions, predefined, skip_header
25 LOG.debug "TestCase created with '#{command}' '#{current_case}' '#{instruction}'"
27 # command - YAML:
29 # check-type: Generator::CASE_CHECK_TYPE
32 # current_case - YAML:
34 # case-check-type: Generator::CASE_CHECK_TYPE
35 # code-template: Generator::CASE_TEMPLATE
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