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/arkcompiler/runtime_core/compiler/tests/aarch32/
Dcallconv32_test.cpp98 // std::variant<Reg, uint8_t> GetNativeParam(const TypeInfo& type) in TEST_F()
105 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
106 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
107 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT8_TYPE)); in TEST_F()
111 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
112 EXPECT_EQ(std::get<Reg>(ret).GetId(), i); in TEST_F()
113 EXPECT_EQ(std::get<Reg>(ret), Reg(i, INT8_TYPE)); in TEST_F()
121 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
122 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
123 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT32_TYPE)); in TEST_F()
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Dregister32_test.cpp70 std::vector<Reg> regs; in TEST_F()
76 for (auto reg : regs) { in TEST_F() local
77 encoder.ReleaseScratchRegister(reg); in TEST_F()
88 for (auto reg : regs) { in TEST_F() local
89 encoder.ReleaseScratchRegister(reg); in TEST_F()
94 ScopedTmpRegRef reg(&encoder); in TEST_F() local
/arkcompiler/runtime_core/compiler/optimizer/optimizations/regalloc/
Dreg_map.cpp26 for (size_t reg = priority_reg; reg < reg_mask.GetSize(); ++reg) { in SetMask() local
27 if (!reg_mask.IsSet(reg)) { in SetMask()
28 codegen_reg_map_.push_back(reg); in SetMask()
34 for (size_t reg = 0; reg < priority_reg; ++reg) { in SetMask() local
35 if (!reg_mask.IsSet(reg)) { in SetMask()
36 codegen_reg_map_.push_back(reg); in SetMask()
42 for (size_t reg = 0; reg < reg_mask.GetSize(); ++reg) { in SetMask() local
43 if (reg_mask.IsSet(reg)) { in SetMask()
44 codegen_reg_map_.push_back(reg); in SetMask()
54 for (size_t reg = 0; reg < first_callee_reg; ++reg) { in SetCallerFirstMask() local
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Dspill_fills_resolver.h106 Location ToLocation(LocationIndex reg) in ToLocation() argument
108 if (reg >= PARAMETER_SLOTS_OFFSET) { in ToLocation()
109 return Location::MakeStackParameter(reg - PARAMETER_SLOTS_OFFSET); in ToLocation()
111 if (reg >= SLOTS_TABLE_OFFSET) { in ToLocation()
112 return Location::MakeStackSlot(reg - SLOTS_TABLE_OFFSET); in ToLocation()
114 if (reg >= VREGS_TABLE_OFFSET) { in ToLocation()
115 return Location::MakeFpRegister(reg - VREGS_TABLE_OFFSET); in ToLocation()
117 return Location::MakeRegister(reg); in ToLocation()
Dspill_fills_resolver.cpp93 auto reg = location.IsFpRegister() ? location.GetValue() + offset : location.GetValue(); in MarkRegWrite() local
94 ASSERT(reg < reg_write->size()); in MarkRegWrite()
95 (*reg_write)[reg] = true; in MarkRegWrite()
97 (*reg_write)[reg + 1] = true; in MarkRegWrite()
103 auto reg = location.IsFpRegister() ? location.GetValue() + offset : location.GetValue(); in IsRegWrite() local
104 ASSERT(reg < reg_write->size()); in IsRegWrite()
105 return (*reg_write)[reg] || (paired && (*reg_write)[reg + 1]); in IsRegWrite()
206 * - dst-reg is NOT used as src-reg in the other spill-fills
207 * - dst-reg is in the cyclically dependent chain of moves: (R1->R2, R2->R1)
241 …e chain of moves is cyclically dependent (R3->R1, R2->R3, R1->R2) and resolve it with a `temp-reg`:
/arkcompiler/runtime_core/compiler/tests/aarch64/
Dcallconv64_test.cpp90 // std::variant<Reg, uint8_t> GetNativeParam(const ArenaVector<TypeInfo>& reg_list, in TEST_F()
97 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
98 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
99 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT8_TYPE)); in TEST_F()
103 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
104 EXPECT_EQ(std::get<Reg>(ret).GetId(), i); in TEST_F()
105 EXPECT_EQ(std::get<Reg>(ret), Reg(i, INT8_TYPE)); in TEST_F()
113 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
114 EXPECT_EQ(std::get<Reg>(ret).GetId(), 0); in TEST_F()
115 EXPECT_EQ(std::get<Reg>(ret), Reg(0, INT32_TYPE)); in TEST_F()
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Dregister64_test.cpp67 std::vector<Reg> regs; in TEST_F()
73 for (auto reg : regs) { in TEST_F() local
74 encoder.ReleaseScratchRegister(reg); in TEST_F()
85 for (auto reg : regs) { in TEST_F() local
86 encoder.ReleaseScratchRegister(reg); in TEST_F()
91 ScopedTmpRegRef reg(&encoder); in TEST_F() local
/arkcompiler/runtime_core/compiler/tests/amd64/
Dcallconv64_test.cpp90 // std::variant<Reg, uint8_t> GetNativeParam(const ArenaVector<TypeInfo>& reg_list, in TEST_F()
98 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
99 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(0)); in TEST_F()
100 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(0), INT8_TYPE)); in TEST_F()
104 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
105 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(i)); in TEST_F()
106 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(i), INT8_TYPE)); in TEST_F()
114 EXPECT_TRUE(std::holds_alternative<Reg>(ret)); in TEST_F()
115 EXPECT_EQ(std::get<Reg>(ret).GetId(), target.GetParamRegId(0)); in TEST_F()
116 EXPECT_EQ(std::get<Reg>(ret), Reg(target.GetParamRegId(0), INT32_TYPE)); in TEST_F()
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Dregister64_test.cpp70 std::vector<Reg> regs; in TEST_F()
76 for (auto reg : regs) { in TEST_F() local
77 encoder.ReleaseScratchRegister(reg); in TEST_F()
88 for (auto reg : regs) { in TEST_F() local
89 encoder.ReleaseScratchRegister(reg); in TEST_F()
94 ScopedTmpRegRef reg(&encoder); in TEST_F() local
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/x64/
Dassembler_x64.h181 void EmitRexPrefix(Register reg, Register rm) in EmitRexPrefix() argument
184 // 2: Extension to the MODRM.reg field R in EmitRexPrefix()
185 EmitU8(REX_PREFIX_W | (HighBit(reg) << 2) | HighBit(rm)); in EmitRexPrefix()
188 void EmitRexPrefixl(Register reg, Register rm) in EmitRexPrefixl() argument
191 if (HighBit(reg) != 0 || HighBit(rm) != 0) { in EmitRexPrefixl()
192 // 2: Extension to the MODRM.reg field R in EmitRexPrefixl()
193 EmitU8(REX_PREFIX_FIXED_BITS | (HighBit(reg) << 2) | HighBit(rm)); in EmitRexPrefixl()
197 void EmitRexPrefix(Register reg, Operand rm) in EmitRexPrefix() argument
200 // 2: Extension to the MODRM.reg field R in EmitRexPrefix()
201 EmitU8(REX_PREFIX_W | (HighBit(reg) << 2) | rm.rex_); in EmitRexPrefix()
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/arkcompiler/ets_frontend/es2panda/compiler/templates/
Disa.h.erb119 % map['reg'].push("#{name}_")
188 % registers = op_map['reg'].map {|reg| "&#{reg}"}.join(", ")
202 % for reg in op_map['reg']
203 (*regs)[<%= reg_cnt %>] = &<%= reg %>;
212 % for reg in op_map['reg']
213 (*regs)[<%= reg_cnt %>] = &<%= reg %>;
222 % if op_map['reg'].length != 0
223 ins->regs.reserve(<%= op_map['reg'].length %>);
231 % for reg in op_map['reg']
232 ins->regs.emplace_back(<%= reg %>);
/arkcompiler/ets_runtime/ecmascript/deoptimizer/
DcalleeReg.cpp55 int CalleeReg::FindCallRegOrder(const LLVMStackMapType::DwarfRegType reg) const in FindCallRegOrder()
57 auto it = reg2Location_.find(static_cast<DwarfReg>(reg)); in FindCallRegOrder()
61 LOG_FULL(FATAL) << "reg:" << std::dec << reg; in FindCallRegOrder()
66 int CalleeReg::FindCallRegOrder(const DwarfReg reg) const in FindCallRegOrder()
68 auto order = FindCallRegOrder(static_cast<LLVMStackMapType::DwarfRegType>(reg)); in FindCallRegOrder()
/arkcompiler/ets_runtime/ecmascript/stackmap/
Dllvm_stackmap_type.cpp19 DwarfRegType reg, OffsetType offset, Triple triple) in EncodeRegAndOffset() argument
24 if (reg == fpReg) { in EncodeRegAndOffset()
26 } else if (reg == spReg) { in EncodeRegAndOffset()
37 void LLVMStackMapType::DecodeRegAndOffset(SLeb128Type regOffset, DwarfRegType &reg, OffsetType &off… in DecodeRegAndOffset() argument
40 reg = GCStackMapRegisters::FP; in DecodeRegAndOffset()
42 reg = GCStackMapRegisters::SP; in DecodeRegAndOffset()
Dark_stackmap_parser.cpp160 LLVMStackMapType::DwarfRegType reg; in ParseArkStackMap() local
168 LLVMStackMapType::DecodeRegAndOffset(regOffset, reg, offsetType); in ParseArkStackMap()
170 LOG_COMPILER(VERBOSE) << " reg: " << std::dec << reg << " offset:" << offsetType; in ParseArkStackMap()
171 arkStackMaps.emplace_back(std::make_pair(reg, offsetType)); in ParseArkStackMap()
183 LLVMStackMapType::DwarfRegType reg; in ParseArkDeopt() local
206 LLVMStackMapType::DecodeRegAndOffset(regOffset, reg, offsetType); in ParseArkDeopt()
208 deopt.value = std::make_pair(reg, offsetType); in ParseArkDeopt()
/arkcompiler/ets_frontend/es2panda/compiler/core/
DregAllocator.cpp130 for (auto *reg : registers) { in AdjustInsRegWhenHasSpill() local
131 *reg = *reg + spillRegs_; in AdjustInsRegWhenHasSpill()
157 for (auto *reg : registers) { in AdjustInsSpill() local
158 if (IsRegisterCorrect(reg)) { in AdjustInsSpill()
163 const auto originReg = *reg; in AdjustInsSpill()
171 *reg = spillIndex_++; in AdjustInsSpill()
194 VReg *reg = *iter; in AdjustRangeInsSpill() local
195 Add<Mov>(newInsns, ins->Node(), spillIndex_, *reg); in AdjustRangeInsSpill()
196 *reg = spillIndex_++; in AdjustRangeInsSpill()
/arkcompiler/ets_runtime/test/typeinfer/automatedcases/
DvarArgsOnConstructorTypes.ts55 let reg: I1; variable
56 AssertType(reg, "I1");
58 reg.register(B);
59 AssertType(reg.register(B), "any");
60 AssertType(reg.register, "{ (new (...any[]) => A): any; ((new (...any[]) => A)[]): any; }");
/arkcompiler/runtime_core/libpandabase/utils/
Dregmask.h138 // Given `reg` is not counted even if it is set.
139 constexpr size_t GetDistanceFromTail(size_t reg) const in GetDistanceFromTail() argument
141 ASSERT(reg < Size()); in GetDistanceFromTail()
142 uint32_t val = GetValue() & ((1U << reg) - 1); in GetDistanceFromTail()
147 // Given `reg` is not counted even if it is set.
148 constexpr size_t GetDistanceFromHead(size_t reg) const in GetDistanceFromHead() argument
150 if (reg < (Size() - 1)) { in GetDistanceFromHead()
151 uint32_t val = GetValue() & ~((1U << (reg + 1)) - 1); in GetDistanceFromHead()
154 if (reg == Size() - 1) { in GetDistanceFromHead()
157 // reg > (Size() - 1), something goes wrong... in GetDistanceFromHead()
/arkcompiler/runtime_core/docs/
Drationale-for-bytecode.md139 | virt. reg. 0 | some local variable |
140 | virt. reg. 1 | some local variable |
141 | virt. reg. 2 | some temporary value |
142 | virt. reg. 3 | some temporary value |
143 | virt. reg. 4 | arg1 |
144 | virt. reg. 5 | arg2 |
177 (acc-reg-reg, acc-reg, acc-imm) and integer-based jumps, but not for floating-point arithmetic
178 (which is rare) and which is supposed to have only acc-reg form. Another good candidates for
/arkcompiler/runtime_core/bytecode_optimizer/
Dreg_encoder.cpp329 sf_inst->AddMove(src, dst.reg, GetRegType(dst.type)); in AddMoveBefore()
330 … LOG(DEBUG, BYTECODE_OPTIMIZER) << "RegEncoder: Move v" << static_cast<int>(dst.reg) << " <- v" in AddMoveBefore()
378 inst->SetSrcReg(i, reg_cont.reg); in InsertSpillsForDynInputsInst()
403 auto reg = inst->GetSrcReg(i); in InsertSpillsForInst() local
404 if (RegNeedsRenumbering(reg) && reg >= NUM_COMPACTLY_ENCODED_REGS) { in InsertSpillsForInst()
405 auto res = spill_map.emplace(reg, RegContent(temp, GetRegType(inst->GetInputType(i)))); in InsertSpillsForInst()
413 inst->SetSrcReg(i, reg_cont.reg); in InsertSpillsForInst()
421 static void IncTempsIfNeeded(const compiler::Register reg, compiler::Register &num_temps) in IncTempsIfNeeded() argument
423 if (RegNeedsRenumbering(reg) && reg >= NUM_COMPACTLY_ENCODED_REGS) { in IncTempsIfNeeded()
451 auto reg = inst->GetSrcReg(i); in CalculateNumNeededTempsForInst() local
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Dreg_encoder.h73 compiler::Register reg; member
76 RegContent() : reg(compiler::INVALID_REG), type(compiler::DataType::NO_TYPE) {} in RegContent()
77 RegContent(compiler::Register r, compiler::DataType::Type t) : reg(r), type(t) {} in RegContent()
81 return reg == other.reg && type == other.type;
/arkcompiler/ets_runtime/ecmascript/compiler/assembler/aarch64/
Dassembler_aarch64.h25 Register(RegisterId reg, RegisterType type = RegisterType::X) : reg_(reg), type_(type) {}; in reg_() argument
79 explicit VectorRegister(VectorRegisterId reg, Scale scale = D) : reg_(reg), scale_(scale) {}; in reg_() argument
164 Operand(Register reg, Shift shift = Shift::LSL, uint8_t shift_amount = 0)
165 … : reg_(reg), extend_(Extend::NO_EXTEND), shift_(shift), shiftAmount_(shift_amount), immediate_(0) in reg_() argument
168 Operand(Register reg, Extend extend, uint8_t shiftAmount = 0)
169 … : reg_(reg), extend_(extend), shift_(Shift::NO_SHIFT), shiftAmount_(shiftAmount), immediate_(0) in reg_() argument
189 inline Register Reg() const in Reg() function
355 // common reg field defines
/arkcompiler/runtime_core/bytecode_optimizer/tests/
Dcodegen_test.cpp63 Register reg = 1; // 1: It's a random number variable
65 DoLda(reg, result);
66 EXPECT_EQ(result[0].regs[0], reg);
78 Register reg = 1; // 1: It's a random number variable
80 DoSta(reg, result);
81 EXPECT_EQ(result[0].regs[0], reg);
192 Register reg = INVALID_REG; in __anona44e78530302() local
193 const_inst->SetDstReg(reg); in __anona44e78530302()
194 EXPECT_EQ(const_inst->GetDstReg(), reg); in __anona44e78530302()
202 const_inst1->SetDstReg(reg); in __anona44e78530302()
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/arkcompiler/ets_frontend/merge_abc/src/
DassemblyDebugProto.cpp43 protoDebug.set_reg(debug.reg); in Serialize()
54 debug.reg = protoDebug.reg(); in Deserialize()
/arkcompiler/runtime_core/assembler/
Dassembly-ins.cpp24 for (const auto &reg : this->regs) { in RegsToString()
31 if (print_args && reg >= first_arg_idx) { in RegsToString()
32 translator << " a" << reg - first_arg_idx; in RegsToString()
34 translator << " v" << reg; in RegsToString()
/arkcompiler/ets_runtime/ecmascript/compiler/
Dbytecode_circuit_builder.h291 …GateRef ResolveDef(const size_t bbId, int32_t bcId, const uint16_t reg, const bool acc, bool needI…
292 GateRef ResolveDef(const BytecodeRegion &bb, int32_t bcId, const uint16_t reg, const bool acc);
564 void NewPhi(BytecodeRegion &bb, uint16_t reg, bool acc, GateRef &currentPhi);
565 GateRef NewLoopBackPhi(BytecodeRegion &bb, uint16_t reg, bool acc);
566 GateRef NewLoopForwardPhi(BytecodeRegion &bb, uint16_t reg, bool acc);
567 bool IsLoopExitValueExists(GateRef loopExit, uint16_t reg, bool acc);
568 GateRef GetLoopExitValue(GateRef loopExit, uint16_t reg, bool acc);
569 GateRef CreateLoopExitValue(GateRef loopExit, uint16_t reg, bool acc, GateRef value);
570 GateRef NewLoopExitValue(GateRef loopExit, uint16_t reg, bool acc, GateRef value);
571 … GateRef NewValueFromPredBB(BytecodeRegion &bb, size_t idx, GateRef exit, uint16_t reg, bool acc);
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