1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "hal_config.h"
16 #include "spi_hw.h"
17 #include "spi_hal.h"
18 #include "spi_ll.h"
19
20 #if CFG_HAL_DEBUG_SPI
21
spi_struct_dump(spi_id_t id)22 void spi_struct_dump(spi_id_t id)
23 {
24 if (id >= SOC_SPI_UNIT_NUM) {
25 SOC_LOGW("spi_id(%d) is out of range(%d)\r\n", id, SOC_SPI_UNIT_NUM);
26 return;
27 }
28 spi_hw_t *hw = (spi_hw_t *)SPI_LL_REG_BASE(id);
29 SOC_LOGI("base=%x\r\n", (uint32_t)hw);
30
31 SOC_LOGI(" ctrl=0x%x value=0x%x\n", &hw->ctrl, hw->ctrl.v);
32 SOC_LOGI(" tx_fifo_int_level: %x\n", hw->ctrl.tx_fifo_int_level);
33 SOC_LOGI(" rx_fifo_int_level: %x\n", hw->ctrl.rx_fifo_int_level);
34 SOC_LOGI(" tx_udf_int_en: %x\n", hw->ctrl.tx_udf_int_en);
35 SOC_LOGI(" rx_ovf_int_en: %x\n", hw->ctrl.rx_ovf_int_en);
36 SOC_LOGI(" tx_fifo_int_en: %x\n", hw->ctrl.tx_fifo_int_en);
37 SOC_LOGI(" rx_fifo_int_en: %x\n", hw->ctrl.rx_fifo_int_en);
38 SOC_LOGI(" clk_rate: %x\n", hw->ctrl.clk_rate);
39 SOC_LOGI(" slave_release_int_en: %x\n", hw->ctrl.slave_release_int_en);
40 SOC_LOGI(" wire3_en: %x\n", hw->ctrl.wire3_en);
41 SOC_LOGI(" bit_width: %x\n", hw->ctrl.bit_width);
42 SOC_LOGI(" lsb_first_en: %x\n", hw->ctrl.lsb_first_en);
43 SOC_LOGI(" cpol: %x\n", hw->ctrl.cpol);
44 SOC_LOGI(" cpha: %x\n", hw->ctrl.cpha);
45 SOC_LOGI(" master_en: %x\n", hw->ctrl.master_en);
46 SOC_LOGI(" enable: %x\n", hw->ctrl.enable);
47 SOC_LOGI(" byte_interval: %x\n", hw->ctrl.byte_interval);
48
49 SOC_LOGI("\n");
50 SOC_LOGI(" config=0x%x value=0x%x\n", &hw->cfg, hw->cfg.v);
51 SOC_LOGI(" tx_en: %x\n", hw->cfg.tx_en);
52 SOC_LOGI(" rx_en: %x\n", hw->cfg.rx_en);
53 SOC_LOGI(" tx_finish_int_en: %x\n", hw->cfg.tx_finish_int_en);
54 SOC_LOGI(" rx_finish_int_en: %x\n", hw->cfg.rx_finish_int_en);
55 SOC_LOGI(" tx_trans_len: %x\n", hw->cfg.tx_trans_len);
56 SOC_LOGI(" rx_trans_len: %x\n", hw->cfg.rx_trans_len);
57
58 SOC_LOGI("\n");
59 SOC_LOGI(" status=0x%x value=0x%x\n", &hw->int_status, hw->int_status.v);
60 SOC_LOGI(" tx_fifo_wr_ready: %x\n", hw->int_status.tx_fifo_wr_ready);
61 SOC_LOGI(" rx_fifo_rd_ready: %x\n", hw->int_status.rx_fifo_rd_ready);
62 SOC_LOGI(" tx_fifo_int: %x\n", hw->int_status.tx_fifo_int);
63 SOC_LOGI(" rx_fifo_int: %x\n", hw->int_status.rx_fifo_int);
64 SOC_LOGI(" slave_release_int: %x\n", hw->int_status.slave_release_int);
65 SOC_LOGI(" tx_underflow: %x\n", hw->int_status.tx_underflow_int);
66 SOC_LOGI(" rx_overflow: %x\n", hw->int_status.rx_overflow_int);
67 SOC_LOGI(" tx_finish_int: %x\n", hw->int_status.tx_finish_int);
68 SOC_LOGI(" rx_finish_int: %x\n", hw->int_status.rx_finish_int);
69 SOC_LOGI(" tx_fifo_clr: %x\n", hw->int_status.tx_fifo_clr);
70 SOC_LOGI(" rx_fifo_clr: %x\n", hw->int_status.rx_fifo_clr);
71
72 SOC_LOGI("\n");
73 SOC_LOGI(" data=0x%x value=0x%x\n", &hw->data, hw->data.v);
74 SOC_LOGI(" fifo_data: %x\n", hw->data.fifo_data);
75 }
76
77 #endif
78
79