1 // Copyright (C) 2022 Beken Corporation
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 /***********************************************************************************************************************************
16 * This file is generated from BK7256_ADDR Mapping_20211224_format_change_highlight_20220113_update.xlsm automatically
17 * Modify it manually is not recommended
18 * CHIP ID:BK7256,GENARATE TIME:2022-01-20 10:15:30
19 ************************************************************************************************************************************/
20
21 #pragma once
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 #include <soc/soc.h>
28
29 #define FFT_LL_REG_BASE (SOC_FFT_REG_BASE) //REG_BASE:0x47000000
30
31 /* REG_0x00 */
32 #define FFT_FFT_CONFIG_ADDR (FFT_LL_REG_BASE + 0x0*4) //REG ADDR :0x47000000
33 #define FFT_FFT_CONFIG_FFT_MODE_POS (0)
34 #define FFT_FFT_CONFIG_FFT_MODE_MASK (0x1)
35
36 #define FFT_FFT_CONFIG_IFFT_POS (1)
37 #define FFT_FFT_CONFIG_IFFT_MASK (0x1)
38
39 #define FFT_FFT_CONFIG_FFT_INT_EN_POS (2)
40 #define FFT_FFT_CONFIG_FFT_INT_EN_MASK (0x1)
41
42 #define FFT_FFT_CONFIG_FFT_ENABLE_POS (3)
43 #define FFT_FFT_CONFIG_FFT_ENABLE_MASK (0x1)
44
45 #define FFT_FFT_CONFIG_FFT_GAT_OFF_POS (4)
46 #define FFT_FFT_CONFIG_FFT_GAT_OFF_MASK (0x1)
47
48 #define FFT_FFT_CONFIG_RESERVED_POS (5)
49 #define FFT_FFT_CONFIG_RESERVED_MASK (0x7FFFFFF)
50
fft_ll_get_fft_config_value(void)51 static inline uint32_t fft_ll_get_fft_config_value(void)
52 {
53 return REG_READ(FFT_FFT_CONFIG_ADDR);
54 }
55
fft_ll_set_fft_config_value(uint32_t value)56 static inline void fft_ll_set_fft_config_value(uint32_t value)
57 {
58 REG_WRITE(FFT_FFT_CONFIG_ADDR,value);
59 }
60
61 /* REG_0x00:fft_config->fft_mode:0x0[0],IFFT模式。 1：BK5130模式 0: 正常模式,0,RW*/
fft_ll_get_fft_config_fft_mode(void)62 static inline uint32_t fft_ll_get_fft_config_fft_mode(void)
63 {
64 uint32_t reg_value;
65 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
66 reg_value = ((reg_value >> FFT_FFT_CONFIG_FFT_MODE_POS) & FFT_FFT_CONFIG_FFT_MODE_MASK);
67 return reg_value;
68 }
69
fft_ll_set_fft_config_fft_mode(uint32_t value)70 static inline void fft_ll_set_fft_config_fft_mode(uint32_t value)
71 {
72 uint32_t reg_value;
73 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
74 reg_value &= ~(FFT_FFT_CONFIG_FFT_MODE_MASK << FFT_FFT_CONFIG_FFT_MODE_POS);
75 reg_value |= ((value & FFT_FFT_CONFIG_FFT_MODE_MASK) << FFT_FFT_CONFIG_FFT_MODE_POS);
76 REG_WRITE(FFT_FFT_CONFIG_ADDR,reg_value);
77 }
78
79 /* REG_0x00:fft_config->ifft:0x0[1],IFFT使能。 1：IFFT运算。 0：FFT运算 ,0,RW*/
fft_ll_get_fft_config_ifft(void)80 static inline uint32_t fft_ll_get_fft_config_ifft(void)
81 {
82 uint32_t reg_value;
83 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
84 reg_value = ((reg_value >> FFT_FFT_CONFIG_IFFT_POS) & FFT_FFT_CONFIG_IFFT_MASK);
85 return reg_value;
86 }
87
fft_ll_set_fft_config_ifft(uint32_t value)88 static inline void fft_ll_set_fft_config_ifft(uint32_t value)
89 {
90 uint32_t reg_value;
91 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
92 reg_value &= ~(FFT_FFT_CONFIG_IFFT_MASK << FFT_FFT_CONFIG_IFFT_POS);
93 reg_value |= ((value & FFT_FFT_CONFIG_IFFT_MASK) << FFT_FFT_CONFIG_IFFT_POS);
94 REG_WRITE(FFT_FFT_CONFIG_ADDR,reg_value);
95 }
96
97 /* REG_0x00:fft_config->fft_int_en:0x0[2],FFT中断使能信号,0,RW*/
fft_ll_get_fft_config_fft_int_en(void)98 static inline uint32_t fft_ll_get_fft_config_fft_int_en(void)
99 {
100 uint32_t reg_value;
101 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
102 reg_value = ((reg_value >> FFT_FFT_CONFIG_FFT_INT_EN_POS) & FFT_FFT_CONFIG_FFT_INT_EN_MASK);
103 return reg_value;
104 }
105
fft_ll_set_fft_config_fft_int_en(uint32_t value)106 static inline void fft_ll_set_fft_config_fft_int_en(uint32_t value)
107 {
108 uint32_t reg_value;
109 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
110 reg_value &= ~(FFT_FFT_CONFIG_FFT_INT_EN_MASK << FFT_FFT_CONFIG_FFT_INT_EN_POS);
111 reg_value |= ((value & FFT_FFT_CONFIG_FFT_INT_EN_MASK) << FFT_FFT_CONFIG_FFT_INT_EN_POS);
112 REG_WRITE(FFT_FFT_CONFIG_ADDR,reg_value);
113 }
114
115 /* REG_0x00:fft_config->fft_enable:0x0[3],FFT使能信号，每次FFT或者IFFT结束后，此信号拉低,0,RW*/
fft_ll_get_fft_config_fft_enable(void)116 static inline uint32_t fft_ll_get_fft_config_fft_enable(void)
117 {
118 uint32_t reg_value;
119 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
120 reg_value = ((reg_value >> FFT_FFT_CONFIG_FFT_ENABLE_POS) & FFT_FFT_CONFIG_FFT_ENABLE_MASK);
121 return reg_value;
122 }
123
fft_ll_set_fft_config_fft_enable(uint32_t value)124 static inline void fft_ll_set_fft_config_fft_enable(uint32_t value)
125 {
126 uint32_t reg_value;
127 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
128 reg_value &= ~(FFT_FFT_CONFIG_FFT_ENABLE_MASK << FFT_FFT_CONFIG_FFT_ENABLE_POS);
129 reg_value |= ((value & FFT_FFT_CONFIG_FFT_ENABLE_MASK) << FFT_FFT_CONFIG_FFT_ENABLE_POS);
130 REG_WRITE(FFT_FFT_CONFIG_ADDR,reg_value);
131 }
132
133 /* REG_0x00:fft_config->fft_gat_off:0x0[4],FFT模块clock gating信号，1 ：gating off 0:gating on ,0,RW*/
fft_ll_get_fft_config_fft_gat_off(void)134 static inline uint32_t fft_ll_get_fft_config_fft_gat_off(void)
135 {
136 uint32_t reg_value;
137 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
138 reg_value = ((reg_value >> FFT_FFT_CONFIG_FFT_GAT_OFF_POS) & FFT_FFT_CONFIG_FFT_GAT_OFF_MASK);
139 return reg_value;
140 }
141
fft_ll_set_fft_config_fft_gat_off(uint32_t value)142 static inline void fft_ll_set_fft_config_fft_gat_off(uint32_t value)
143 {
144 uint32_t reg_value;
145 reg_value = REG_READ(FFT_FFT_CONFIG_ADDR);
146 reg_value &= ~(FFT_FFT_CONFIG_FFT_GAT_OFF_MASK << FFT_FFT_CONFIG_FFT_GAT_OFF_POS);
147 reg_value |= ((value & FFT_FFT_CONFIG_FFT_GAT_OFF_MASK) << FFT_FFT_CONFIG_FFT_GAT_OFF_POS);
148 REG_WRITE(FFT_FFT_CONFIG_ADDR,reg_value);
149 }
150
151 /* REG_0x01 */
152 #define FFT_FIR_CONFIG_ADDR (FFT_LL_REG_BASE + 0x1*4) //REG ADDR :0x47000004
153 #define FFT_FIR_CONFIG_FIR_LENGTH_POS (0)
154 #define FFT_FIR_CONFIG_FIR_LENGTH_MASK (0xFF)
155
156 #define FFT_FIR_CONFIG_FIR_CWIDTH_POS (8)
157 #define FFT_FIR_CONFIG_FIR_CWIDTH_MASK (0x7)
158
159 #define FFT_FIR_CONFIG_FIR_DWIDTH_POS (11)
160 #define FFT_FIR_CONFIG_FIR_DWIDTH_MASK (0x7)
161
162 #define FFT_FIR_CONFIG_FIR_MODE_POS (14)
163 #define FFT_FIR_CONFIG_FIR_MODE_MASK (0x1)
164
165 #define FFT_FIR_CONFIG_FIR_INT_EN_POS (15)
166 #define FFT_FIR_CONFIG_FIR_INT_EN_MASK (0x1)
167
168 #define FFT_FIR_CONFIG_FIR_ENABLE_POS (16)
169 #define FFT_FIR_CONFIG_FIR_ENABLE_MASK (0x1)
170
171 #define FFT_FIR_CONFIG_RESERVED_POS (17)
172 #define FFT_FIR_CONFIG_RESERVED_MASK (0x7FFF)
173
fft_ll_get_fir_config_value(void)174 static inline uint32_t fft_ll_get_fir_config_value(void)
175 {
176 return REG_READ(FFT_FIR_CONFIG_ADDR);
177 }
178
fft_ll_set_fir_config_value(uint32_t value)179 static inline void fft_ll_set_fir_config_value(uint32_t value)
180 {
181 REG_WRITE(FFT_FIR_CONFIG_ADDR,value);
182 }
183
184 /* REG_0x01:fir_config->fir_length:0x1[7:0],FIR的计算点数 fir_length + 1 ,0,RW*/
fft_ll_get_fir_config_fir_length(void)185 static inline uint32_t fft_ll_get_fir_config_fir_length(void)
186 {
187 uint32_t reg_value;
188 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
189 reg_value = ((reg_value >> FFT_FIR_CONFIG_FIR_LENGTH_POS) & FFT_FIR_CONFIG_FIR_LENGTH_MASK);
190 return reg_value;
191 }
192
fft_ll_set_fir_config_fir_length(uint32_t value)193 static inline void fft_ll_set_fir_config_fir_length(uint32_t value)
194 {
195 uint32_t reg_value;
196 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
197 reg_value &= ~(FFT_FIR_CONFIG_FIR_LENGTH_MASK << FFT_FIR_CONFIG_FIR_LENGTH_POS);
198 reg_value |= ((value & FFT_FIR_CONFIG_FIR_LENGTH_MASK) << FFT_FIR_CONFIG_FIR_LENGTH_POS);
199 REG_WRITE(FFT_FIR_CONFIG_ADDR,reg_value);
200 }
201
202 /* REG_0x01:fir_config->fir_cwidth:0x1[10:8],FIR的系数位宽 16 - fir_cwidth,0,RW*/
fft_ll_get_fir_config_fir_cwidth(void)203 static inline uint32_t fft_ll_get_fir_config_fir_cwidth(void)
204 {
205 uint32_t reg_value;
206 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
207 reg_value = ((reg_value >> FFT_FIR_CONFIG_FIR_CWIDTH_POS) & FFT_FIR_CONFIG_FIR_CWIDTH_MASK);
208 return reg_value;
209 }
210
fft_ll_set_fir_config_fir_cwidth(uint32_t value)211 static inline void fft_ll_set_fir_config_fir_cwidth(uint32_t value)
212 {
213 uint32_t reg_value;
214 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
215 reg_value &= ~(FFT_FIR_CONFIG_FIR_CWIDTH_MASK << FFT_FIR_CONFIG_FIR_CWIDTH_POS);
216 reg_value |= ((value & FFT_FIR_CONFIG_FIR_CWIDTH_MASK) << FFT_FIR_CONFIG_FIR_CWIDTH_POS);
217 REG_WRITE(FFT_FIR_CONFIG_ADDR,reg_value);
218 }
219
220 /* REG_0x01:fir_config->fir_dwidth:0x1[13:11],FIR的数据位宽 21 - fir_dwidth,0,RW*/
fft_ll_get_fir_config_fir_dwidth(void)221 static inline uint32_t fft_ll_get_fir_config_fir_dwidth(void)
222 {
223 uint32_t reg_value;
224 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
225 reg_value = ((reg_value >> FFT_FIR_CONFIG_FIR_DWIDTH_POS) & FFT_FIR_CONFIG_FIR_DWIDTH_MASK);
226 return reg_value;
227 }
228
fft_ll_set_fir_config_fir_dwidth(uint32_t value)229 static inline void fft_ll_set_fir_config_fir_dwidth(uint32_t value)
230 {
231 uint32_t reg_value;
232 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
233 reg_value &= ~(FFT_FIR_CONFIG_FIR_DWIDTH_MASK << FFT_FIR_CONFIG_FIR_DWIDTH_POS);
234 reg_value |= ((value & FFT_FIR_CONFIG_FIR_DWIDTH_MASK) << FFT_FIR_CONFIG_FIR_DWIDTH_POS);
235 REG_WRITE(FFT_FIR_CONFIG_ADDR,reg_value);
236 }
237
238 /* REG_0x01:fir_config->fir_mode:0x1[14],FIR的工作模式，1 ：双FIR模式，0：单FIR模式,0,RW*/
fft_ll_get_fir_config_fir_mode(void)239 static inline uint32_t fft_ll_get_fir_config_fir_mode(void)
240 {
241 uint32_t reg_value;
242 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
243 reg_value = ((reg_value >> FFT_FIR_CONFIG_FIR_MODE_POS) & FFT_FIR_CONFIG_FIR_MODE_MASK);
244 return reg_value;
245 }
246
fft_ll_set_fir_config_fir_mode(uint32_t value)247 static inline void fft_ll_set_fir_config_fir_mode(uint32_t value)
248 {
249 uint32_t reg_value;
250 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
251 reg_value &= ~(FFT_FIR_CONFIG_FIR_MODE_MASK << FFT_FIR_CONFIG_FIR_MODE_POS);
252 reg_value |= ((value & FFT_FIR_CONFIG_FIR_MODE_MASK) << FFT_FIR_CONFIG_FIR_MODE_POS);
253 REG_WRITE(FFT_FIR_CONFIG_ADDR,reg_value);
254 }
255
256 /* REG_0x01:fir_config->fir_int_en:0x1[15],FIR的中断使能,0,RW*/
fft_ll_get_fir_config_fir_int_en(void)257 static inline uint32_t fft_ll_get_fir_config_fir_int_en(void)
258 {
259 uint32_t reg_value;
260 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
261 reg_value = ((reg_value >> FFT_FIR_CONFIG_FIR_INT_EN_POS) & FFT_FIR_CONFIG_FIR_INT_EN_MASK);
262 return reg_value;
263 }
264
fft_ll_set_fir_config_fir_int_en(uint32_t value)265 static inline void fft_ll_set_fir_config_fir_int_en(uint32_t value)
266 {
267 uint32_t reg_value;
268 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
269 reg_value &= ~(FFT_FIR_CONFIG_FIR_INT_EN_MASK << FFT_FIR_CONFIG_FIR_INT_EN_POS);
270 reg_value |= ((value & FFT_FIR_CONFIG_FIR_INT_EN_MASK) << FFT_FIR_CONFIG_FIR_INT_EN_POS);
271 REG_WRITE(FFT_FIR_CONFIG_ADDR,reg_value);
272 }
273
274 /* REG_0x01:fir_config->fir_enable:0x1[16],FIR的工作使能 1 ：使能,0,RW*/
fft_ll_get_fir_config_fir_enable(void)275 static inline uint32_t fft_ll_get_fir_config_fir_enable(void)
276 {
277 uint32_t reg_value;
278 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
279 reg_value = ((reg_value >> FFT_FIR_CONFIG_FIR_ENABLE_POS) & FFT_FIR_CONFIG_FIR_ENABLE_MASK);
280 return reg_value;
281 }
282
fft_ll_set_fir_config_fir_enable(uint32_t value)283 static inline void fft_ll_set_fir_config_fir_enable(uint32_t value)
284 {
285 uint32_t reg_value;
286 reg_value = REG_READ(FFT_FIR_CONFIG_ADDR);
287 reg_value &= ~(FFT_FIR_CONFIG_FIR_ENABLE_MASK << FFT_FIR_CONFIG_FIR_ENABLE_POS);
288 reg_value |= ((value & FFT_FIR_CONFIG_FIR_ENABLE_MASK) << FFT_FIR_CONFIG_FIR_ENABLE_POS);
289 REG_WRITE(FFT_FIR_CONFIG_ADDR,reg_value);
290 }
291
292 /* REG_0x02 */
293 #define FFT_DATA_PORTS_ADDR (FFT_LL_REG_BASE + 0x2*4) //REG ADDR :0x47000008
294 #define FFT_DATA_PORTS_DATA_PORT_POS (0)
295 #define FFT_DATA_PORTS_DATA_PORT_MASK (0xFFFFFFFF)
296
fft_ll_get_data_ports_value(void)297 static inline int32 fft_ll_get_data_ports_value(void)
298 {
299 return REG_READ(FFT_DATA_PORTS_ADDR);
300 }
301
fft_ll_set_data_ports_value(int32 value)302 static inline void fft_ll_set_data_ports_value(int32 value)
303 {
304 REG_WRITE(FFT_DATA_PORTS_ADDR,value);
305 }
306
307 /* REG_0x02:data_ports->data_port:0x2[31:0],FIR和FFT的入口地址，写是输入口，读是输出口 {FFT_I,FFT_Q} 31:0 ; {FIR_D1,FIR_D0} 31:0,0,R/W*/
fft_ll_get_data_ports_data_port(void)308 static inline int32 fft_ll_get_data_ports_data_port(void)
309 {
310 return REG_READ(FFT_DATA_PORTS_ADDR);
311 }
312
fft_ll_set_data_ports_data_port(int32 value)313 static inline void fft_ll_set_data_ports_data_port(int32 value)
314 {
315 REG_WRITE(FFT_DATA_PORTS_ADDR,value);
316 }
317
318 /* REG_0x03 */
319 #define FFT_COEF_PORTS_ADDR (FFT_LL_REG_BASE + 0x3*4) //REG ADDR :0x4700000c
320 #define FFT_COEF_PORTS_COEF_PORT_POS (0)
321 #define FFT_COEF_PORTS_COEF_PORT_MASK (0xFFFFFFFF)
322
fft_ll_set_coef_ports_value(int32 value)323 static inline void fft_ll_set_coef_ports_value(int32 value)
324 {
325 REG_WRITE(FFT_COEF_PORTS_ADDR,value);
326 }
327
328 /* REG_0x03:coef_ports->coef_port:0x3[31:0],FIR 系数的入口地址 {FIR_C1, FIR_C0} 31:0,0,WO*/
fft_ll_set_coef_ports_coef_port(int32 value)329 static inline void fft_ll_set_coef_ports_coef_port(int32 value)
330 {
331 REG_WRITE(FFT_COEF_PORTS_ADDR,value);
332 }
333
334 /* REG_0x04 */
335 #define FFT_MAC_REULT1_ADDR (FFT_LL_REG_BASE + 0x4*4) //REG ADDR :0x47000010
336 #define FFT_MAC_REULT1_MAC_RESULT_POS (0)
337 #define FFT_MAC_REULT1_MAC_RESULT_MASK (0xFFFFFFFF)
338
fft_ll_get_mac_reult1_value(void)339 static inline uint32_t fft_ll_get_mac_reult1_value(void)
340 {
341 return REG_READ(FFT_MAC_REULT1_ADDR);
342 }
343
344 /* REG_0x04:mac_reult1->mac_result:0x4[31:0],MAC 结果输出 ,0,RO*/
fft_ll_get_mac_reult1_mac_result(void)345 static inline uint32_t fft_ll_get_mac_reult1_mac_result(void)
346 {
347 return REG_READ(FFT_MAC_REULT1_ADDR);
348 }
349
350 /* REG_0x05 */
351 #define FFT_MAC_REULT2_ADDR (FFT_LL_REG_BASE + 0x5*4) //REG ADDR :0x47000014
352 #define FFT_MAC_REULT2_MAC_RESULT_POS (0)
353 #define FFT_MAC_REULT2_MAC_RESULT_MASK (0xFFF)
354
355 #define FFT_MAC_REULT2_RESERVED_POS (12)
356 #define FFT_MAC_REULT2_RESERVED_MASK (0xFFFFF)
357
fft_ll_get_mac_reult2_value(void)358 static inline uint32_t fft_ll_get_mac_reult2_value(void)
359 {
360 return REG_READ(FFT_MAC_REULT2_ADDR);
361 }
362
363 /* REG_0x05:mac_reult2->mac_result:0x5[11:0],,MAC 结果输出 ,0,RO*/
fft_ll_get_mac_reult2_mac_result(void)364 static inline uint32_t fft_ll_get_mac_reult2_mac_result(void)
365 {
366 uint32_t reg_value;
367 reg_value = REG_READ(FFT_MAC_REULT2_ADDR);
368 reg_value = ((reg_value >> FFT_MAC_REULT2_MAC_RESULT_POS)&FFT_MAC_REULT2_MAC_RESULT_MASK);
369 return reg_value;
370 }
371
372 /* REG_0x06 */
373 #define FFT_STATUS_ADDR (FFT_LL_REG_BASE + 0x6*4) //REG ADDR :0x47000018
374 #define FFT_STATUS_FFT_DONE_POS (0)
375 #define FFT_STATUS_FFT_DONE_MASK (0x1)
376
377 #define FFT_STATUS_FIR_DONE_POS (1)
378 #define FFT_STATUS_FIR_DONE_MASK (0x1)
379
380 #define FFT_STATUS_SELF_PROC_DONE_POS (2)
381 #define FFT_STATUS_SELF_PROC_DONE_MASK (0x1)
382
383 #define FFT_STATUS_RESERVED_POS (3)
384 #define FFT_STATUS_RESERVED_MASK (0xF)
385
386 #define FFT_STATUS_BIT_EXT_POS (7)
387 #define FFT_STATUS_BIT_EXT_MASK (0x3F)
388
389 #define FFT_STATUS_RESERVED1_POS (13)
390 #define FFT_STATUS_RESERVED1_MASK (0x7FFFF)
391
fft_ll_get_status_value(void)392 static inline uint32_t fft_ll_get_status_value(void)
393 {
394 return REG_READ(FFT_STATUS_ADDR);
395 }
396
fft_ll_set_status_value(uint32_t value)397 static inline void fft_ll_set_status_value(uint32_t value)
398 {
399 REG_WRITE(FFT_STATUS_ADDR,value);
400 }
401
402 /* REG_0x06:status->fft_done:0x6[0],FFT 结束指示标志, 一旦启动读结果，自动清零,0,RW*/
fft_ll_get_status_fft_done(void)403 static inline uint32_t fft_ll_get_status_fft_done(void)
404 {
405 uint32_t reg_value;
406 reg_value = REG_READ(FFT_STATUS_ADDR);
407 reg_value = ((reg_value >> FFT_STATUS_FFT_DONE_POS) & FFT_STATUS_FFT_DONE_MASK);
408 return reg_value;
409 }
410
fft_ll_set_status_fft_done(uint32_t value)411 static inline void fft_ll_set_status_fft_done(uint32_t value)
412 {
413 uint32_t reg_value;
414 reg_value = REG_READ(FFT_STATUS_ADDR);
415 reg_value &= ~(FFT_STATUS_FFT_DONE_MASK << FFT_STATUS_FFT_DONE_POS);
416 reg_value |= ((value & FFT_STATUS_FFT_DONE_MASK) << FFT_STATUS_FFT_DONE_POS);
417 REG_WRITE(FFT_STATUS_ADDR,reg_value);
418 }
419
420 /* REG_0x06:status->fir_done:0x6[1],FIR 结束指示标志, 一旦启动读结果，自动清零,0,RW*/
fft_ll_get_status_fir_done(void)421 static inline uint32_t fft_ll_get_status_fir_done(void)
422 {
423 uint32_t reg_value;
424 reg_value = REG_READ(FFT_STATUS_ADDR);
425 reg_value = ((reg_value >> FFT_STATUS_FIR_DONE_POS) & FFT_STATUS_FIR_DONE_MASK);
426 return reg_value;
427 }
428
fft_ll_set_status_fir_done(uint32_t value)429 static inline void fft_ll_set_status_fir_done(uint32_t value)
430 {
431 uint32_t reg_value;
432 reg_value = REG_READ(FFT_STATUS_ADDR);
433 reg_value &= ~(FFT_STATUS_FIR_DONE_MASK << FFT_STATUS_FIR_DONE_POS);
434 reg_value |= ((value & FFT_STATUS_FIR_DONE_MASK) << FFT_STATUS_FIR_DONE_POS);
435 REG_WRITE(FFT_STATUS_ADDR,reg_value);
436 }
437
438 /* REG_0x06:status->self_proc_done:0x6[2],自相关处理结束指示标志, 一旦启动读结果，自动清零,0,RW*/
fft_ll_get_status_self_proc_done(void)439 static inline uint32_t fft_ll_get_status_self_proc_done(void)
440 {
441 uint32_t reg_value;
442 reg_value = REG_READ(FFT_STATUS_ADDR);
443 reg_value = ((reg_value >> FFT_STATUS_SELF_PROC_DONE_POS) & FFT_STATUS_SELF_PROC_DONE_MASK);
444 return reg_value;
445 }
446
fft_ll_set_status_self_proc_done(uint32_t value)447 static inline void fft_ll_set_status_self_proc_done(uint32_t value)
448 {
449 uint32_t reg_value;
450 reg_value = REG_READ(FFT_STATUS_ADDR);
451 reg_value &= ~(FFT_STATUS_SELF_PROC_DONE_MASK << FFT_STATUS_SELF_PROC_DONE_POS);
452 reg_value |= ((value & FFT_STATUS_SELF_PROC_DONE_MASK) << FFT_STATUS_SELF_PROC_DONE_POS);
453 REG_WRITE(FFT_STATUS_ADDR,reg_value);
454 }
455
456 /* REG_0x06:status->bit_ext:0x6[12:7],FFT输出扩展标志，2的补码格式，如果为正数。需要在输出缩小2^bit_ext倍数。,0,RW*/
fft_ll_get_status_bit_ext(void)457 static inline uint32_t fft_ll_get_status_bit_ext(void)
458 {
459 uint32_t reg_value;
460 reg_value = REG_READ(FFT_STATUS_ADDR);
461 reg_value = ((reg_value >> FFT_STATUS_BIT_EXT_POS) & FFT_STATUS_BIT_EXT_MASK);
462 return reg_value;
463 }
464
fft_ll_set_status_bit_ext(uint32_t value)465 static inline void fft_ll_set_status_bit_ext(uint32_t value)
466 {
467 uint32_t reg_value;
468 reg_value = REG_READ(FFT_STATUS_ADDR);
469 reg_value &= ~(FFT_STATUS_BIT_EXT_MASK << FFT_STATUS_BIT_EXT_POS);
470 reg_value |= ((value & FFT_STATUS_BIT_EXT_MASK) << FFT_STATUS_BIT_EXT_POS);
471 REG_WRITE(FFT_STATUS_ADDR,reg_value);
472 }
473
474 /* REG_0x07 */
475 #define FFT_START_TRIGGER_ADDR (FFT_LL_REG_BASE + 0x7*4) //REG ADDR :0x4700001c
476 #define FFT_START_TRIGGER_START_TRIGGER_POS (0)
477 #define FFT_START_TRIGGER_START_TRIGGER_MASK (0x1)
478
479 #define FFT_START_TRIGGER_RESERVED_POS (1)
480 #define FFT_START_TRIGGER_RESERVED_MASK (0x7FFFFFFF)
481
fft_ll_get_start_trigger_value(void)482 static inline uint32_t fft_ll_get_start_trigger_value(void)
483 {
484 return REG_READ(FFT_START_TRIGGER_ADDR);
485 }
486
fft_ll_set_start_trigger_value(uint32_t value)487 static inline void fft_ll_set_start_trigger_value(uint32_t value)
488 {
489 REG_WRITE(FFT_START_TRIGGER_ADDR,value);
490 }
491
492 /* REG_0x07:start_trigger->start_trigger:0x7[0],写1有效，触发内核工作，并自动清零。,0,RW*/
fft_ll_get_start_trigger_start_trigger(void)493 static inline uint32_t fft_ll_get_start_trigger_start_trigger(void)
494 {
495 uint32_t reg_value;
496 reg_value = REG_READ(FFT_START_TRIGGER_ADDR);
497 reg_value = ((reg_value >> FFT_START_TRIGGER_START_TRIGGER_POS) & FFT_START_TRIGGER_START_TRIGGER_MASK);
498 return reg_value;
499 }
500
fft_ll_set_start_trigger_start_trigger(uint32_t value)501 static inline void fft_ll_set_start_trigger_start_trigger(uint32_t value)
502 {
503 uint32_t reg_value;
504 reg_value = REG_READ(FFT_START_TRIGGER_ADDR);
505 reg_value &= ~(FFT_START_TRIGGER_START_TRIGGER_MASK << FFT_START_TRIGGER_START_TRIGGER_POS);
506 reg_value |= ((value & FFT_START_TRIGGER_START_TRIGGER_MASK) << FFT_START_TRIGGER_START_TRIGGER_POS);
507 REG_WRITE(FFT_START_TRIGGER_ADDR,reg_value);
508 }
509
510 /* REG_0x08 */
511 #define FFT_SELF_CONFIG_ADDR (FFT_LL_REG_BASE + 0x8*4) //REG ADDR :0x47000020
512 #define FFT_SELF_CONFIG_ANA_LEN_POS (0)
513 #define FFT_SELF_CONFIG_ANA_LEN_MASK (0xFF)
514
515 #define FFT_SELF_CONFIG_LPC_LEN_POS (8)
516 #define FFT_SELF_CONFIG_LPC_LEN_MASK (0xFF)
517
518 #define FFT_SELF_CONFIG_ROUND_BIT_IDX_POS (16)
519 #define FFT_SELF_CONFIG_ROUND_BIT_IDX_MASK (0x1F)
520
521 #define FFT_SELF_CONFIG_RESERVED_POS (21)
522 #define FFT_SELF_CONFIG_RESERVED_MASK (0x7)
523
524 #define FFT_SELF_CONFIG_SELF_PROC_MODE_POS (24)
525 #define FFT_SELF_CONFIG_SELF_PROC_MODE_MASK (0x1)
526
527 #define FFT_SELF_CONFIG_RESERVED1_POS (25)
528 #define FFT_SELF_CONFIG_RESERVED1_MASK (0x7)
529
530 #define FFT_SELF_CONFIG_SELF_ENABLE_POS (28)
531 #define FFT_SELF_CONFIG_SELF_ENABLE_MASK (0x1)
532
533 #define FFT_SELF_CONFIG_RESERVED2_POS (29)
534 #define FFT_SELF_CONFIG_RESERVED2_MASK (0x7)
535
fft_ll_get_self_config_value(void)536 static inline uint32_t fft_ll_get_self_config_value(void)
537 {
538 return REG_READ(FFT_SELF_CONFIG_ADDR);
539 }
540
fft_ll_set_self_config_value(uint32_t value)541 static inline void fft_ll_set_self_config_value(uint32_t value)
542 {
543 REG_WRITE(FFT_SELF_CONFIG_ADDR,value);
544 }
545
546 /* REG_0x08:self_config->ana_len:0x8[7:0],输入数据长度,0,RW*/
fft_ll_get_self_config_ana_len(void)547 static inline uint32_t fft_ll_get_self_config_ana_len(void)
548 {
549 uint32_t reg_value;
550 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
551 reg_value = ((reg_value >> FFT_SELF_CONFIG_ANA_LEN_POS) & FFT_SELF_CONFIG_ANA_LEN_MASK);
552 return reg_value;
553 }
554
fft_ll_set_self_config_ana_len(uint32_t value)555 static inline void fft_ll_set_self_config_ana_len(uint32_t value)
556 {
557 uint32_t reg_value;
558 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
559 reg_value &= ~(FFT_SELF_CONFIG_ANA_LEN_MASK << FFT_SELF_CONFIG_ANA_LEN_POS);
560 reg_value |= ((value & FFT_SELF_CONFIG_ANA_LEN_MASK) << FFT_SELF_CONFIG_ANA_LEN_POS);
561 REG_WRITE(FFT_SELF_CONFIG_ADDR,reg_value);
562 }
563
564 /* REG_0x08:self_config->lpc_len:0x8[15:8],LPC_LEN长度,0,RW*/
fft_ll_get_self_config_lpc_len(void)565 static inline uint32_t fft_ll_get_self_config_lpc_len(void)
566 {
567 uint32_t reg_value;
568 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
569 reg_value = ((reg_value >> FFT_SELF_CONFIG_LPC_LEN_POS) & FFT_SELF_CONFIG_LPC_LEN_MASK);
570 return reg_value;
571 }
572
fft_ll_set_self_config_lpc_len(uint32_t value)573 static inline void fft_ll_set_self_config_lpc_len(uint32_t value)
574 {
575 uint32_t reg_value;
576 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
577 reg_value &= ~(FFT_SELF_CONFIG_LPC_LEN_MASK << FFT_SELF_CONFIG_LPC_LEN_POS);
578 reg_value |= ((value & FFT_SELF_CONFIG_LPC_LEN_MASK) << FFT_SELF_CONFIG_LPC_LEN_POS);
579 REG_WRITE(FFT_SELF_CONFIG_ADDR,reg_value);
580 }
581
582 /* REG_0x08:self_config->round_bit_idx:0x8[20:16],自相关累加结果需要round的比特数,0,RW*/
fft_ll_get_self_config_round_bit_idx(void)583 static inline uint32_t fft_ll_get_self_config_round_bit_idx(void)
584 {
585 uint32_t reg_value;
586 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
587 reg_value = ((reg_value >> FFT_SELF_CONFIG_ROUND_BIT_IDX_POS) & FFT_SELF_CONFIG_ROUND_BIT_IDX_MASK);
588 return reg_value;
589 }
590
fft_ll_set_self_config_round_bit_idx(uint32_t value)591 static inline void fft_ll_set_self_config_round_bit_idx(uint32_t value)
592 {
593 uint32_t reg_value;
594 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
595 reg_value &= ~(FFT_SELF_CONFIG_ROUND_BIT_IDX_MASK << FFT_SELF_CONFIG_ROUND_BIT_IDX_POS);
596 reg_value |= ((value & FFT_SELF_CONFIG_ROUND_BIT_IDX_MASK) << FFT_SELF_CONFIG_ROUND_BIT_IDX_POS);
597 REG_WRITE(FFT_SELF_CONFIG_ADDR,reg_value);
598 }
599
600 /* REG_0x08:self_config->self_proc_mode:0x8[24],自相关处理模式选择,0,RW*/
fft_ll_get_self_config_self_proc_mode(void)601 static inline uint32_t fft_ll_get_self_config_self_proc_mode(void)
602 {
603 uint32_t reg_value;
604 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
605 reg_value = ((reg_value >> FFT_SELF_CONFIG_SELF_PROC_MODE_POS) & FFT_SELF_CONFIG_SELF_PROC_MODE_MASK);
606 return reg_value;
607 }
608
fft_ll_set_self_config_self_proc_mode(uint32_t value)609 static inline void fft_ll_set_self_config_self_proc_mode(uint32_t value)
610 {
611 uint32_t reg_value;
612 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
613 reg_value &= ~(FFT_SELF_CONFIG_SELF_PROC_MODE_MASK << FFT_SELF_CONFIG_SELF_PROC_MODE_POS);
614 reg_value |= ((value & FFT_SELF_CONFIG_SELF_PROC_MODE_MASK) << FFT_SELF_CONFIG_SELF_PROC_MODE_POS);
615 REG_WRITE(FFT_SELF_CONFIG_ADDR,reg_value);
616 }
617
618 /* REG_0x08:self_config->self_enable:0x8[28],自相关工作使能. 0:不使能;1:使能,0,RW*/
fft_ll_get_self_config_self_enable(void)619 static inline uint32_t fft_ll_get_self_config_self_enable(void)
620 {
621 uint32_t reg_value;
622 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
623 reg_value = ((reg_value >> FFT_SELF_CONFIG_SELF_ENABLE_POS) & FFT_SELF_CONFIG_SELF_ENABLE_MASK);
624 return reg_value;
625 }
626
fft_ll_set_self_config_self_enable(uint32_t value)627 static inline void fft_ll_set_self_config_self_enable(uint32_t value)
628 {
629 uint32_t reg_value;
630 reg_value = REG_READ(FFT_SELF_CONFIG_ADDR);
631 reg_value &= ~(FFT_SELF_CONFIG_SELF_ENABLE_MASK << FFT_SELF_CONFIG_SELF_ENABLE_POS);
632 reg_value |= ((value & FFT_SELF_CONFIG_SELF_ENABLE_MASK) << FFT_SELF_CONFIG_SELF_ENABLE_POS);
633 REG_WRITE(FFT_SELF_CONFIG_ADDR,reg_value);
634 }
635
636 /* REG_0x09 */
637 #define FFT_MEMORY_CONFIG_ADDR (FFT_LL_REG_BASE + 0x9*4) //REG ADDR :0x47000024
638 #define FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_POS (0)
639 #define FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_MASK (0x1)
640
641 #define FFT_MEMORY_CONFIG_RESERVED_POS (1)
642 #define FFT_MEMORY_CONFIG_RESERVED_MASK (0x7FFFFFFF)
643
fft_ll_get_memory_config_value(void)644 static inline uint32_t fft_ll_get_memory_config_value(void)
645 {
646 return REG_READ(FFT_MEMORY_CONFIG_ADDR);
647 }
648
fft_ll_set_memory_config_value(uint32_t value)649 static inline void fft_ll_set_memory_config_value(uint32_t value)
650 {
651 REG_WRITE(FFT_MEMORY_CONFIG_ADDR,value);
652 }
653
654 /* REG_0x09:memory_config->memory_config_mode:0x9[0],Memory0和Memory1软件配置方式.; 0:Memory0和Memory1软件分别配置;; 1:在fft_enable/fir_enable/self_enable都不使能的情况下,Memory0和Memory1软件同时配置.,0,RW*/
fft_ll_get_memory_config_memory_config_mode(void)655 static inline uint32_t fft_ll_get_memory_config_memory_config_mode(void)
656 {
657 uint32_t reg_value;
658 reg_value = REG_READ(FFT_MEMORY_CONFIG_ADDR);
659 reg_value = ((reg_value >> FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_POS) & FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_MASK);
660 return reg_value;
661 }
662
fft_ll_set_memory_config_memory_config_mode(uint32_t value)663 static inline void fft_ll_set_memory_config_memory_config_mode(uint32_t value)
664 {
665 uint32_t reg_value;
666 reg_value = REG_READ(FFT_MEMORY_CONFIG_ADDR);
667 reg_value &= ~(FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_MASK << FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_POS);
668 reg_value |= ((value & FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_MASK) << FFT_MEMORY_CONFIG_MEMORY_CONFIG_MODE_POS);
669 REG_WRITE(FFT_MEMORY_CONFIG_ADDR,reg_value);
670 }
671
672 #ifdef __cplusplus
673 }
674 #endif
675