1 /* 2 * Copyright (c) 2022 Huawei Device Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef HI3516_AIAO_IMPL_H 20 #define HI3516_AIAO_IMPL_H 21 22 #include <linux/types.h> 23 #include "audio_platform_base.h" 24 25 /* AIO base address */ 26 #define AIAO_REG_BASE 0x113b0000 27 #define AIAO_MAX_REG_SIZE 0x10000 28 29 #define AOP_BUFF_WPTR_REG 0x2088 30 #define AOP_BUFF_RPTR_REG 0x208C 31 #define AIP_BUFF_WPTR_REG 0x1088 32 #define OFFSET_MULTL 8 33 34 typedef enum { 35 HI_FALSE = 0, 36 HI_TRUE = 1, 37 } HiBool; 38 39 typedef enum { 40 AUDIO_BIT_WIDTH_8 = 0, /* 8bit width */ 41 AUDIO_BIT_WIDTH_16 = 1, /* 16bit width */ 42 AUDIO_BIT_WIDTH_24 = 2, /* 24bit width */ 43 AUDIO_BIT_WIDTH_BUTT, 44 } AudioBitWidth; 45 46 typedef struct { 47 bool clkSelect; 48 /* 256fs */ 49 unsigned int mclkDiv48k256fs; 50 unsigned int mclkDiv441k256fs; 51 unsigned int mclkDiv32k256fs; 52 /* 320fs */ 53 unsigned int mclkDiv48k320fs; 54 unsigned int mclkDiv441k320fs; 55 unsigned int mclkDiv32k320fs; 56 } AiaoClkInfo; 57 58 // define the union u_rx_dsp_ctrl 59 typedef union { 60 struct { 61 unsigned int reserved0 : 28; // [27..0] 62 unsigned int rxEnable : 1; // [28] 63 unsigned int rxDisableDone : 1; // [29] 64 unsigned int reserved1 : 2; // [31..30] 65 } Bits; 66 unsigned int u32; 67 } URxDspCtrl; 68 69 typedef union { 70 struct { 71 unsigned int reserved0 : 8; // [7..0] 72 unsigned int volume : 7; // [14..8] 73 unsigned int reserved1 : 13; // [27..15] 74 unsigned int txEnable : 1; // [28] 75 unsigned int reserved2 : 3; // [31..29] 76 } Bits; 77 unsigned int u32; 78 } UTxDspCtrl; 79 80 // define the union u_tx_buff_rptr 81 typedef union { 82 struct { 83 unsigned int txBuffRptr : 24; // [23..0] 84 unsigned int reserved0 : 8; // [31..24] 85 } Bits; 86 unsigned int u32; 87 } UTxBuffRptr; 88 89 typedef union { 90 struct { 91 unsigned int txBuffWptr : 24; // [23..0] 92 unsigned int reserved0 : 8; // [31..24] 93 } Bits; 94 unsigned int u32; 95 } UTxBuffWptr; 96 97 typedef union { 98 struct { 99 unsigned int txBuffSize : 24; // [23..0] 100 unsigned int reserved0 : 8; // [31..24] 101 } Bits; 102 unsigned int u32; 103 } UTxBuffSize; 104 105 typedef union { 106 struct { 107 unsigned int txTransSize : 24; // [23..0] 108 unsigned int reserved0 : 8; // [31..24] 109 } Bits; 110 unsigned int u32; 111 } UTxTransSize; 112 113 uint32_t AiopRegCfg(const int reg, const int offset, uint32_t n); 114 int32_t AiaoHalSysInit(void); 115 int32_t AiaoClockReset(void); 116 uint32_t AiaoHalReadReg(uint32_t offset); 117 int32_t AopHalSetBuffRptr(uint32_t chnId, uint32_t value); 118 int32_t AopHalSetBuffWptr(uint32_t chnId, uint32_t value); 119 int32_t AipHalSetBuffWptr(uint32_t chnId, uint32_t value); 120 int32_t AipHalSetBuffRptr(uint32_t chnId, uint32_t value); 121 int32_t AopHalSetTxStart(uint32_t chnId, bool en); 122 int32_t AipHalSetRxStart(uint32_t chnId, bool en); 123 int32_t AopHalDevEnable(uint32_t chnId); 124 int32_t AiaoDeviceInit(uint32_t chnId); 125 int32_t AudioAoInit(const struct PlatformData *platformData); 126 int32_t AudioAiInit(const struct PlatformData *platformData); 127 int32_t AiaoSysPinMux(void); 128 int32_t AiaoRxIntClr(uint32_t chnId); 129 int32_t AiaoGetMclk(uint32_t rate, uint32_t *mclkSel); 130 int32_t AiaoSetSysCtlRegValue(uint32_t mclkSel, uint32_t bitWidth, 131 uint32_t rate, uint32_t *clkRegVal); 132 #endif // __HI3516_ACODEC_H__ 133