1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_HALL_H 10 #define HPM_HALL_H 11 12 typedef struct { 13 __RW uint32_t CR; /* 0x0: Control Register */ 14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ 15 __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ 16 __RW uint32_t UVWCFG; /* 0xC: U,V,W configure register */ 17 __RW uint32_t TRGOEN; /* 0x10: Trigger output enable register */ 18 __RW uint32_t READEN; /* 0x14: Read event enable register */ 19 __R uint8_t RESERVED0[12]; /* 0x18 - 0x23: Reserved */ 20 __RW uint32_t DMAEN; /* 0x24: DMA enable register */ 21 __RW uint32_t SR; /* 0x28: Status register */ 22 __RW uint32_t IRQEN; /* 0x2C: Interrupt request enable register */ 23 struct { 24 __R uint32_t W; /* 0x30: W counter */ 25 __R uint32_t V; /* 0x34: V counter */ 26 __R uint32_t U; /* 0x38: U counter */ 27 __R uint32_t TMR; /* 0x3C: Timer counter */ 28 } COUNT[4]; 29 struct { 30 __R uint32_t HIS0; /* 0x70: history register 0 */ 31 __R uint32_t HIS1; /* 0x74: history register 1 */ 32 } HIS[3]; 33 } HALL_Type; 34 35 36 /* Bitfield definition for register: CR */ 37 /* 38 * READ (WO) 39 * 40 * 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 41 */ 42 #define HALL_CR_READ_MASK (0x80000000UL) 43 #define HALL_CR_READ_SHIFT (31U) 44 #define HALL_CR_READ_SET(x) (((uint32_t)(x) << HALL_CR_READ_SHIFT) & HALL_CR_READ_MASK) 45 #define HALL_CR_READ_GET(x) (((uint32_t)(x) & HALL_CR_READ_MASK) >> HALL_CR_READ_SHIFT) 46 47 /* 48 * SNAPEN (RW) 49 * 50 * 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert 51 */ 52 #define HALL_CR_SNAPEN_MASK (0x800U) 53 #define HALL_CR_SNAPEN_SHIFT (11U) 54 #define HALL_CR_SNAPEN_SET(x) (((uint32_t)(x) << HALL_CR_SNAPEN_SHIFT) & HALL_CR_SNAPEN_MASK) 55 #define HALL_CR_SNAPEN_GET(x) (((uint32_t)(x) & HALL_CR_SNAPEN_MASK) >> HALL_CR_SNAPEN_SHIFT) 56 57 /* 58 * RSTCNT (RW) 59 * 60 * set to reset all counter and related snapshots 61 */ 62 #define HALL_CR_RSTCNT_MASK (0x10U) 63 #define HALL_CR_RSTCNT_SHIFT (4U) 64 #define HALL_CR_RSTCNT_SET(x) (((uint32_t)(x) << HALL_CR_RSTCNT_SHIFT) & HALL_CR_RSTCNT_MASK) 65 #define HALL_CR_RSTCNT_GET(x) (((uint32_t)(x) & HALL_CR_RSTCNT_MASK) >> HALL_CR_RSTCNT_SHIFT) 66 67 /* Bitfield definition for register: PHCFG */ 68 /* 69 * DLYSEL (RW) 70 * 71 * This bit select delay start time: 72 * 1- start counting delay after pre-trigger 73 * 0- start counting delay after u,v,w toggle 74 */ 75 #define HALL_PHCFG_DLYSEL_MASK (0x80000000UL) 76 #define HALL_PHCFG_DLYSEL_SHIFT (31U) 77 #define HALL_PHCFG_DLYSEL_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYSEL_SHIFT) & HALL_PHCFG_DLYSEL_MASK) 78 #define HALL_PHCFG_DLYSEL_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYSEL_MASK) >> HALL_PHCFG_DLYSEL_SHIFT) 79 80 /* 81 * DLYCNT (RW) 82 * 83 * delay clock cycles number 84 */ 85 #define HALL_PHCFG_DLYCNT_MASK (0xFFFFFFUL) 86 #define HALL_PHCFG_DLYCNT_SHIFT (0U) 87 #define HALL_PHCFG_DLYCNT_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYCNT_SHIFT) & HALL_PHCFG_DLYCNT_MASK) 88 #define HALL_PHCFG_DLYCNT_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYCNT_MASK) >> HALL_PHCFG_DLYCNT_SHIFT) 89 90 /* Bitfield definition for register: WDGCFG */ 91 /* 92 * WDGEN (RW) 93 * 94 * 1- enable wdog counter 95 */ 96 #define HALL_WDGCFG_WDGEN_MASK (0x80000000UL) 97 #define HALL_WDGCFG_WDGEN_SHIFT (31U) 98 #define HALL_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGEN_SHIFT) & HALL_WDGCFG_WDGEN_MASK) 99 #define HALL_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGEN_MASK) >> HALL_WDGCFG_WDGEN_SHIFT) 100 101 /* 102 * WDGTO (RW) 103 * 104 * watch dog timeout value 105 */ 106 #define HALL_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) 107 #define HALL_WDGCFG_WDGTO_SHIFT (0U) 108 #define HALL_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGTO_SHIFT) & HALL_WDGCFG_WDGTO_MASK) 109 #define HALL_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGTO_MASK) >> HALL_WDGCFG_WDGTO_SHIFT) 110 111 /* Bitfield definition for register: UVWCFG */ 112 /* 113 * PRECNT (RW) 114 * 115 * the clock cycle number which the pre flag will set before the next uvw transition 116 */ 117 #define HALL_UVWCFG_PRECNT_MASK (0xFFFFFFUL) 118 #define HALL_UVWCFG_PRECNT_SHIFT (0U) 119 #define HALL_UVWCFG_PRECNT_SET(x) (((uint32_t)(x) << HALL_UVWCFG_PRECNT_SHIFT) & HALL_UVWCFG_PRECNT_MASK) 120 #define HALL_UVWCFG_PRECNT_GET(x) (((uint32_t)(x) & HALL_UVWCFG_PRECNT_MASK) >> HALL_UVWCFG_PRECNT_SHIFT) 121 122 /* Bitfield definition for register: TRGOEN */ 123 /* 124 * WDGEN (RW) 125 * 126 * 1- enable trigger output when wdg flag set 127 */ 128 #define HALL_TRGOEN_WDGEN_MASK (0x80000000UL) 129 #define HALL_TRGOEN_WDGEN_SHIFT (31U) 130 #define HALL_TRGOEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WDGEN_SHIFT) & HALL_TRGOEN_WDGEN_MASK) 131 #define HALL_TRGOEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WDGEN_MASK) >> HALL_TRGOEN_WDGEN_SHIFT) 132 133 /* 134 * PHUPTEN (RW) 135 * 136 * 1- enable trigger output when phupt flag set 137 */ 138 #define HALL_TRGOEN_PHUPTEN_MASK (0x40000000UL) 139 #define HALL_TRGOEN_PHUPTEN_SHIFT (30U) 140 #define HALL_TRGOEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHUPTEN_SHIFT) & HALL_TRGOEN_PHUPTEN_MASK) 141 #define HALL_TRGOEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHUPTEN_MASK) >> HALL_TRGOEN_PHUPTEN_SHIFT) 142 143 /* 144 * PHPREEN (RW) 145 * 146 * 1- enable trigger output when phpre flag set 147 */ 148 #define HALL_TRGOEN_PHPREEN_MASK (0x20000000UL) 149 #define HALL_TRGOEN_PHPREEN_SHIFT (29U) 150 #define HALL_TRGOEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHPREEN_SHIFT) & HALL_TRGOEN_PHPREEN_MASK) 151 #define HALL_TRGOEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHPREEN_MASK) >> HALL_TRGOEN_PHPREEN_SHIFT) 152 153 /* 154 * PHDLYEN (RW) 155 * 156 * 1- enable trigger output when phdly flag set 157 */ 158 #define HALL_TRGOEN_PHDLYEN_MASK (0x10000000UL) 159 #define HALL_TRGOEN_PHDLYEN_SHIFT (28U) 160 #define HALL_TRGOEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHDLYEN_SHIFT) & HALL_TRGOEN_PHDLYEN_MASK) 161 #define HALL_TRGOEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHDLYEN_MASK) >> HALL_TRGOEN_PHDLYEN_SHIFT) 162 163 /* 164 * UFEN (RW) 165 * 166 * 1- enable trigger output when u flag set 167 */ 168 #define HALL_TRGOEN_UFEN_MASK (0x800000UL) 169 #define HALL_TRGOEN_UFEN_SHIFT (23U) 170 #define HALL_TRGOEN_UFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_UFEN_SHIFT) & HALL_TRGOEN_UFEN_MASK) 171 #define HALL_TRGOEN_UFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_UFEN_MASK) >> HALL_TRGOEN_UFEN_SHIFT) 172 173 /* 174 * VFEN (RW) 175 * 176 * 1- enable trigger output when v flag set 177 */ 178 #define HALL_TRGOEN_VFEN_MASK (0x400000UL) 179 #define HALL_TRGOEN_VFEN_SHIFT (22U) 180 #define HALL_TRGOEN_VFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_VFEN_SHIFT) & HALL_TRGOEN_VFEN_MASK) 181 #define HALL_TRGOEN_VFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_VFEN_MASK) >> HALL_TRGOEN_VFEN_SHIFT) 182 183 /* 184 * WFEN (RW) 185 * 186 * 1- enable trigger output when w flag set 187 */ 188 #define HALL_TRGOEN_WFEN_MASK (0x200000UL) 189 #define HALL_TRGOEN_WFEN_SHIFT (21U) 190 #define HALL_TRGOEN_WFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WFEN_SHIFT) & HALL_TRGOEN_WFEN_MASK) 191 #define HALL_TRGOEN_WFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WFEN_MASK) >> HALL_TRGOEN_WFEN_SHIFT) 192 193 /* Bitfield definition for register: READEN */ 194 /* 195 * WDGEN (RW) 196 * 197 * 1- load counters to their read registers when wdg flag set 198 */ 199 #define HALL_READEN_WDGEN_MASK (0x80000000UL) 200 #define HALL_READEN_WDGEN_SHIFT (31U) 201 #define HALL_READEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_READEN_WDGEN_SHIFT) & HALL_READEN_WDGEN_MASK) 202 #define HALL_READEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_READEN_WDGEN_MASK) >> HALL_READEN_WDGEN_SHIFT) 203 204 /* 205 * PHUPTEN (RW) 206 * 207 * 1- load counters to their read registers when phupt flag set 208 */ 209 #define HALL_READEN_PHUPTEN_MASK (0x40000000UL) 210 #define HALL_READEN_PHUPTEN_SHIFT (30U) 211 #define HALL_READEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHUPTEN_SHIFT) & HALL_READEN_PHUPTEN_MASK) 212 #define HALL_READEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHUPTEN_MASK) >> HALL_READEN_PHUPTEN_SHIFT) 213 214 /* 215 * PHPREEN (RW) 216 * 217 * 1- load counters to their read registers when phpre flag set 218 */ 219 #define HALL_READEN_PHPREEN_MASK (0x20000000UL) 220 #define HALL_READEN_PHPREEN_SHIFT (29U) 221 #define HALL_READEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHPREEN_SHIFT) & HALL_READEN_PHPREEN_MASK) 222 #define HALL_READEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHPREEN_MASK) >> HALL_READEN_PHPREEN_SHIFT) 223 224 /* 225 * PHDLYEN (RW) 226 * 227 * 1- load counters to their read registers when phdly flag set 228 */ 229 #define HALL_READEN_PHDLYEN_MASK (0x10000000UL) 230 #define HALL_READEN_PHDLYEN_SHIFT (28U) 231 #define HALL_READEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHDLYEN_SHIFT) & HALL_READEN_PHDLYEN_MASK) 232 #define HALL_READEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHDLYEN_MASK) >> HALL_READEN_PHDLYEN_SHIFT) 233 234 /* 235 * UFEN (RW) 236 * 237 * 1- load counters to their read registers when u flag set 238 */ 239 #define HALL_READEN_UFEN_MASK (0x800000UL) 240 #define HALL_READEN_UFEN_SHIFT (23U) 241 #define HALL_READEN_UFEN_SET(x) (((uint32_t)(x) << HALL_READEN_UFEN_SHIFT) & HALL_READEN_UFEN_MASK) 242 #define HALL_READEN_UFEN_GET(x) (((uint32_t)(x) & HALL_READEN_UFEN_MASK) >> HALL_READEN_UFEN_SHIFT) 243 244 /* 245 * VFEN (RW) 246 * 247 * 1- load counters to their read registers when v flag set 248 */ 249 #define HALL_READEN_VFEN_MASK (0x400000UL) 250 #define HALL_READEN_VFEN_SHIFT (22U) 251 #define HALL_READEN_VFEN_SET(x) (((uint32_t)(x) << HALL_READEN_VFEN_SHIFT) & HALL_READEN_VFEN_MASK) 252 #define HALL_READEN_VFEN_GET(x) (((uint32_t)(x) & HALL_READEN_VFEN_MASK) >> HALL_READEN_VFEN_SHIFT) 253 254 /* 255 * WFEN (RW) 256 * 257 * 1- load counters to their read registers when w flag set 258 */ 259 #define HALL_READEN_WFEN_MASK (0x200000UL) 260 #define HALL_READEN_WFEN_SHIFT (21U) 261 #define HALL_READEN_WFEN_SET(x) (((uint32_t)(x) << HALL_READEN_WFEN_SHIFT) & HALL_READEN_WFEN_MASK) 262 #define HALL_READEN_WFEN_GET(x) (((uint32_t)(x) & HALL_READEN_WFEN_MASK) >> HALL_READEN_WFEN_SHIFT) 263 264 /* Bitfield definition for register: DMAEN */ 265 /* 266 * WDGEN (RW) 267 * 268 * 1- generate dma request when wdg flag set 269 */ 270 #define HALL_DMAEN_WDGEN_MASK (0x80000000UL) 271 #define HALL_DMAEN_WDGEN_SHIFT (31U) 272 #define HALL_DMAEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WDGEN_SHIFT) & HALL_DMAEN_WDGEN_MASK) 273 #define HALL_DMAEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WDGEN_MASK) >> HALL_DMAEN_WDGEN_SHIFT) 274 275 /* 276 * PHUPTEN (RW) 277 * 278 * 1- generate dma request when phupt flag set 279 */ 280 #define HALL_DMAEN_PHUPTEN_MASK (0x40000000UL) 281 #define HALL_DMAEN_PHUPTEN_SHIFT (30U) 282 #define HALL_DMAEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHUPTEN_SHIFT) & HALL_DMAEN_PHUPTEN_MASK) 283 #define HALL_DMAEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHUPTEN_MASK) >> HALL_DMAEN_PHUPTEN_SHIFT) 284 285 /* 286 * PHPREEN (RW) 287 * 288 * 1- generate dma request when phpre flag set 289 */ 290 #define HALL_DMAEN_PHPREEN_MASK (0x20000000UL) 291 #define HALL_DMAEN_PHPREEN_SHIFT (29U) 292 #define HALL_DMAEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHPREEN_SHIFT) & HALL_DMAEN_PHPREEN_MASK) 293 #define HALL_DMAEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHPREEN_MASK) >> HALL_DMAEN_PHPREEN_SHIFT) 294 295 /* 296 * PHDLYEN (RW) 297 * 298 * 1- generate dma request when phdly flag set 299 */ 300 #define HALL_DMAEN_PHDLYEN_MASK (0x10000000UL) 301 #define HALL_DMAEN_PHDLYEN_SHIFT (28U) 302 #define HALL_DMAEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHDLYEN_SHIFT) & HALL_DMAEN_PHDLYEN_MASK) 303 #define HALL_DMAEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHDLYEN_MASK) >> HALL_DMAEN_PHDLYEN_SHIFT) 304 305 /* 306 * UFEN (RW) 307 * 308 * 1- generate dma request when u flag set 309 */ 310 #define HALL_DMAEN_UFEN_MASK (0x800000UL) 311 #define HALL_DMAEN_UFEN_SHIFT (23U) 312 #define HALL_DMAEN_UFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_UFEN_SHIFT) & HALL_DMAEN_UFEN_MASK) 313 #define HALL_DMAEN_UFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_UFEN_MASK) >> HALL_DMAEN_UFEN_SHIFT) 314 315 /* 316 * VFEN (RW) 317 * 318 * 1- generate dma request when v flag set 319 */ 320 #define HALL_DMAEN_VFEN_MASK (0x400000UL) 321 #define HALL_DMAEN_VFEN_SHIFT (22U) 322 #define HALL_DMAEN_VFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_VFEN_SHIFT) & HALL_DMAEN_VFEN_MASK) 323 #define HALL_DMAEN_VFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_VFEN_MASK) >> HALL_DMAEN_VFEN_SHIFT) 324 325 /* 326 * WFEN (RW) 327 * 328 * 1- generate dma request when w flag set 329 */ 330 #define HALL_DMAEN_WFEN_MASK (0x200000UL) 331 #define HALL_DMAEN_WFEN_SHIFT (21U) 332 #define HALL_DMAEN_WFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WFEN_SHIFT) & HALL_DMAEN_WFEN_MASK) 333 #define HALL_DMAEN_WFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WFEN_MASK) >> HALL_DMAEN_WFEN_SHIFT) 334 335 /* Bitfield definition for register: SR */ 336 /* 337 * WDGF (RW) 338 * 339 * watchdog count timeout flag 340 */ 341 #define HALL_SR_WDGF_MASK (0x80000000UL) 342 #define HALL_SR_WDGF_SHIFT (31U) 343 #define HALL_SR_WDGF_SET(x) (((uint32_t)(x) << HALL_SR_WDGF_SHIFT) & HALL_SR_WDGF_MASK) 344 #define HALL_SR_WDGF_GET(x) (((uint32_t)(x) & HALL_SR_WDGF_MASK) >> HALL_SR_WDGF_SHIFT) 345 346 /* 347 * PHUPTF (RW) 348 * 349 * phase update flag, will set when any of u, v, w signal toggle 350 */ 351 #define HALL_SR_PHUPTF_MASK (0x40000000UL) 352 #define HALL_SR_PHUPTF_SHIFT (30U) 353 #define HALL_SR_PHUPTF_SET(x) (((uint32_t)(x) << HALL_SR_PHUPTF_SHIFT) & HALL_SR_PHUPTF_MASK) 354 #define HALL_SR_PHUPTF_GET(x) (((uint32_t)(x) & HALL_SR_PHUPTF_MASK) >> HALL_SR_PHUPTF_SHIFT) 355 356 /* 357 * PHPREF (RW) 358 * 359 * phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle 360 */ 361 #define HALL_SR_PHPREF_MASK (0x20000000UL) 362 #define HALL_SR_PHPREF_SHIFT (29U) 363 #define HALL_SR_PHPREF_SET(x) (((uint32_t)(x) << HALL_SR_PHPREF_SHIFT) & HALL_SR_PHPREF_MASK) 364 #define HALL_SR_PHPREF_GET(x) (((uint32_t)(x) & HALL_SR_PHPREF_MASK) >> HALL_SR_PHPREF_SHIFT) 365 366 /* 367 * PHDLYF (RW) 368 * 369 * phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting 370 */ 371 #define HALL_SR_PHDLYF_MASK (0x10000000UL) 372 #define HALL_SR_PHDLYF_SHIFT (28U) 373 #define HALL_SR_PHDLYF_SET(x) (((uint32_t)(x) << HALL_SR_PHDLYF_SHIFT) & HALL_SR_PHDLYF_MASK) 374 #define HALL_SR_PHDLYF_GET(x) (((uint32_t)(x) & HALL_SR_PHDLYF_MASK) >> HALL_SR_PHDLYF_SHIFT) 375 376 /* 377 * UF (RW) 378 * 379 * u flag, will set when u signal toggle 380 */ 381 #define HALL_SR_UF_MASK (0x800000UL) 382 #define HALL_SR_UF_SHIFT (23U) 383 #define HALL_SR_UF_SET(x) (((uint32_t)(x) << HALL_SR_UF_SHIFT) & HALL_SR_UF_MASK) 384 #define HALL_SR_UF_GET(x) (((uint32_t)(x) & HALL_SR_UF_MASK) >> HALL_SR_UF_SHIFT) 385 386 /* 387 * VF (RW) 388 * 389 * v flag, will set when v signal toggle 390 */ 391 #define HALL_SR_VF_MASK (0x400000UL) 392 #define HALL_SR_VF_SHIFT (22U) 393 #define HALL_SR_VF_SET(x) (((uint32_t)(x) << HALL_SR_VF_SHIFT) & HALL_SR_VF_MASK) 394 #define HALL_SR_VF_GET(x) (((uint32_t)(x) & HALL_SR_VF_MASK) >> HALL_SR_VF_SHIFT) 395 396 /* 397 * WF (RW) 398 * 399 * w flag, will set when w signal toggle 400 */ 401 #define HALL_SR_WF_MASK (0x200000UL) 402 #define HALL_SR_WF_SHIFT (21U) 403 #define HALL_SR_WF_SET(x) (((uint32_t)(x) << HALL_SR_WF_SHIFT) & HALL_SR_WF_MASK) 404 #define HALL_SR_WF_GET(x) (((uint32_t)(x) & HALL_SR_WF_MASK) >> HALL_SR_WF_SHIFT) 405 406 /* Bitfield definition for register: IRQEN */ 407 /* 408 * WDGIE (RW) 409 * 410 * 1- generate interrupt request when wdg flag set 411 */ 412 #define HALL_IRQEN_WDGIE_MASK (0x80000000UL) 413 #define HALL_IRQEN_WDGIE_SHIFT (31U) 414 #define HALL_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WDGIE_SHIFT) & HALL_IRQEN_WDGIE_MASK) 415 #define HALL_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WDGIE_MASK) >> HALL_IRQEN_WDGIE_SHIFT) 416 417 /* 418 * PHUPTIE (RW) 419 * 420 * 1- generate interrupt request when phupt flag set 421 */ 422 #define HALL_IRQEN_PHUPTIE_MASK (0x40000000UL) 423 #define HALL_IRQEN_PHUPTIE_SHIFT (30U) 424 #define HALL_IRQEN_PHUPTIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHUPTIE_SHIFT) & HALL_IRQEN_PHUPTIE_MASK) 425 #define HALL_IRQEN_PHUPTIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHUPTIE_MASK) >> HALL_IRQEN_PHUPTIE_SHIFT) 426 427 /* 428 * PHPREIE (RW) 429 * 430 * 1- generate interrupt request when phpre flag set 431 */ 432 #define HALL_IRQEN_PHPREIE_MASK (0x20000000UL) 433 #define HALL_IRQEN_PHPREIE_SHIFT (29U) 434 #define HALL_IRQEN_PHPREIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHPREIE_SHIFT) & HALL_IRQEN_PHPREIE_MASK) 435 #define HALL_IRQEN_PHPREIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHPREIE_MASK) >> HALL_IRQEN_PHPREIE_SHIFT) 436 437 /* 438 * PHDLYIE (RW) 439 * 440 * 1- generate interrupt request when phdly flag set 441 */ 442 #define HALL_IRQEN_PHDLYIE_MASK (0x10000000UL) 443 #define HALL_IRQEN_PHDLYIE_SHIFT (28U) 444 #define HALL_IRQEN_PHDLYIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHDLYIE_SHIFT) & HALL_IRQEN_PHDLYIE_MASK) 445 #define HALL_IRQEN_PHDLYIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHDLYIE_MASK) >> HALL_IRQEN_PHDLYIE_SHIFT) 446 447 /* 448 * UFIE (RW) 449 * 450 * 1- generate interrupt request when u flag set 451 */ 452 #define HALL_IRQEN_UFIE_MASK (0x800000UL) 453 #define HALL_IRQEN_UFIE_SHIFT (23U) 454 #define HALL_IRQEN_UFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_UFIE_SHIFT) & HALL_IRQEN_UFIE_MASK) 455 #define HALL_IRQEN_UFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_UFIE_MASK) >> HALL_IRQEN_UFIE_SHIFT) 456 457 /* 458 * VFIE (RW) 459 * 460 * 1- generate interrupt request when v flag set 461 */ 462 #define HALL_IRQEN_VFIE_MASK (0x400000UL) 463 #define HALL_IRQEN_VFIE_SHIFT (22U) 464 #define HALL_IRQEN_VFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_VFIE_SHIFT) & HALL_IRQEN_VFIE_MASK) 465 #define HALL_IRQEN_VFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_VFIE_MASK) >> HALL_IRQEN_VFIE_SHIFT) 466 467 /* 468 * WFIE (RW) 469 * 470 * 1- generate interrupt request when w flag set 471 */ 472 #define HALL_IRQEN_WFIE_MASK (0x200000UL) 473 #define HALL_IRQEN_WFIE_SHIFT (21U) 474 #define HALL_IRQEN_WFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WFIE_SHIFT) & HALL_IRQEN_WFIE_MASK) 475 #define HALL_IRQEN_WFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WFIE_MASK) >> HALL_IRQEN_WFIE_SHIFT) 476 477 /* Bitfield definition for register of struct array COUNT: W */ 478 /* 479 * WCNT (RO) 480 * 481 * wcnt counter 482 */ 483 #define HALL_COUNT_W_WCNT_MASK (0xFFFFFFFUL) 484 #define HALL_COUNT_W_WCNT_SHIFT (0U) 485 #define HALL_COUNT_W_WCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_W_WCNT_MASK) >> HALL_COUNT_W_WCNT_SHIFT) 486 487 /* Bitfield definition for register of struct array COUNT: V */ 488 /* 489 * VCNT (RO) 490 * 491 * vcnt counter 492 */ 493 #define HALL_COUNT_V_VCNT_MASK (0xFFFFFFFUL) 494 #define HALL_COUNT_V_VCNT_SHIFT (0U) 495 #define HALL_COUNT_V_VCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_V_VCNT_MASK) >> HALL_COUNT_V_VCNT_SHIFT) 496 497 /* Bitfield definition for register of struct array COUNT: U */ 498 /* 499 * DIR (RO) 500 * 501 * 1- reverse rotation 502 * 0- forward rotation 503 */ 504 #define HALL_COUNT_U_DIR_MASK (0x80000000UL) 505 #define HALL_COUNT_U_DIR_SHIFT (31U) 506 #define HALL_COUNT_U_DIR_GET(x) (((uint32_t)(x) & HALL_COUNT_U_DIR_MASK) >> HALL_COUNT_U_DIR_SHIFT) 507 508 /* 509 * USTAT (RO) 510 * 511 * this bit indicate U state 512 */ 513 #define HALL_COUNT_U_USTAT_MASK (0x40000000UL) 514 #define HALL_COUNT_U_USTAT_SHIFT (30U) 515 #define HALL_COUNT_U_USTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_USTAT_MASK) >> HALL_COUNT_U_USTAT_SHIFT) 516 517 /* 518 * VSTAT (RO) 519 * 520 * this bit indicate V state 521 */ 522 #define HALL_COUNT_U_VSTAT_MASK (0x20000000UL) 523 #define HALL_COUNT_U_VSTAT_SHIFT (29U) 524 #define HALL_COUNT_U_VSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_VSTAT_MASK) >> HALL_COUNT_U_VSTAT_SHIFT) 525 526 /* 527 * WSTAT (RO) 528 * 529 * this bit indicate W state 530 */ 531 #define HALL_COUNT_U_WSTAT_MASK (0x10000000UL) 532 #define HALL_COUNT_U_WSTAT_SHIFT (28U) 533 #define HALL_COUNT_U_WSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_WSTAT_MASK) >> HALL_COUNT_U_WSTAT_SHIFT) 534 535 /* 536 * UCNT (RO) 537 * 538 * ucnt counter 539 */ 540 #define HALL_COUNT_U_UCNT_MASK (0xFFFFFFFUL) 541 #define HALL_COUNT_U_UCNT_SHIFT (0U) 542 #define HALL_COUNT_U_UCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_UCNT_MASK) >> HALL_COUNT_U_UCNT_SHIFT) 543 544 /* Bitfield definition for register of struct array COUNT: TMR */ 545 /* 546 * TIMER (RO) 547 * 548 * 32 bit free run timer 549 */ 550 #define HALL_COUNT_TMR_TIMER_MASK (0xFFFFFFFFUL) 551 #define HALL_COUNT_TMR_TIMER_SHIFT (0U) 552 #define HALL_COUNT_TMR_TIMER_GET(x) (((uint32_t)(x) & HALL_COUNT_TMR_TIMER_MASK) >> HALL_COUNT_TMR_TIMER_SHIFT) 553 554 /* Bitfield definition for register of struct array HIS: HIS0 */ 555 /* 556 * UHIS0 (RO) 557 * 558 * copy of ucnt when u signal transition from 0 to 1 559 */ 560 #define HALL_HIS_HIS0_UHIS0_MASK (0xFFFFFFFFUL) 561 #define HALL_HIS_HIS0_UHIS0_SHIFT (0U) 562 #define HALL_HIS_HIS0_UHIS0_GET(x) (((uint32_t)(x) & HALL_HIS_HIS0_UHIS0_MASK) >> HALL_HIS_HIS0_UHIS0_SHIFT) 563 564 /* Bitfield definition for register of struct array HIS: HIS1 */ 565 /* 566 * UHIS1 (RO) 567 * 568 * copy of ucnt when u signal transition from 1 to 0 569 */ 570 #define HALL_HIS_HIS1_UHIS1_MASK (0xFFFFFFFFUL) 571 #define HALL_HIS_HIS1_UHIS1_SHIFT (0U) 572 #define HALL_HIS_HIS1_UHIS1_GET(x) (((uint32_t)(x) & HALL_HIS_HIS1_UHIS1_MASK) >> HALL_HIS_HIS1_UHIS1_SHIFT) 573 574 575 576 /* COUNT register group index macro definition */ 577 #define HALL_COUNT_CURRENT (0UL) 578 #define HALL_COUNT_READ (1UL) 579 #define HALL_COUNT_SNAP0 (2UL) 580 #define HALL_COUNT_SNAP1 (3UL) 581 582 /* HIS register group index macro definition */ 583 #define HALL_HIS_U (0UL) 584 #define HALL_HIS_V (1UL) 585 #define HALL_HIS_W (2UL) 586 587 588 #endif /* HPM_HALL_H */