1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_LCDC_H 10 #define HPM_LCDC_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __RW uint32_t BGND_CL; /* 0x4: Background Color Register */ 15 __RW uint32_t DISP_WN_SIZE; /* 0x8: Display Window Size Register */ 16 __RW uint32_t HSYNC_PARA; /* 0xC: HSYNC Config Register */ 17 __RW uint32_t VSYNC_PARA; /* 0x10: VSYNC Config Register */ 18 __W uint32_t DMA_ST; /* 0x14: DMA Status Register */ 19 __W uint32_t ST; /* 0x18: Status Register */ 20 __RW uint32_t INT_EN; /* 0x1C: Interrupt Enable Register */ 21 __RW uint32_t TXFIFO; /* 0x20: TX FIFO Register */ 22 __R uint8_t RESERVED0[476]; /* 0x24 - 0x1FF: Reserved */ 23 struct { 24 __RW uint32_t LAYCTRL; /* 0x200: Layer Control Register */ 25 __RW uint32_t ALPHAS; /* 0x204: Layer Alpha Register */ 26 __RW uint32_t LAYSIZE; /* 0x208: Layer Size Register */ 27 __RW uint32_t LAYPOS; /* 0x20C: Layer Position Register */ 28 __RW uint32_t START0; /* 0x210: Layer Buffer Pointer Register */ 29 __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ 30 __RW uint32_t LINECFG; /* 0x218: Layer Bus Config Register */ 31 __RW uint32_t BG_CL; /* 0x21C: Layer Background Color Register */ 32 __RW uint32_t CSC_COEF0; /* 0x220: Layer Color Space Conversion Config Register 0 */ 33 __RW uint32_t CSC_COEF1; /* 0x224: Layer Color Space Conversion Config Register 1 */ 34 __RW uint32_t CSC_COEF2; /* 0x228: Layer Color Space Conversion Config Register 2 */ 35 __R uint8_t RESERVED1[20]; /* 0x22C - 0x23F: Reserved */ 36 } LAYER[8]; 37 __RW uint32_t CLUT_LOAD; /* 0x400: Clut Load Control Register */ 38 } LCDC_Type; 39 40 41 /* Bitfield definition for register: CTRL */ 42 /* 43 * SW_RST (RW) 44 * 45 * Software reset, high active. When write 1 ,all internal logical will be reset. 46 * 0b - No action 47 * 1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. 48 */ 49 #define LCDC_CTRL_SW_RST_MASK (0x80000000UL) 50 #define LCDC_CTRL_SW_RST_SHIFT (31U) 51 #define LCDC_CTRL_SW_RST_SET(x) (((uint32_t)(x) << LCDC_CTRL_SW_RST_SHIFT) & LCDC_CTRL_SW_RST_MASK) 52 #define LCDC_CTRL_SW_RST_GET(x) (((uint32_t)(x) & LCDC_CTRL_SW_RST_MASK) >> LCDC_CTRL_SW_RST_SHIFT) 53 54 /* 55 * DISP_ON (RW) 56 * 57 * Display panel On/Off mode. 58 * 0b - Display Off. 59 * 1b - Display On. 60 * Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. 61 * So a good procedure to stop and turn on the display is: 62 * 1) clr VS_BLANK status 63 * 2) assert software reset 64 * 3) de-assert software reset 65 * 4) set display off 66 * 5) check VS_BLANK status until it is asserted, 67 * 6)reset the module, change settings 68 * 7) set display on 69 */ 70 #define LCDC_CTRL_DISP_ON_MASK (0x40000000UL) 71 #define LCDC_CTRL_DISP_ON_SHIFT (30U) 72 #define LCDC_CTRL_DISP_ON_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_ON_SHIFT) & LCDC_CTRL_DISP_ON_MASK) 73 #define LCDC_CTRL_DISP_ON_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_ON_MASK) >> LCDC_CTRL_DISP_ON_SHIFT) 74 75 /* 76 * LINE_PATTERN (RW) 77 * 78 * LCDIF line output order. 79 * 000b - RGB. 80 * 001b - RBG. 81 * 010b - GBR. 82 * 011b - GRB. 83 * 100b - BRG. 84 * 101b - BGR. 85 */ 86 #define LCDC_CTRL_LINE_PATTERN_MASK (0x38000000UL) 87 #define LCDC_CTRL_LINE_PATTERN_SHIFT (27U) 88 #define LCDC_CTRL_LINE_PATTERN_SET(x) (((uint32_t)(x) << LCDC_CTRL_LINE_PATTERN_SHIFT) & LCDC_CTRL_LINE_PATTERN_MASK) 89 #define LCDC_CTRL_LINE_PATTERN_GET(x) (((uint32_t)(x) & LCDC_CTRL_LINE_PATTERN_MASK) >> LCDC_CTRL_LINE_PATTERN_SHIFT) 90 91 /* 92 * DISP_MODE (RW) 93 * 94 * LCDIF operating mode. 95 * 00b - Normal mode. Panel content controlled by layer configuration. 96 * 01b - Test Mode1.(BGND Color Display) 97 * 10b - Test Mode2.(Column Color Bar) 98 * 11b - Test Mode3.(Row Color Bar) 99 */ 100 #define LCDC_CTRL_DISP_MODE_MASK (0x6000000UL) 101 #define LCDC_CTRL_DISP_MODE_SHIFT (25U) 102 #define LCDC_CTRL_DISP_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_MODE_SHIFT) & LCDC_CTRL_DISP_MODE_MASK) 103 #define LCDC_CTRL_DISP_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_MODE_MASK) >> LCDC_CTRL_DISP_MODE_SHIFT) 104 105 /* 106 * BGDCL4CLR (RW) 107 * 108 * background color for clear mode when the alpha channel is 0 109 */ 110 #define LCDC_CTRL_BGDCL4CLR_MASK (0x1000000UL) 111 #define LCDC_CTRL_BGDCL4CLR_SHIFT (24U) 112 #define LCDC_CTRL_BGDCL4CLR_SET(x) (((uint32_t)(x) << LCDC_CTRL_BGDCL4CLR_SHIFT) & LCDC_CTRL_BGDCL4CLR_MASK) 113 #define LCDC_CTRL_BGDCL4CLR_GET(x) (((uint32_t)(x) & LCDC_CTRL_BGDCL4CLR_MASK) >> LCDC_CTRL_BGDCL4CLR_SHIFT) 114 115 /* 116 * ARQOS (RW) 117 * 118 * ARQOS for bus fabric arbitration 119 */ 120 #define LCDC_CTRL_ARQOS_MASK (0xF00000UL) 121 #define LCDC_CTRL_ARQOS_SHIFT (20U) 122 #define LCDC_CTRL_ARQOS_SET(x) (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) 123 #define LCDC_CTRL_ARQOS_GET(x) (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) 124 125 /* 126 * INV_PXDATA (RW) 127 * 128 * Indicates if value at the output (pixel data output) needs to be negated. 129 * 0b - Output is to remain same as the data inside memory 130 * 1b - Output to be negated from the data inside memory 131 */ 132 #define LCDC_CTRL_INV_PXDATA_MASK (0x10U) 133 #define LCDC_CTRL_INV_PXDATA_SHIFT (4U) 134 #define LCDC_CTRL_INV_PXDATA_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXDATA_SHIFT) & LCDC_CTRL_INV_PXDATA_MASK) 135 #define LCDC_CTRL_INV_PXDATA_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXDATA_MASK) >> LCDC_CTRL_INV_PXDATA_SHIFT) 136 137 /* 138 * INV_PXCLK (RW) 139 * 140 * Polarity change of Pixel Clock. 141 * 0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge 142 * 1b - LCDC outputs data on the falling edge, Display samples data on the rising edge 143 */ 144 #define LCDC_CTRL_INV_PXCLK_MASK (0x8U) 145 #define LCDC_CTRL_INV_PXCLK_SHIFT (3U) 146 #define LCDC_CTRL_INV_PXCLK_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXCLK_SHIFT) & LCDC_CTRL_INV_PXCLK_MASK) 147 #define LCDC_CTRL_INV_PXCLK_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXCLK_MASK) >> LCDC_CTRL_INV_PXCLK_SHIFT) 148 149 /* 150 * INV_HREF (RW) 151 * 152 * Polarity of HREF 153 * 0b - HREF signal active HIGH, indicating active pixel data 154 * 1b - HREF signal active LOW 155 */ 156 #define LCDC_CTRL_INV_HREF_MASK (0x4U) 157 #define LCDC_CTRL_INV_HREF_SHIFT (2U) 158 #define LCDC_CTRL_INV_HREF_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HREF_SHIFT) & LCDC_CTRL_INV_HREF_MASK) 159 #define LCDC_CTRL_INV_HREF_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HREF_MASK) >> LCDC_CTRL_INV_HREF_SHIFT) 160 161 /* 162 * INV_VSYNC (RW) 163 * 164 * Polarity of VSYNC 165 * 0b - VSYNC signal active HIGH 166 * 1b - VSYNC signal active LOW 167 */ 168 #define LCDC_CTRL_INV_VSYNC_MASK (0x2U) 169 #define LCDC_CTRL_INV_VSYNC_SHIFT (1U) 170 #define LCDC_CTRL_INV_VSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_VSYNC_SHIFT) & LCDC_CTRL_INV_VSYNC_MASK) 171 #define LCDC_CTRL_INV_VSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_VSYNC_MASK) >> LCDC_CTRL_INV_VSYNC_SHIFT) 172 173 /* 174 * INV_HSYNC (RW) 175 * 176 * Polarity of HSYNC 177 * 0b - HSYNC signal active HIGH 178 * 1b - HSYNC signal active LOW 179 */ 180 #define LCDC_CTRL_INV_HSYNC_MASK (0x1U) 181 #define LCDC_CTRL_INV_HSYNC_SHIFT (0U) 182 #define LCDC_CTRL_INV_HSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HSYNC_SHIFT) & LCDC_CTRL_INV_HSYNC_MASK) 183 #define LCDC_CTRL_INV_HSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HSYNC_MASK) >> LCDC_CTRL_INV_HSYNC_SHIFT) 184 185 /* Bitfield definition for register: BGND_CL */ 186 /* 187 * R (RW) 188 * 189 * Red component of the default color displayed in the sectors where no layer is active. 190 */ 191 #define LCDC_BGND_CL_R_MASK (0xFF0000UL) 192 #define LCDC_BGND_CL_R_SHIFT (16U) 193 #define LCDC_BGND_CL_R_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_R_SHIFT) & LCDC_BGND_CL_R_MASK) 194 #define LCDC_BGND_CL_R_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_R_MASK) >> LCDC_BGND_CL_R_SHIFT) 195 196 /* 197 * G (RW) 198 * 199 * Green component of the default color displayed in the sectors where no layer is active. 200 */ 201 #define LCDC_BGND_CL_G_MASK (0xFF00U) 202 #define LCDC_BGND_CL_G_SHIFT (8U) 203 #define LCDC_BGND_CL_G_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_G_SHIFT) & LCDC_BGND_CL_G_MASK) 204 #define LCDC_BGND_CL_G_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_G_MASK) >> LCDC_BGND_CL_G_SHIFT) 205 206 /* 207 * B (RW) 208 * 209 * Blue component of the default color displayed in the sectors where no layer is active. 210 */ 211 #define LCDC_BGND_CL_B_MASK (0xFFU) 212 #define LCDC_BGND_CL_B_SHIFT (0U) 213 #define LCDC_BGND_CL_B_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_B_SHIFT) & LCDC_BGND_CL_B_MASK) 214 #define LCDC_BGND_CL_B_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_B_MASK) >> LCDC_BGND_CL_B_SHIFT) 215 216 /* Bitfield definition for register: DISP_WN_SIZE */ 217 /* 218 * Y (RW) 219 * 220 * Sets the display size vertical resolution in pixels. 221 */ 222 #define LCDC_DISP_WN_SIZE_Y_MASK (0xFFF0000UL) 223 #define LCDC_DISP_WN_SIZE_Y_SHIFT (16U) 224 #define LCDC_DISP_WN_SIZE_Y_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_Y_SHIFT) & LCDC_DISP_WN_SIZE_Y_MASK) 225 #define LCDC_DISP_WN_SIZE_Y_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_Y_MASK) >> LCDC_DISP_WN_SIZE_Y_SHIFT) 226 227 /* 228 * X (RW) 229 * 230 * Sets the display size horizontal resolution in pixels. 231 */ 232 #define LCDC_DISP_WN_SIZE_X_MASK (0xFFFU) 233 #define LCDC_DISP_WN_SIZE_X_SHIFT (0U) 234 #define LCDC_DISP_WN_SIZE_X_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_X_SHIFT) & LCDC_DISP_WN_SIZE_X_MASK) 235 #define LCDC_DISP_WN_SIZE_X_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_X_MASK) >> LCDC_DISP_WN_SIZE_X_SHIFT) 236 237 /* Bitfield definition for register: HSYNC_PARA */ 238 /* 239 * FP (RW) 240 * 241 * HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC 242 */ 243 #define LCDC_HSYNC_PARA_FP_MASK (0x7FC00000UL) 244 #define LCDC_HSYNC_PARA_FP_SHIFT (22U) 245 #define LCDC_HSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_FP_SHIFT) & LCDC_HSYNC_PARA_FP_MASK) 246 #define LCDC_HSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_FP_MASK) >> LCDC_HSYNC_PARA_FP_SHIFT) 247 248 /* 249 * BP (RW) 250 * 251 * HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC 252 */ 253 #define LCDC_HSYNC_PARA_BP_MASK (0xFF800UL) 254 #define LCDC_HSYNC_PARA_BP_SHIFT (11U) 255 #define LCDC_HSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_BP_SHIFT) & LCDC_HSYNC_PARA_BP_MASK) 256 #define LCDC_HSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_BP_MASK) >> LCDC_HSYNC_PARA_BP_SHIFT) 257 258 /* 259 * PW (RW) 260 * 261 * HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. 262 */ 263 #define LCDC_HSYNC_PARA_PW_MASK (0x1FFU) 264 #define LCDC_HSYNC_PARA_PW_SHIFT (0U) 265 #define LCDC_HSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_PW_SHIFT) & LCDC_HSYNC_PARA_PW_MASK) 266 #define LCDC_HSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_PW_MASK) >> LCDC_HSYNC_PARA_PW_SHIFT) 267 268 /* Bitfield definition for register: VSYNC_PARA */ 269 /* 270 * FP (RW) 271 * 272 * VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC 273 */ 274 #define LCDC_VSYNC_PARA_FP_MASK (0x7FC00000UL) 275 #define LCDC_VSYNC_PARA_FP_SHIFT (22U) 276 #define LCDC_VSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_FP_SHIFT) & LCDC_VSYNC_PARA_FP_MASK) 277 #define LCDC_VSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_FP_MASK) >> LCDC_VSYNC_PARA_FP_SHIFT) 278 279 /* 280 * BP (RW) 281 * 282 * VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC 283 */ 284 #define LCDC_VSYNC_PARA_BP_MASK (0xFF800UL) 285 #define LCDC_VSYNC_PARA_BP_SHIFT (11U) 286 #define LCDC_VSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_BP_SHIFT) & LCDC_VSYNC_PARA_BP_MASK) 287 #define LCDC_VSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_BP_MASK) >> LCDC_VSYNC_PARA_BP_SHIFT) 288 289 /* 290 * PW (RW) 291 * 292 * VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. 293 */ 294 #define LCDC_VSYNC_PARA_PW_MASK (0x1FFU) 295 #define LCDC_VSYNC_PARA_PW_SHIFT (0U) 296 #define LCDC_VSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_PW_SHIFT) & LCDC_VSYNC_PARA_PW_MASK) 297 #define LCDC_VSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_PW_MASK) >> LCDC_VSYNC_PARA_PW_SHIFT) 298 299 /* Bitfield definition for register: DMA_ST */ 300 /* 301 * DMA_ERR (W1C) 302 * 303 * plane n axi error. W1C. 304 */ 305 #define LCDC_DMA_ST_DMA_ERR_MASK (0xFF000000UL) 306 #define LCDC_DMA_ST_DMA_ERR_SHIFT (24U) 307 #define LCDC_DMA_ST_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA_ERR_SHIFT) & LCDC_DMA_ST_DMA_ERR_MASK) 308 #define LCDC_DMA_ST_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA_ERR_MASK) >> LCDC_DMA_ST_DMA_ERR_SHIFT) 309 310 /* 311 * DMA1_DONE (W1C) 312 * 313 * Plane n frame 1 dma done. W1C. 314 */ 315 #define LCDC_DMA_ST_DMA1_DONE_MASK (0xFF0000UL) 316 #define LCDC_DMA_ST_DMA1_DONE_SHIFT (16U) 317 #define LCDC_DMA_ST_DMA1_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA1_DONE_SHIFT) & LCDC_DMA_ST_DMA1_DONE_MASK) 318 #define LCDC_DMA_ST_DMA1_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA1_DONE_MASK) >> LCDC_DMA_ST_DMA1_DONE_SHIFT) 319 320 /* 321 * DMA0_DONE (W1C) 322 * 323 * Plane n frame 0 dma done. W1C. 324 */ 325 #define LCDC_DMA_ST_DMA0_DONE_MASK (0xFF00U) 326 #define LCDC_DMA_ST_DMA0_DONE_SHIFT (8U) 327 #define LCDC_DMA_ST_DMA0_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA0_DONE_SHIFT) & LCDC_DMA_ST_DMA0_DONE_MASK) 328 #define LCDC_DMA_ST_DMA0_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) 329 330 /* Bitfield definition for register: ST */ 331 /* 332 * URGENT_UNDERRUN (W1C) 333 * 334 * Asserted when the output buffer urgent underrun condition encountered 335 */ 336 #define LCDC_ST_URGENT_UNDERRUN_MASK (0x8U) 337 #define LCDC_ST_URGENT_UNDERRUN_SHIFT (3U) 338 #define LCDC_ST_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_URGENT_UNDERRUN_SHIFT) & LCDC_ST_URGENT_UNDERRUN_MASK) 339 #define LCDC_ST_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_URGENT_UNDERRUN_MASK) >> LCDC_ST_URGENT_UNDERRUN_SHIFT) 340 341 /* 342 * VS_BLANK (W1C) 343 * 344 * Asserted when in vertical blanking period. At the start of VSYNC 345 */ 346 #define LCDC_ST_VS_BLANK_MASK (0x4U) 347 #define LCDC_ST_VS_BLANK_SHIFT (2U) 348 #define LCDC_ST_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_ST_VS_BLANK_SHIFT) & LCDC_ST_VS_BLANK_MASK) 349 #define LCDC_ST_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_ST_VS_BLANK_MASK) >> LCDC_ST_VS_BLANK_SHIFT) 350 351 /* 352 * UNDERRUN (W1C) 353 * 354 * Asserted when the output buffer underrun condition encountered 355 */ 356 #define LCDC_ST_UNDERRUN_MASK (0x2U) 357 #define LCDC_ST_UNDERRUN_SHIFT (1U) 358 #define LCDC_ST_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_UNDERRUN_SHIFT) & LCDC_ST_UNDERRUN_MASK) 359 #define LCDC_ST_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_UNDERRUN_MASK) >> LCDC_ST_UNDERRUN_SHIFT) 360 361 /* 362 * VSYNC (W1C) 363 * 364 * Asserted when in vertical blanking period. At the end of VSYNC 365 */ 366 #define LCDC_ST_VSYNC_MASK (0x1U) 367 #define LCDC_ST_VSYNC_SHIFT (0U) 368 #define LCDC_ST_VSYNC_SET(x) (((uint32_t)(x) << LCDC_ST_VSYNC_SHIFT) & LCDC_ST_VSYNC_MASK) 369 #define LCDC_ST_VSYNC_GET(x) (((uint32_t)(x) & LCDC_ST_VSYNC_MASK) >> LCDC_ST_VSYNC_SHIFT) 370 371 /* Bitfield definition for register: INT_EN */ 372 /* 373 * DMA_ERR (RW) 374 * 375 * Interrupt enable for DMA error 376 */ 377 #define LCDC_INT_EN_DMA_ERR_MASK (0xFF000000UL) 378 #define LCDC_INT_EN_DMA_ERR_SHIFT (24U) 379 #define LCDC_INT_EN_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_ERR_SHIFT) & LCDC_INT_EN_DMA_ERR_MASK) 380 #define LCDC_INT_EN_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_ERR_MASK) >> LCDC_INT_EN_DMA_ERR_SHIFT) 381 382 /* 383 * DMA_DONE (RW) 384 * 385 * Interrupt enable for DMA done 386 */ 387 #define LCDC_INT_EN_DMA_DONE_MASK (0xFF0000UL) 388 #define LCDC_INT_EN_DMA_DONE_SHIFT (16U) 389 #define LCDC_INT_EN_DMA_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_DONE_SHIFT) & LCDC_INT_EN_DMA_DONE_MASK) 390 #define LCDC_INT_EN_DMA_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) 391 392 /* 393 * URGENT_UNDERRUN (ROI) 394 * 395 * Asserted when the output buffer urgent underrun condition encountered 396 */ 397 #define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) 398 #define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) 399 #define LCDC_INT_EN_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) 400 401 /* 402 * VS_BLANK (RW) 403 * 404 * Interrupt enable for start of sof 405 */ 406 #define LCDC_INT_EN_VS_BLANK_MASK (0x4U) 407 #define LCDC_INT_EN_VS_BLANK_SHIFT (2U) 408 #define LCDC_INT_EN_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VS_BLANK_SHIFT) & LCDC_INT_EN_VS_BLANK_MASK) 409 #define LCDC_INT_EN_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VS_BLANK_MASK) >> LCDC_INT_EN_VS_BLANK_SHIFT) 410 411 /* 412 * UNDERRUN (RW) 413 * 414 * Interrupt enable for underrun 415 */ 416 #define LCDC_INT_EN_UNDERRUN_MASK (0x2U) 417 #define LCDC_INT_EN_UNDERRUN_SHIFT (1U) 418 #define LCDC_INT_EN_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_UNDERRUN_SHIFT) & LCDC_INT_EN_UNDERRUN_MASK) 419 #define LCDC_INT_EN_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_UNDERRUN_MASK) >> LCDC_INT_EN_UNDERRUN_SHIFT) 420 421 /* 422 * VSYNC (RW) 423 * 424 * Interrupt enable for end of sof 425 */ 426 #define LCDC_INT_EN_VSYNC_MASK (0x1U) 427 #define LCDC_INT_EN_VSYNC_SHIFT (0U) 428 #define LCDC_INT_EN_VSYNC_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VSYNC_SHIFT) & LCDC_INT_EN_VSYNC_MASK) 429 #define LCDC_INT_EN_VSYNC_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VSYNC_MASK) >> LCDC_INT_EN_VSYNC_SHIFT) 430 431 /* Bitfield definition for register: TXFIFO */ 432 /* 433 * THRSH (RW) 434 * 435 * Threshold to start the lcd raster (0--0x7F) 436 */ 437 #define LCDC_TXFIFO_THRSH_MASK (0xFFU) 438 #define LCDC_TXFIFO_THRSH_SHIFT (0U) 439 #define LCDC_TXFIFO_THRSH_SET(x) (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) 440 #define LCDC_TXFIFO_THRSH_GET(x) (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) 441 442 /* Bitfield definition for register of struct array LAYER: LAYCTRL */ 443 /* 444 * PACK_DIR (RW) 445 * 446 * The byte sequence of the 4 bytes in a 32-bit word. 447 * 1: {A0, A1, A2, A3} byte re-ordered. 448 * 0: {A3, A2, A1, A0} the normal case with no byte re-order 449 */ 450 #define LCDC_LAYER_LAYCTRL_PACK_DIR_MASK (0x80000UL) 451 #define LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT (19U) 452 #define LCDC_LAYER_LAYCTRL_PACK_DIR_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) 453 #define LCDC_LAYER_LAYCTRL_PACK_DIR_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) >> LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) 454 455 /* 456 * SHADOW_LOAD_EN (RW) 457 * 458 * Shadow Load Enable 459 * The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. 460 */ 461 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK (0x10000UL) 462 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT (16U) 463 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) 464 #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) >> LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) 465 466 /* 467 * YUV_FORMAT (RW) 468 * 469 * The YUV422 input format selection. 470 * 00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 471 * 01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 472 * 10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 473 * 11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 474 * If not YUV422 mode, 475 * FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) 476 * FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) 477 */ 478 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK (0xC000U) 479 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT (14U) 480 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) 481 #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) >> LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) 482 483 /* 484 * PIXFORMAT (RW) 485 * 486 * Layer encoding format (bit per pixel) 487 * 0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. 488 * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. 489 * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. 490 * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. 491 * 0100b - 16 bpp (RGB565), byte sequence as B,R 492 * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] 493 * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A 494 * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 495 */ 496 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK (0x3C00U) 497 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT (10U) 498 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) 499 #define LCDC_LAYER_LAYCTRL_PIXFORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) >> LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) 500 501 /* 502 * LOCALPHA_OP (RW) 503 * 504 * The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) 505 * 0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream 506 * 1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) 507 * 2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream 508 * Others: Reserved 509 */ 510 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK (0x300U) 511 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT (8U) 512 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) 513 #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) 514 515 /* 516 * INALPHA_OP (RW) 517 * 518 * The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) 519 * 0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline 520 * 1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) 521 * 2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline 522 * Others: Reserved 523 */ 524 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK (0xC0U) 525 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT (6U) 526 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) 527 #define LCDC_LAYER_LAYCTRL_INALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) 528 529 /* 530 * AB_MODE (RW) 531 * 532 * Alpha Blending Mode 533 * 0: SKBlendMode_Clear; 534 * 1: SKBlendMode_Src ; 535 * 2: SKBlendMode_Dst 536 * 3: SKBlendMode_SrcOver 537 * 4: SKBlendMode_DstOver 538 * 5: SKBlendMode_SrcIn 539 * 6: SKBlendMode_DstIn 540 * 7: SKBlendMode_SrcOut 541 * 8: SKBlendMode_DstOut 542 * 9: SKBlendMode_SrcATop 543 * 10: SKBlendMode_DstATop 544 * 11: SKBlendMode_Xor 545 * 12: SKBlendMode_Plus (The conventional blending mode) 546 * 13: SKBlendMode_Modulate 547 * 14: SRC org 548 * 15: DST org 549 * Others: Reserved. 550 */ 551 #define LCDC_LAYER_LAYCTRL_AB_MODE_MASK (0x3CU) 552 #define LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT (2U) 553 #define LCDC_LAYER_LAYCTRL_AB_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) 554 #define LCDC_LAYER_LAYCTRL_AB_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) >> LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) 555 556 /* 557 * EN (RW) 558 * 559 * Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. 560 */ 561 #define LCDC_LAYER_LAYCTRL_EN_MASK (0x1U) 562 #define LCDC_LAYER_LAYCTRL_EN_SHIFT (0U) 563 #define LCDC_LAYER_LAYCTRL_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_EN_SHIFT) & LCDC_LAYER_LAYCTRL_EN_MASK) 564 #define LCDC_LAYER_LAYCTRL_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_EN_MASK) >> LCDC_LAYER_LAYCTRL_EN_SHIFT) 565 566 /* Bitfield definition for register of struct array LAYER: ALPHAS */ 567 /* 568 * LOCD (RW) 569 * 570 * The system alpha value for the data stream of current layer stream (SRC) 571 */ 572 #define LCDC_LAYER_ALPHAS_LOCD_MASK (0xFF00U) 573 #define LCDC_LAYER_ALPHAS_LOCD_SHIFT (8U) 574 #define LCDC_LAYER_ALPHAS_LOCD_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_LOCD_SHIFT) & LCDC_LAYER_ALPHAS_LOCD_MASK) 575 #define LCDC_LAYER_ALPHAS_LOCD_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_LOCD_MASK) >> LCDC_LAYER_ALPHAS_LOCD_SHIFT) 576 577 /* 578 * IND (RW) 579 * 580 * The system alpha value for the input stream from previous stage (DST) 581 */ 582 #define LCDC_LAYER_ALPHAS_IND_MASK (0xFFU) 583 #define LCDC_LAYER_ALPHAS_IND_SHIFT (0U) 584 #define LCDC_LAYER_ALPHAS_IND_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_IND_SHIFT) & LCDC_LAYER_ALPHAS_IND_MASK) 585 #define LCDC_LAYER_ALPHAS_IND_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_IND_MASK) >> LCDC_LAYER_ALPHAS_IND_SHIFT) 586 587 /* Bitfield definition for register of struct array LAYER: LAYSIZE */ 588 /* 589 * HEIGHT (RW) 590 * 591 * Height of the layer in pixels 592 */ 593 #define LCDC_LAYER_LAYSIZE_HEIGHT_MASK (0xFFF0000UL) 594 #define LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT (16U) 595 #define LCDC_LAYER_LAYSIZE_HEIGHT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) 596 #define LCDC_LAYER_LAYSIZE_HEIGHT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) >> LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) 597 598 /* 599 * WIDTH (RW) 600 * 601 * Width of the layer in pixels (Note: not actual width-1) 602 * The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. 603 */ 604 #define LCDC_LAYER_LAYSIZE_WIDTH_MASK (0xFFFU) 605 #define LCDC_LAYER_LAYSIZE_WIDTH_SHIFT (0U) 606 #define LCDC_LAYER_LAYSIZE_WIDTH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) 607 #define LCDC_LAYER_LAYSIZE_WIDTH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) 608 609 /* Bitfield definition for register of struct array LAYER: LAYPOS */ 610 /* 611 * Y (RW) 612 * 613 * The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. 614 */ 615 #define LCDC_LAYER_LAYPOS_Y_MASK (0xFFFF0000UL) 616 #define LCDC_LAYER_LAYPOS_Y_SHIFT (16U) 617 #define LCDC_LAYER_LAYPOS_Y_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_Y_SHIFT) & LCDC_LAYER_LAYPOS_Y_MASK) 618 #define LCDC_LAYER_LAYPOS_Y_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_Y_MASK) >> LCDC_LAYER_LAYPOS_Y_SHIFT) 619 620 /* 621 * X (RW) 622 * 623 * The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. 624 */ 625 #define LCDC_LAYER_LAYPOS_X_MASK (0xFFFFU) 626 #define LCDC_LAYER_LAYPOS_X_SHIFT (0U) 627 #define LCDC_LAYER_LAYPOS_X_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_X_SHIFT) & LCDC_LAYER_LAYPOS_X_MASK) 628 #define LCDC_LAYER_LAYPOS_X_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_X_MASK) >> LCDC_LAYER_LAYPOS_X_SHIFT) 629 630 /* Bitfield definition for register of struct array LAYER: START0 */ 631 /* 632 * ADDR0 (RW) 633 * 634 * Input buffer Start address 0 635 */ 636 #define LCDC_LAYER_START0_ADDR0_MASK (0xFFFFFFFFUL) 637 #define LCDC_LAYER_START0_ADDR0_SHIFT (0U) 638 #define LCDC_LAYER_START0_ADDR0_SET(x) (((uint32_t)(x) << LCDC_LAYER_START0_ADDR0_SHIFT) & LCDC_LAYER_START0_ADDR0_MASK) 639 #define LCDC_LAYER_START0_ADDR0_GET(x) (((uint32_t)(x) & LCDC_LAYER_START0_ADDR0_MASK) >> LCDC_LAYER_START0_ADDR0_SHIFT) 640 641 /* Bitfield definition for register of struct array LAYER: LINECFG */ 642 /* 643 * MPT_SIZE (RW) 644 * 645 * Maximal Per Transfer Data Size: 646 * 0: 64 bytes 647 * 1: 128 bytes 648 * 2: 256 bytes 649 * 3: 512 bytes 650 * 4: 1024 bytes 651 */ 652 #define LCDC_LAYER_LINECFG_MPT_SIZE_MASK (0xE0000000UL) 653 #define LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT (29U) 654 #define LCDC_LAYER_LINECFG_MPT_SIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) 655 #define LCDC_LAYER_LINECFG_MPT_SIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) >> LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) 656 657 /* 658 * MAX_OT (RW) 659 * 660 * the number of outstanding axi read transactions. 661 * If zero, it means max 8. 662 */ 663 #define LCDC_LAYER_LINECFG_MAX_OT_MASK (0xE00000UL) 664 #define LCDC_LAYER_LINECFG_MAX_OT_SHIFT (21U) 665 #define LCDC_LAYER_LINECFG_MAX_OT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MAX_OT_SHIFT) & LCDC_LAYER_LINECFG_MAX_OT_MASK) 666 #define LCDC_LAYER_LINECFG_MAX_OT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MAX_OT_MASK) >> LCDC_LAYER_LINECFG_MAX_OT_SHIFT) 667 668 /* 669 * PITCH (RW) 670 * 671 * Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry. 672 */ 673 #define LCDC_LAYER_LINECFG_PITCH_MASK (0xFFFFU) 674 #define LCDC_LAYER_LINECFG_PITCH_SHIFT (0U) 675 #define LCDC_LAYER_LINECFG_PITCH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_PITCH_SHIFT) & LCDC_LAYER_LINECFG_PITCH_MASK) 676 #define LCDC_LAYER_LINECFG_PITCH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_PITCH_MASK) >> LCDC_LAYER_LINECFG_PITCH_SHIFT) 677 678 /* Bitfield definition for register of struct array LAYER: BG_CL */ 679 /* 680 * ARGB (RW) 681 * 682 * ARGB8888. It is only useful in the last active stage in the pipeline. 683 */ 684 #define LCDC_LAYER_BG_CL_ARGB_MASK (0xFFFFFFFFUL) 685 #define LCDC_LAYER_BG_CL_ARGB_SHIFT (0U) 686 #define LCDC_LAYER_BG_CL_ARGB_SET(x) (((uint32_t)(x) << LCDC_LAYER_BG_CL_ARGB_SHIFT) & LCDC_LAYER_BG_CL_ARGB_MASK) 687 #define LCDC_LAYER_BG_CL_ARGB_GET(x) (((uint32_t)(x) & LCDC_LAYER_BG_CL_ARGB_MASK) >> LCDC_LAYER_BG_CL_ARGB_SHIFT) 688 689 /* Bitfield definition for register of struct array LAYER: CSC_COEF0 */ 690 /* 691 * YCBCR_MODE (RW) 692 * 693 * This bit changes the behavior when performing U/V converting. 694 * 0b - Converting YUV to RGB data 695 * 1b - Converting YCbCr to RGB data 696 */ 697 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) 698 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT (31U) 699 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) 700 #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) >> LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) 701 702 /* 703 * ENABLE (RW) 704 * 705 * Enable the CSC unit in the LCDC plane data path. 706 * 0b - The CSC is bypassed and the input pixels are RGB data already 707 * 1b - The CSC is enabled and the pixels will be converted to RGB data 708 * This bit will be shadowed. 709 */ 710 #define LCDC_LAYER_CSC_COEF0_ENABLE_MASK (0x40000000UL) 711 #define LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT (30U) 712 #define LCDC_LAYER_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) 713 #define LCDC_LAYER_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) >> LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) 714 715 /* 716 * C0 (RW) 717 * 718 * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) 719 */ 720 #define LCDC_LAYER_CSC_COEF0_C0_MASK (0x1FFC0000UL) 721 #define LCDC_LAYER_CSC_COEF0_C0_SHIFT (18U) 722 #define LCDC_LAYER_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_C0_SHIFT) & LCDC_LAYER_CSC_COEF0_C0_MASK) 723 #define LCDC_LAYER_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_C0_MASK) >> LCDC_LAYER_CSC_COEF0_C0_SHIFT) 724 725 /* 726 * UV_OFFSET (RW) 727 * 728 * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. 729 * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). 730 */ 731 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) 732 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT (9U) 733 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) 734 #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) 735 736 /* 737 * Y_OFFSET (RW) 738 * 739 * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is 740 * typically -16 (0x1F0). 741 */ 742 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) 743 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT (0U) 744 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) 745 #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) 746 747 /* Bitfield definition for register of struct array LAYER: CSC_COEF1 */ 748 /* 749 * C1 (RW) 750 * 751 * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). 752 */ 753 #define LCDC_LAYER_CSC_COEF1_C1_MASK (0x7FF0000UL) 754 #define LCDC_LAYER_CSC_COEF1_C1_SHIFT (16U) 755 #define LCDC_LAYER_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C1_SHIFT) & LCDC_LAYER_CSC_COEF1_C1_MASK) 756 #define LCDC_LAYER_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C1_MASK) >> LCDC_LAYER_CSC_COEF1_C1_SHIFT) 757 758 /* 759 * C4 (RW) 760 * 761 * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). 762 */ 763 #define LCDC_LAYER_CSC_COEF1_C4_MASK (0x7FFU) 764 #define LCDC_LAYER_CSC_COEF1_C4_SHIFT (0U) 765 #define LCDC_LAYER_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C4_SHIFT) & LCDC_LAYER_CSC_COEF1_C4_MASK) 766 #define LCDC_LAYER_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C4_MASK) >> LCDC_LAYER_CSC_COEF1_C4_SHIFT) 767 768 /* Bitfield definition for register of struct array LAYER: CSC_COEF2 */ 769 /* 770 * C2 (RW) 771 * 772 * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). 773 */ 774 #define LCDC_LAYER_CSC_COEF2_C2_MASK (0x7FF0000UL) 775 #define LCDC_LAYER_CSC_COEF2_C2_SHIFT (16U) 776 #define LCDC_LAYER_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C2_SHIFT) & LCDC_LAYER_CSC_COEF2_C2_MASK) 777 #define LCDC_LAYER_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C2_MASK) >> LCDC_LAYER_CSC_COEF2_C2_SHIFT) 778 779 /* 780 * C3 (RW) 781 * 782 * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). 783 */ 784 #define LCDC_LAYER_CSC_COEF2_C3_MASK (0x7FFU) 785 #define LCDC_LAYER_CSC_COEF2_C3_SHIFT (0U) 786 #define LCDC_LAYER_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C3_SHIFT) & LCDC_LAYER_CSC_COEF2_C3_MASK) 787 #define LCDC_LAYER_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) 788 789 /* Bitfield definition for register: CLUT_LOAD */ 790 /* 791 * SEL_NUM (RW) 792 * 793 * Selected CLUT Number 794 * The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. 795 * . 3'h0 - PLANE 0 796 * . 3'h1 - PLANE 1 797 * . ------ 798 * . 3'h7 - PLANE 7 799 * CLUT 8 can be modified via APB even when display is on. 800 * Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. 801 */ 802 #define LCDC_CLUT_LOAD_SEL_NUM_MASK (0x70U) 803 #define LCDC_CLUT_LOAD_SEL_NUM_SHIFT (4U) 804 #define LCDC_CLUT_LOAD_SEL_NUM_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_SEL_NUM_SHIFT) & LCDC_CLUT_LOAD_SEL_NUM_MASK) 805 #define LCDC_CLUT_LOAD_SEL_NUM_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_SEL_NUM_MASK) >> LCDC_CLUT_LOAD_SEL_NUM_SHIFT) 806 807 /* 808 * UPDATE_EN (RW) 809 * 810 * CLUT Update Enable 811 * The bit is written to 1 when software want to update the Color Look Up Tables during display. 812 * If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. 813 * If set to 0, software can update CLUT8 directly according to the CLUT memory map. 814 * Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. 815 */ 816 #define LCDC_CLUT_LOAD_UPDATE_EN_MASK (0x1U) 817 #define LCDC_CLUT_LOAD_UPDATE_EN_SHIFT (0U) 818 #define LCDC_CLUT_LOAD_UPDATE_EN_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) 819 #define LCDC_CLUT_LOAD_UPDATE_EN_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) >> LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) 820 821 822 823 /* LAYER register group index macro definition */ 824 #define LCDC_LAYER_0 (0UL) 825 #define LCDC_LAYER_1 (1UL) 826 #define LCDC_LAYER_2 (2UL) 827 #define LCDC_LAYER_3 (3UL) 828 #define LCDC_LAYER_4 (4UL) 829 #define LCDC_LAYER_5 (5UL) 830 #define LCDC_LAYER_6 (6UL) 831 #define LCDC_LAYER_7 (7UL) 832 833 834 #endif /* HPM_LCDC_H */