1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_PMON_H 10 #define HPM_PMON_H 11 12 typedef struct { 13 struct { 14 __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ 15 __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ 16 } MONITOR[4]; 17 __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ 18 __RW uint32_t IRQ_FLAG; /* 0x40: */ 19 __RW uint32_t IRQ_ENABLE; /* 0x44: */ 20 } PMON_Type; 21 22 23 /* Bitfield definition for register of struct array MONITOR: CONTROL */ 24 /* 25 * ACTIVE (RW) 26 * 27 * select glitch works in active mode or passve mode. 28 * 0: passive mode, depends on power glitch destory DFF value 29 * 1: active mode, check glitch by DFF chain 30 */ 31 #define PMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) 32 #define PMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) 33 #define PMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ACTIVE_SHIFT) & PMON_MONITOR_CONTROL_ACTIVE_MASK) 34 #define PMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ACTIVE_MASK) >> PMON_MONITOR_CONTROL_ACTIVE_SHIFT) 35 36 /* 37 * ENABLE (RW) 38 * 39 * enable glitch detector 40 * 0: detector disabled 41 * 1: detector enabled 42 */ 43 #define PMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) 44 #define PMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) 45 #define PMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ENABLE_SHIFT) & PMON_MONITOR_CONTROL_ENABLE_MASK) 46 #define PMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ENABLE_MASK) >> PMON_MONITOR_CONTROL_ENABLE_SHIFT) 47 48 /* Bitfield definition for register of struct array MONITOR: STATUS */ 49 /* 50 * FLAG (RW) 51 * 52 * flag for glitch detected, write 1 to clear this flag 53 * 0: glitch not detected 54 * 1: glitch detected 55 */ 56 #define PMON_MONITOR_STATUS_FLAG_MASK (0x1U) 57 #define PMON_MONITOR_STATUS_FLAG_SHIFT (0U) 58 #define PMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << PMON_MONITOR_STATUS_FLAG_SHIFT) & PMON_MONITOR_STATUS_FLAG_MASK) 59 #define PMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & PMON_MONITOR_STATUS_FLAG_MASK) >> PMON_MONITOR_STATUS_FLAG_SHIFT) 60 61 /* Bitfield definition for register: IRQ_FLAG */ 62 /* 63 * FLAG (RW) 64 * 65 * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag 66 * 0: no monitor interrupt 67 * 1: monitor interrupt happened 68 */ 69 #define PMON_IRQ_FLAG_FLAG_MASK (0xFU) 70 #define PMON_IRQ_FLAG_FLAG_SHIFT (0U) 71 #define PMON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << PMON_IRQ_FLAG_FLAG_SHIFT) & PMON_IRQ_FLAG_FLAG_MASK) 72 #define PMON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & PMON_IRQ_FLAG_FLAG_MASK) >> PMON_IRQ_FLAG_FLAG_SHIFT) 73 74 /* Bitfield definition for register: IRQ_ENABLE */ 75 /* 76 * ENABLE (RW) 77 * 78 * interrupt enable, each bit represents for one monitor 79 * 0: monitor interrupt disabled 80 * 1: monitor interrupt enabled 81 */ 82 #define PMON_IRQ_ENABLE_ENABLE_MASK (0xFU) 83 #define PMON_IRQ_ENABLE_ENABLE_SHIFT (0U) 84 #define PMON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PMON_IRQ_ENABLE_ENABLE_SHIFT) & PMON_IRQ_ENABLE_ENABLE_MASK) 85 #define PMON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PMON_IRQ_ENABLE_ENABLE_MASK) >> PMON_IRQ_ENABLE_ENABLE_SHIFT) 86 87 88 89 /* MONITOR register group index macro definition */ 90 #define PMON_MONITOR_GLITCH0 (0UL) 91 #define PMON_MONITOR_GLITCH1 (1UL) 92 #define PMON_MONITOR_CLOCK0 (2UL) 93 #define PMON_MONITOR_CLOCK1 (3UL) 94 95 96 #endif /* HPM_PMON_H */