1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_UART_H 10 #define HPM_UART_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ 14 __RW uint32_t CFG; /* 0x10: Configuration Register */ 15 __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ 16 __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ 17 union { 18 __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ 19 __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ 20 __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ 21 }; 22 union { 23 __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ 24 __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ 25 }; 26 union { 27 __R uint32_t IIR; /* 0x28: Interrupt Identification Register */ 28 __W uint32_t FCR; /* 0x28: FIFO Control Register */ 29 }; 30 __RW uint32_t LCR; /* 0x2C: Line Control Register */ 31 __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ 32 __R uint32_t LSR; /* 0x34: Line Status Register */ 33 __R uint32_t MSR; /* 0x38: Modem Status Register */ 34 } UART_Type; 35 36 37 /* Bitfield definition for register: CFG */ 38 /* 39 * FIFOSIZE (RO) 40 * 41 * The depth of RXFIFO and TXFIFO 42 * 0: 16-byte FIFO 43 * 1: 32-byte FIFO 44 * 2: 64-byte FIFO 45 * 3: 128-byte FIFO 46 */ 47 #define UART_CFG_FIFOSIZE_MASK (0x3U) 48 #define UART_CFG_FIFOSIZE_SHIFT (0U) 49 #define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) 50 51 /* Bitfield definition for register: OSCR */ 52 /* 53 * OSC (RW) 54 * 55 * Over-sample control 56 * The value must be an even number; any odd value 57 * writes to this field will be converted to an even value. 58 * OSC=0: The over-sample ratio is 32 59 * OSC<=8: The over-sample ratio is 8 60 * 8 < OSC< 32: The over sample ratio is OSC 61 */ 62 #define UART_OSCR_OSC_MASK (0x1FU) 63 #define UART_OSCR_OSC_SHIFT (0U) 64 #define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) 65 #define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) 66 67 /* Bitfield definition for register: RBR */ 68 /* 69 * RBR (RO) 70 * 71 * Receive data read port 72 */ 73 #define UART_RBR_RBR_MASK (0xFFU) 74 #define UART_RBR_RBR_SHIFT (0U) 75 #define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) 76 77 /* Bitfield definition for register: THR */ 78 /* 79 * THR (WO) 80 * 81 * Transmit data write port 82 */ 83 #define UART_THR_THR_MASK (0xFFU) 84 #define UART_THR_THR_SHIFT (0U) 85 #define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) 86 #define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) 87 88 /* Bitfield definition for register: DLL */ 89 /* 90 * DLL (RW) 91 * 92 * Least significant byte of the Divisor Latch 93 */ 94 #define UART_DLL_DLL_MASK (0xFFU) 95 #define UART_DLL_DLL_SHIFT (0U) 96 #define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) 97 #define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) 98 99 /* Bitfield definition for register: IER */ 100 /* 101 * EMSI (RW) 102 * 103 * Enable modem status interrupt 104 * The interrupt asserts when the status of one of the 105 * following occurs: 106 * The status of modem_rin, modem_dcdn, 107 * modem_dsrn or modem_ctsn (If the auto-cts mode is 108 * disabled) has been changed. 109 * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), 110 * modem_ctsn would be used to control the transmitter. 111 */ 112 #define UART_IER_EMSI_MASK (0x8U) 113 #define UART_IER_EMSI_SHIFT (3U) 114 #define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) 115 #define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) 116 117 /* 118 * ELSI (RW) 119 * 120 * Enable receiver line status interrupt 121 */ 122 #define UART_IER_ELSI_MASK (0x4U) 123 #define UART_IER_ELSI_SHIFT (2U) 124 #define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) 125 #define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) 126 127 /* 128 * ETHEI (RW) 129 * 130 * Enable transmitter holding register interrupt 131 */ 132 #define UART_IER_ETHEI_MASK (0x2U) 133 #define UART_IER_ETHEI_SHIFT (1U) 134 #define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) 135 #define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) 136 137 /* 138 * ERBI (RW) 139 * 140 * Enable received data available interrupt and the 141 * character timeout interrupt 142 * 0: Disable 143 * 1: Enable 144 */ 145 #define UART_IER_ERBI_MASK (0x1U) 146 #define UART_IER_ERBI_SHIFT (0U) 147 #define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) 148 #define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) 149 150 /* Bitfield definition for register: DLM */ 151 /* 152 * DLM (RW) 153 * 154 * Most significant byte of the Divisor Latch 155 */ 156 #define UART_DLM_DLM_MASK (0xFFU) 157 #define UART_DLM_DLM_SHIFT (0U) 158 #define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) 159 #define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) 160 161 /* Bitfield definition for register: IIR */ 162 /* 163 * FIFOED (RO) 164 * 165 * FIFOs enabled 166 * These two bits are 1 when bit 0 of the FIFO Control 167 * Register (FIFOE) is set to 1. 168 */ 169 #define UART_IIR_FIFOED_MASK (0xC0U) 170 #define UART_IIR_FIFOED_SHIFT (6U) 171 #define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) 172 173 /* 174 * INTRID (RO) 175 * 176 * Interrupt ID 177 */ 178 #define UART_IIR_INTRID_MASK (0xFU) 179 #define UART_IIR_INTRID_SHIFT (0U) 180 #define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) 181 182 /* Bitfield definition for register: FCR */ 183 /* 184 * RFIFOT (WO) 185 * 186 * Receiver FIFO trigger level 187 */ 188 #define UART_FCR_RFIFOT_MASK (0xC0U) 189 #define UART_FCR_RFIFOT_SHIFT (6U) 190 #define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) 191 #define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) 192 193 /* 194 * TFIFOT (WO) 195 * 196 * Transmitter FIFO trigger level 197 */ 198 #define UART_FCR_TFIFOT_MASK (0x30U) 199 #define UART_FCR_TFIFOT_SHIFT (4U) 200 #define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) 201 #define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) 202 203 /* 204 * DMAE (WO) 205 * 206 * DMA enable 207 * 0: Disable 208 * 1: Enable 209 */ 210 #define UART_FCR_DMAE_MASK (0x8U) 211 #define UART_FCR_DMAE_SHIFT (3U) 212 #define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) 213 #define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) 214 215 /* 216 * TFIFORST (WO) 217 * 218 * Transmitter FIFO reset 219 * Write 1 to clear all bytes in the TXFIFO and resets its 220 * counter. The Transmitter Shift Register is not cleared. 221 * This bit will automatically be cleared. 222 */ 223 #define UART_FCR_TFIFORST_MASK (0x4U) 224 #define UART_FCR_TFIFORST_SHIFT (2U) 225 #define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) 226 #define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) 227 228 /* 229 * RFIFORST (WO) 230 * 231 * Receiver FIFO reset 232 * Write 1 to clear all bytes in the RXFIFO and resets its 233 * counter. The Receiver Shift Register is not cleared. 234 * This bit will automatically be cleared. 235 */ 236 #define UART_FCR_RFIFORST_MASK (0x2U) 237 #define UART_FCR_RFIFORST_SHIFT (1U) 238 #define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) 239 #define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) 240 241 /* 242 * FIFOE (WO) 243 * 244 * FIFO enable 245 * Write 1 to enable both the transmitter and receiver 246 * FIFOs. 247 * The FIFOs are reset when the value of this bit toggles. 248 */ 249 #define UART_FCR_FIFOE_MASK (0x1U) 250 #define UART_FCR_FIFOE_SHIFT (0U) 251 #define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) 252 #define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) 253 254 /* Bitfield definition for register: LCR */ 255 /* 256 * DLAB (RW) 257 * 258 * Divisor latch access bit 259 */ 260 #define UART_LCR_DLAB_MASK (0x80U) 261 #define UART_LCR_DLAB_SHIFT (7U) 262 #define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) 263 #define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) 264 265 /* 266 * BC (RW) 267 * 268 * Break control 269 */ 270 #define UART_LCR_BC_MASK (0x40U) 271 #define UART_LCR_BC_SHIFT (6U) 272 #define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) 273 #define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) 274 275 /* 276 * SPS (RW) 277 * 278 * Stick parity 279 * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). 280 * 0: Disable the sticky bit parity. 281 */ 282 #define UART_LCR_SPS_MASK (0x20U) 283 #define UART_LCR_SPS_SHIFT (5U) 284 #define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) 285 #define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) 286 287 /* 288 * EPS (RW) 289 * 290 * Even parity select 291 * 1: Even parity (an even number of logic-1 is in the data 292 * and parity bits) 293 * 0: Old parity. 294 */ 295 #define UART_LCR_EPS_MASK (0x10U) 296 #define UART_LCR_EPS_SHIFT (4U) 297 #define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) 298 #define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) 299 300 /* 301 * PEN (RW) 302 * 303 * Parity enable 304 * When this bit is set, a parity bit is generated in 305 * transmitted data before the first STOP bit and the parity 306 * bit would be checked for the received data. 307 */ 308 #define UART_LCR_PEN_MASK (0x8U) 309 #define UART_LCR_PEN_SHIFT (3U) 310 #define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) 311 #define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) 312 313 /* 314 * STB (RW) 315 * 316 * Number of STOP bits 317 * 0: 1 bits 318 * 1: The number of STOP bit is based on the WLS setting 319 * When WLS = 0, STOP bit is 1.5 bits 320 * When WLS = 1, 2, 3, STOP bit is 2 bits 321 */ 322 #define UART_LCR_STB_MASK (0x4U) 323 #define UART_LCR_STB_SHIFT (2U) 324 #define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) 325 #define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) 326 327 /* 328 * WLS (RW) 329 * 330 * Word length setting 331 * 0: 5 bits 332 * 1: 6 bits 333 * 2: 7 bits 334 * 3: 8 bits 335 */ 336 #define UART_LCR_WLS_MASK (0x3U) 337 #define UART_LCR_WLS_SHIFT (0U) 338 #define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) 339 #define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) 340 341 /* Bitfield definition for register: MCR */ 342 /* 343 * AFE (RW) 344 * 345 * Auto flow control enable 346 * 0: Disable 347 * 1: The auto-CTS and auto-RTS setting is based on the 348 * RTS bit setting: 349 * When RTS = 0, auto-CTS only 350 * When RTS = 1, auto-CTS and auto-RTS 351 */ 352 #define UART_MCR_AFE_MASK (0x20U) 353 #define UART_MCR_AFE_SHIFT (5U) 354 #define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) 355 #define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) 356 357 /* 358 * LOOP (RW) 359 * 360 * Enable loopback mode 361 * 0: Disable 362 * 1: Enable 363 */ 364 #define UART_MCR_LOOP_MASK (0x10U) 365 #define UART_MCR_LOOP_SHIFT (4U) 366 #define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) 367 #define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) 368 369 /* 370 * RTS (RW) 371 * 372 * Request to send 373 * This bit controls the modem_rtsn output. 374 * 0: The modem_rtsn output signal will be driven HIGH 375 * 1: The modem_rtsn output signal will be driven LOW 376 */ 377 #define UART_MCR_RTS_MASK (0x2U) 378 #define UART_MCR_RTS_SHIFT (1U) 379 #define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) 380 #define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) 381 382 /* Bitfield definition for register: LSR */ 383 /* 384 * ERRF (RO) 385 * 386 * Error in RXFIFO 387 * In the FIFO mode, this bit is set when there is at least 388 * one parity error, framing error, or line break 389 * associated with data in the RXFIFO. It is cleared when 390 * this register is read and there is no more error for the 391 * rest of data in the RXFIFO. 392 */ 393 #define UART_LSR_ERRF_MASK (0x80U) 394 #define UART_LSR_ERRF_SHIFT (7U) 395 #define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) 396 397 /* 398 * TEMT (RO) 399 * 400 * Transmitter empty 401 * This bit is 1 when the THR (TXFIFO in the FIFO 402 * mode) and the Transmitter Shift Register (TSR) are 403 * both empty. Otherwise, it is zero. 404 */ 405 #define UART_LSR_TEMT_MASK (0x40U) 406 #define UART_LSR_TEMT_SHIFT (6U) 407 #define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) 408 409 /* 410 * THRE (RO) 411 * 412 * Transmitter Holding Register empty 413 * This bit is 1 when the THR (TXFIFO in the FIFO 414 * mode) is empty. Otherwise, it is zero. 415 * If the THRE interrupt is enabled, an interrupt is 416 * triggered when THRE becomes 1. 417 */ 418 #define UART_LSR_THRE_MASK (0x20U) 419 #define UART_LSR_THRE_SHIFT (5U) 420 #define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) 421 422 /* 423 * LBREAK (RO) 424 * 425 * Line break 426 * This bit is set when the uart_sin input signal was held 427 * LOWfor longer than the time for a full-word 428 * transmission. A full-word transmission is the 429 * transmission of the START, data, parity, and STOP 430 * bits. It is cleared when this register is read. 431 * In the FIFO mode, this bit indicates the line break for 432 * the received data at the top of the RXFIFO. 433 */ 434 #define UART_LSR_LBREAK_MASK (0x10U) 435 #define UART_LSR_LBREAK_SHIFT (4U) 436 #define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) 437 438 /* 439 * FE (RO) 440 * 441 * Framing error 442 * This bit is set when the received STOP bit is not 443 * HIGH. It is cleared when this register is read. 444 * In the FIFO mode, this bit indicates the framing error 445 * for the received data at the top of the RXFIFO. 446 */ 447 #define UART_LSR_FE_MASK (0x8U) 448 #define UART_LSR_FE_SHIFT (3U) 449 #define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) 450 451 /* 452 * PE (RO) 453 * 454 * Parity error 455 * This bit is set when the received parity does not match 456 * with the parity selected in the LCR[5:4]. It is cleared 457 * when this register is read. 458 * In the FIFO mode, this bit indicates the parity error 459 * for the received data at the top of the RXFIFO. 460 */ 461 #define UART_LSR_PE_MASK (0x4U) 462 #define UART_LSR_PE_SHIFT (2U) 463 #define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) 464 465 /* 466 * OE (RO) 467 * 468 * Overrun error 469 * This bit indicates that data in the Receiver Buffer 470 * Register (RBR) is overrun. 471 */ 472 #define UART_LSR_OE_MASK (0x2U) 473 #define UART_LSR_OE_SHIFT (1U) 474 #define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) 475 476 /* 477 * DR (RO) 478 * 479 * Data ready. 480 * This bit is set when there are incoming received data 481 * in the Receiver Buffer Register (RBR). It is cleared 482 * when all of the received data are read. 483 */ 484 #define UART_LSR_DR_MASK (0x1U) 485 #define UART_LSR_DR_SHIFT (0U) 486 #define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) 487 488 /* Bitfield definition for register: MSR */ 489 /* 490 * CTS (RO) 491 * 492 * Clear to send 493 * 0: The modem_ctsn input signal is HIGH. 494 * 1: The modem_ctsn input signal is LOW. 495 */ 496 #define UART_MSR_CTS_MASK (0x10U) 497 #define UART_MSR_CTS_SHIFT (4U) 498 #define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) 499 500 /* 501 * DCTS (RC) 502 * 503 * Delta clear to send 504 * This bit is set when the state of the modem_ctsn input 505 * signal has been changed since the last time this 506 * register is read. 507 */ 508 #define UART_MSR_DCTS_MASK (0x1U) 509 #define UART_MSR_DCTS_SHIFT (0U) 510 #define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) 511 512 513 514 515 #endif /* HPM_UART_H */