1 2 /* 3 * isp520_reg_cfg.h 4 * 5 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 6 * 7 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #ifndef __ISP520__REG__CFG__H 21 #define __ISP520__REG__CFG__H 22 23 #define ISP_ADDR_BIT_R_SHIFT 2 24 25 #define ISP_LOAD_DRAM_SIZE 0x9f00 26 #define ISP_LOAD_REG_SIZE 0x1000 27 #define ISP_FE_TBL_SIZE 0x0600 28 #define ISP_BAYER_TABLE_SIZE 0x5600 29 #define ISP_RGB_TABLE_SIZE 0x1c00 30 #define ISP_YUV_TABLE_SIZE 0x1700 31 32 #define ISP_SAVE_DRAM_SIZE 0xea40 33 #define ISP_SAVE_REG_SIZE 0x0040 34 #define ISP_STATISTIC_SIZE 0xea00 35 #define ISP_STAT_TOTAL_SIZE 0xea40 36 37 #define ISP_S1_LC_R_TBL_SIZE 0x0200 38 #define ISP_S1_LC_G_TBL_SIZE 0x0200 39 #define ISP_S1_LC_B_TBL_SIZE 0x0200 40 #define ISP_S1_LC_TBL_SIZE 0x0600 41 42 #define ISP_S0_LC_R_TBL_SIZE 0x0200 43 #define ISP_S0_LC_G_TBL_SIZE 0x0200 44 #define ISP_S0_LC_B_TBL_SIZE 0x0200 45 #define ISP_S0_LC_TBL_SIZE 0x0600 46 47 #define ISP_WDR_GAMMA_FE_MEM_SIZE 0x2000 48 #define ISP_WDR_GAMMA_BE_MEM_SIZE 0x2000 49 50 #define ISP_LSC_TBL_SIZE 0x0800 51 #define ISP_D3D_K_3D_INCREASE_SIZE 0x0100 52 #define ISP_D3D_DIFF_TBL_SIZE 0x0100 53 #define ISP_PLTM_MERGE_H_TBL_SIZE 0x0100 54 #define ISP_PLTM_MERGE_V_TBL_SIZE 0x0100 55 #define ISP_PLTM_POW_TBL_SIZE 0x0200 56 #define ISP_PLTM_F_TBL_SIZE 0x0200 57 58 #define ISP_SATURATION_TBL_SIZE 0x0200 59 #define ISP_RGB_DRC_TBL_SIZE 0x0200 60 #define ISP_GAMMA_MEM_SIZE 0x1000 61 #define ISP_DEHAZE_PP_TBL_SIZE 0x0100 62 #define ISP_DEHAZE_PD_TBL_SIZE 0x0100 63 #define ISP_DEHAZE_TR_TBL_SIZE 0x0100 64 #define ISP_DEHAZE_BT_TBL_SIZE 0x0400 65 66 #define ISP_CEM_TBL0_SIZE 0x0cc0 67 #define ISP_CEM_TBL1_SIZE 0x0a40 68 69 #define ISP_STAT_HIST_MEM_SIZE 0x0200 70 #define ISP_STAT_AE_MEM_SIZE 0x4800 71 #define ISP_STAT_AF_MEM_SIZE 0x3c00 72 #define ISP_STAT_AF_IIR_ACC_SIZE 0x0c00 73 #define ISP_STAT_AF_FIR_ACC_SIZE 0x0c00 74 #define ISP_STAT_AF_IIR_CNT_SIZE 0x0c00 75 #define ISP_STAT_AF_FIR_CNT_SIZE 0x0c00 76 #define ISP_STAT_AF_HL_CNT_SIZE 0x0c00 77 #define ISP_STAT_AFS_SIZE 0x0200 78 #define ISP_STAT_AWB_RGB_SIZE 0x4800 79 #define ISP_STAT_AWB_CNT_SIZE 0x0c00 80 #define ISP_STAT_PLTM_LST_SIZE 0x0600 81 #define ISP_STAT_DEHAZE_DC_HIST_SIZE 0x0400 82 #define ISP_STAT_DEHAZE_BT_SIZE 0x0400 83 84 /* 85 * update table 86 */ 87 #define LINEAR_UPDATE (1 << 1) 88 #define LENS_UPDATE (1 << 2) 89 #define GAMMA_UPDATE (1 << 3) 90 #define DRC_UPDATE (1 << 4) 91 #define SATU_UPDATE (1 << 5) 92 #define WDR_UPDATE (1 << 6) 93 #define D3D_UPDATE (1 << 7) 94 #define PLTM_UPDATE (1 << 8) 95 #define CEM_UPDATE (1 << 9) 96 #define DEHAZE_UPDATE (1 << 11) 97 #define S1_PARA_READY (1 << 12) 98 #define S1_LINEAR_UPDATE (1 << 13) 99 100 101 #define TABLE_UPDATE_ALL 0xffffffff 102 103 /* 104 * ISP Module enable 105 */ 106 #define S1_BLC_EN (1 << 0) 107 #define S1_LC_EN (1 << 1) 108 109 #define AE_EN (1 << 0) 110 #define LC_EN (1 << 1) 111 #define WDR_EN (1 << 2) 112 #define DPC_EN (1 << 3) 113 #define D2D_EN (1 << 4) 114 #define D3D_EN (1 << 5) 115 #define AWB_EN (1 << 6) 116 #define WB_EN (1 << 7) 117 #define LSC_EN (1 << 8) 118 #define BGC_EN (1 << 9) 119 #define SHARP_EN (1 << 10) 120 #define AF_EN (1 << 11) 121 #define RGB2RGB_EN (1 << 12) 122 #define RGB_DRC_EN (1 << 13) 123 #define PLTM_EN (1 << 14) 124 #define CEM_EN (1 << 15) 125 #define AFS_EN (1 << 16) 126 #define HIST_EN (1 << 17) 127 #define BLC_EN (1 << 18) 128 #define DG_EN (1 << 19) 129 #define SO_EN (1 << 20) 130 #define CTC_EN (1 << 21) 131 #define CNR_EN (1 << 23) 132 #define SATU_EN (1 << 24) 133 #define DEHAZE_EN (1 << 25) 134 135 #define SRC0_EN (1 << 31) 136 137 #define ISP_MODULE_EN_ALL (0xffffffff) 138 139 /* 140 * ISP interrupt enable 141 */ 142 #define FINISH_INT_EN (1 << 0) 143 #define S0_START_INT_EN (1 << 1) 144 #define S1_START_INT_EN (1 << 2) 145 #define PARA_SAVE_INT_EN (1 << 3) 146 #define S0_PARA_LOAD_INT_EN (1 << 4) 147 #define S1_PARA_LOAD_INT_EN (1 << 5) 148 #define S0_FIFO_INT_EN (1 << 6) 149 #define S1_FIFO_INT_EN (1 << 7) 150 #define S0_N_LINE_START_INT_EN (1 << 8) 151 #define S1_N_LINE_START_INT_EN (1 << 9) 152 #define S0_FRAME_ERROR_INT_EN (1 << 10) 153 #define S1_FRAME_ERROR_INT_EN (1 << 11) 154 #define S0_FRAME_LOST_INT_EN (1 << 12) 155 #define S1_FRAME_LOST_INT_EN (1 << 13) 156 #define S0_HB_SHORT_INT_EN (1 << 14) 157 #define S1_HB_SHORT_INT_EN (1 << 15) 158 #define SRAM_CLR_INT_EN (1 << 16) 159 #define DDR_W_FINISH_INT_EN (1 << 17) 160 161 #define ISP_IRQ_EN_ALL 0xffffffff 162 163 #define FINISH_PD (1 << 0) 164 #define S0_START_PD (1 << 1) 165 #define S1_START_PD (1 << 2) 166 #define PARA_SAVE_PD (1 << 3) 167 #define S0_PARA_LOAD_PD (1 << 4) 168 #define S1_PARA_LOAD_PD (1 << 5) 169 #define S0_FIFO_OF_PD (1 << 6) 170 #define S1_FIFO_OF_PD (1 << 7) 171 #define S0_N_LINE_START_PD (1 << 8) 172 #define S1_N_LINE_START_PD (1 << 9) 173 #define S0_FRAME_ERROR_PD (1 << 10) 174 #define S1_FRAME_ERROR_PD (1 << 11) 175 #define S0_FRAME_LOST_PD (1 << 12) 176 #define S1_FRAME_LOST_PD (1 << 13) 177 #define S0_HB_SHORT_PD (1 << 14) 178 #define S1_HB_SHORT_PD (1 << 15) 179 #define SRAM_CLR_PD (1 << 16) 180 #define DDR_W_FINISH_PD (1 << 17) 181 #define FIFO_VALID_ST (1 << 31) 182 183 #define PARA_LOAD_PD S0_PARA_LOAD_PD 184 #define FRAME_ERROR_PD S0_FRAME_ERROR_PD 185 #define FRAME_LOST_PD S0_FRAME_LOST_PD 186 #define HB_SHORT_PD S0_HB_SHORT_PD 187 188 #define ISP_IRQ_STATUS_ALL 0xffffffff 189 190 #define D3D_W_FINISH_PD (1 << 0) 191 #define WDR_W_FINISH_PD (1 << 1) 192 #define S0_CIN_FIFO_OF_PD (1 << 2) 193 #define DPC_FIFO_OF_PD (1 << 3) 194 #define BIS_FIFO_OF_PD (1 << 5) 195 #define CNR_FIFO_OF_PD (1 << 6) 196 #define PLTM_FIFO_OF_PD (1 << 7) 197 #define D3D_WRITE_FIFO_OF_PD (1 << 8) 198 #define D3D_READ_FIFO_OF_PD (1 << 9) 199 #define WDR_WRITE_FIFO_OF_PD (1 << 11) 200 #define WDR_READ_FIFO_OF_PD (1 << 13) 201 #define S1_CIN_FIFO_OF_PD (1 << 15) 202 203 struct isp_wdr_mode_cfg { 204 unsigned char wdr_ch_seq; 205 unsigned char wdr_exp_seq; 206 unsigned char wdr_mode; 207 }; 208 209 enum isp_channel { 210 ISP_CH0 = 0, 211 ISP_CH1 = 1, 212 ISP_CH2 = 2, 213 ISP_CH3 = 3, 214 ISP_MAX_CH_NUM, 215 }; 216 217 struct isp_size { 218 u32 width; 219 u32 height; 220 }; 221 222 struct coor { 223 u32 hor; 224 u32 ver; 225 }; 226 227 struct isp_size_settings { 228 struct coor ob_start; 229 struct isp_size ob_black; 230 struct isp_size ob_valid; 231 u32 set_cnt; 232 }; 233 234 enum ready_flag { 235 PARA_NOT_READY = 0, 236 PARA_READY = 1, 237 }; 238 239 enum enable_flag { 240 DISABLE = 0, 241 ENABLE = 1, 242 }; 243 244 enum isp_input_seq { 245 ISP_BGGR = 4, 246 ISP_RGGB = 5, 247 ISP_GBRG = 6, 248 ISP_GRBG = 7, 249 }; 250 251 void bsp_isp_map_reg_addr(unsigned long id, unsigned long base); 252 void bsp_isp_map_load_dram_addr(unsigned long id, unsigned long base); 253 254 /*******isp control register which we can write directly to register*********/ 255 256 void bsp_isp_enable(unsigned long id, unsigned int en); 257 void bsp_isp_capture_start(unsigned long id); 258 void bsp_isp_capture_stop(unsigned long id); 259 void bsp_isp_ver_read_en(unsigned long id, unsigned int en); 260 void bsp_isp_set_input_fmt(unsigned long id, unsigned int fmt); 261 void bsp_isp_ch_enable(unsigned long id, int ch, int enable); 262 void bsp_isp_wdr_mode_cfg(unsigned long id, struct isp_wdr_mode_cfg *cfg); 263 void bsp_isp_set_line_int_num(unsigned long id, unsigned int line_num); 264 void bsp_isp_set_speed_mode(unsigned long id, unsigned int speed); 265 void bsp_isp_set_last_blank_cycle(unsigned long id, unsigned int blank); 266 void bsp_isp_debug_output_cfg(unsigned long id, int enable, int output_sel); 267 void bsp_isp_set_para_ready_mode(unsigned long id, int enable); 268 void bsp_isp_set_para_ready(unsigned long id, int ready); 269 void bsp_isp_update_table(unsigned long id, unsigned short table_update); 270 void bsp_isp_set_load_addr0(unsigned long id, dma_addr_t addr); 271 void bsp_isp_set_load_addr1(unsigned long id, dma_addr_t addr); 272 void bsp_isp_set_saved_addr(unsigned long id, unsigned long addr); 273 void bsp_isp_set_statistics_addr(unsigned long id, dma_addr_t addr); 274 void bsp_isp_irq_enable(unsigned long id, unsigned int irq_flag); 275 void bsp_isp_irq_disable(unsigned long id, unsigned int irq_flag); 276 unsigned int bsp_isp_get_irq_status(unsigned long id, unsigned int flag); 277 void bsp_isp_clr_irq_status(unsigned long id, unsigned int flag); 278 unsigned int bsp_isp_get_internal_status0(unsigned long id, unsigned int flag); 279 void bsp_isp_clr_internal_status0(unsigned long id, unsigned int flag); 280 unsigned int bsp_isp_get_internal_status1(unsigned long id); 281 unsigned int bsp_isp_get_isp_ver(unsigned long id, unsigned int *major, unsigned int *minor); 282 unsigned int bsp_isp_get_max_width(unsigned long id); 283 void bsp_isp_get_comp_fifo_max_layer(unsigned long id, unsigned int *wdr_fifo, unsigned int *d3d_fifo); 284 void bsp_isp_get_uncomp_fifo_max_layer(unsigned long id, unsigned int *wdr_fifo, unsigned int *d3d_fifo); 285 void bsp_isp_get_s0_ch_fmerr_cnt(unsigned long id, struct isp_size *size); 286 void bsp_isp_get_s1_ch_fmerr_cnt(unsigned long id, struct isp_size *size); 287 void bsp_isp_get_s0_ch_hb_cnt(unsigned long id, unsigned int *hb_max, unsigned int *hb_min); 288 void bsp_isp_get_s1_ch_hb_cnt(unsigned long id, unsigned int *hb_max, unsigned int *hb_min); 289 void bsp_isp_get_wdr_fifo_overflow_line(unsigned long id, unsigned int *decomp_line, unsigned int *comp_line); 290 void bsp_isp_get_d3d_fifo_overflow_line(unsigned long id, unsigned int *decomp_line, unsigned int *comp_line); 291 void bsp_isp_set_wdr_addr0(unsigned long id, dma_addr_t addr); 292 void bsp_isp_set_wdr_addr1(unsigned long id, dma_addr_t addr); 293 void bsp_isp_set_d3d_addr0(unsigned long id, dma_addr_t addr); 294 void bsp_isp_set_d3d_addr1(unsigned long id, dma_addr_t addr); 295 void bsp_isp_top_control(unsigned long id, int isp_num, int isp0_max_w); 296 void bsp_isp_set_fifo_mode(unsigned long id, unsigned int mode); 297 void bsp_isp_min_ddr_size(unsigned long id, unsigned int size); 298 void bsp_isp_fifo_raw_write(unsigned long id, unsigned int depth); 299 void bsp_isp_k_min_ddr_size(unsigned long id, unsigned int size); 300 301 /*******isp load register which we should write to ddr first*********/ 302 303 void bsp_isp_s1_module_enable(unsigned long id, unsigned int module_flag); 304 void bsp_isp_s1_module_disable(unsigned long id, unsigned int module_flag); 305 void bsp_isp_module_enable(unsigned long id, unsigned int module_flag); 306 void bsp_isp_module_disable(unsigned long id, unsigned int module_flag); 307 void bsp_isp_set_size(unsigned long id, struct isp_size_settings *size); 308 unsigned int bsp_isp_load_update_flag(unsigned long id); 309 310 #endif /*__ISP520__REG__CFG__H*/ 311