1 /*
2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-mipi/protocol/protocol_reg.c
3 *
4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 /*
18 * sunxi mipi protocol low-level interface
19 * Author:raymonxiu
20 */
21
22 #include "protocol_reg_i.h"
23 #include "protocol.h"
24 #include "protocol_reg.h"
25
26 MIPI_CSI2_CTL_t *mipi_csi2_ctl[MAX_MIPI_PTL];
27 MIPI_CSI2_CFG_t *mipi_csi2_cfg[MAX_MIPI_PTL];
28 MIPI_CSI2_VCDT_RX_t *mipi_csi2_vcdt_rx[MAX_MIPI_PTL];
29 MIPI_CSI2_RX_PKT_NUM_t *mipi_csi2_rx_pkt_num[MAX_MIPI_PTL];
30
31 MIPI_CSI2_CH_CFG_t *mipi_csi2_ch_cfg[MAX_MIPI_PTL];
32 MIPI_CSI2_CH_INT_EN_t *mipi_csi2_ch_int_en[MAX_MIPI_PTL];
33 MIPI_CSI2_CH_INT_PD_t *mipi_csi2_ch_int_pd[MAX_MIPI_PTL];
34 MIPI_CSI2_CH_DT_TRM_t *mipi_csi2_ch_dt_trm[MAX_MIPI_PTL];
35 MIPI_CSI2_CH_CUR_PH_t *mipi_csi2_ch_cur_ph[MAX_MIPI_PTL];
36 MIPI_CSI2_CH_ECC_t *mipi_csi2_ch_ecc[MAX_MIPI_PTL];
37 MIPI_CSI2_CH_CKS_t *mipi_csi2_ch_cks[MAX_MIPI_PTL];
38 MIPI_CSI2_CH_FRAME_NUM_t *mipi_csi2_ch_frame_num[MAX_MIPI_PTL];
39 MIPI_CSI2_CH_LINE_NUM_t *mipi_csi2_ch_line_num[MAX_MIPI_PTL];
40
ptcl_reg_map(unsigned int sel,unsigned long addr_base)41 int ptcl_reg_map(unsigned int sel, unsigned long addr_base)
42 {
43 if (sel >= MAX_MIPI_PTL)
44 return -1;
45
46 mipi_csi2_ctl[sel] =
47 (MIPI_CSI2_CTL_t *) (addr_base + MIPI_CSI2_CTL_OFF);
48 mipi_csi2_cfg[sel] =
49 (MIPI_CSI2_CFG_t *) (addr_base + MIPI_CSI2_CFG_OFF);
50 mipi_csi2_vcdt_rx[sel] =
51 (MIPI_CSI2_VCDT_RX_t *) (addr_base + MIPI_CSI2_VCDT_RX_OFF);
52 mipi_csi2_rx_pkt_num[sel] =
53 (MIPI_CSI2_RX_PKT_NUM_t *) (addr_base + MIPI_CSI2_RX_PKT_NUM_OFF);
54 mipi_csi2_ch_cfg[sel] =
55 (MIPI_CSI2_CH_CFG_t *) (addr_base + MIPI_CSI2_CH_CFG_OFF);
56 mipi_csi2_ch_int_en[sel] =
57 (MIPI_CSI2_CH_INT_EN_t *) (addr_base + MIPI_CSI2_CH_INT_EN_OFF);
58 mipi_csi2_ch_int_pd[sel] =
59 (MIPI_CSI2_CH_INT_PD_t *) (addr_base + MIPI_CSI2_CH_INT_PD_OFF);
60 mipi_csi2_ch_dt_trm[sel] =
61 (MIPI_CSI2_CH_DT_TRM_t *) (addr_base + MIPI_CSI2_CH_DT_TRM_OFF);
62 mipi_csi2_ch_cur_ph[sel] =
63 (MIPI_CSI2_CH_CUR_PH_t *) (addr_base + MIPI_CSI2_CH_CUR_PH_OFF);
64 mipi_csi2_ch_ecc[sel] =
65 (MIPI_CSI2_CH_ECC_t *) (addr_base + MIPI_CSI2_CH_ECC_OFF);
66 mipi_csi2_ch_cks[sel] =
67 (MIPI_CSI2_CH_CKS_t *) (addr_base + MIPI_CSI2_CH_CKS_OFF);
68 mipi_csi2_ch_frame_num[sel] =
69 (MIPI_CSI2_CH_FRAME_NUM_t *) (addr_base +
70 MIPI_CSI2_CH_FRAME_NUM_OFF);
71 mipi_csi2_ch_line_num[sel] =
72 (MIPI_CSI2_CH_LINE_NUM_t *) (addr_base + MIPI_CSI2_CH_LINE_NUM_OFF);
73
74 return 0;
75 }
76
ptcl_enable(unsigned int sel)77 void ptcl_enable(unsigned int sel)
78 {
79 mipi_csi2_ctl[sel]->bits.rst = 1;
80 mipi_csi2_ctl[sel]->bits.en = 1;
81 }
82
ptcl_disable(unsigned int sel)83 void ptcl_disable(unsigned int sel)
84 {
85 mipi_csi2_ctl[sel]->bits.en = 0;
86 mipi_csi2_ctl[sel]->bits.rst = 0;
87 }
88
ptcl_set_data_lane(unsigned int sel,unsigned char lane_num)89 void ptcl_set_data_lane(unsigned int sel, unsigned char lane_num)
90 {
91 mipi_csi2_cfg[sel]->bits.dl_cfg = lane_num - 1;
92 }
93
ptcl_get_data_lane(unsigned int sel)94 unsigned char ptcl_get_data_lane(unsigned int sel)
95 {
96 return mipi_csi2_cfg[sel]->bits.dl_cfg + 1;
97 }
98
ptcl_set_pl_bit_order(unsigned int sel,enum bit_order pl_bit_ord)99 void ptcl_set_pl_bit_order(unsigned int sel, enum bit_order pl_bit_ord)
100 {
101 mipi_csi2_cfg[sel]->bits.pl_bit_ord = pl_bit_ord;
102 }
103
ptcl_get_pl_bit_order(unsigned int sel)104 enum bit_order ptcl_get_pl_bit_order(unsigned int sel)
105 {
106 return (enum bit_order)mipi_csi2_cfg[sel]->bits.pl_bit_ord;
107 }
108
ptcl_set_ph_bit_order(unsigned int sel,enum bit_order ph_bit_ord)109 void ptcl_set_ph_bit_order(unsigned int sel, enum bit_order ph_bit_ord)
110 {
111 mipi_csi2_cfg[sel]->bits.ph_bit_ord = ph_bit_ord;
112 }
113
ptcl_get_ph_bit_order(unsigned int sel)114 enum bit_order ptcl_get_ph_bit_order(unsigned int sel)
115 {
116 return (enum bit_order)mipi_csi2_cfg[sel]->bits.ph_bit_ord;
117 }
118
ptcl_set_ph_byte_order(unsigned int sel,enum byte_order ph_byte_order)119 void ptcl_set_ph_byte_order(unsigned int sel, enum byte_order ph_byte_order)
120 {
121 mipi_csi2_cfg[sel]->bits.ph_byte_ord = ph_byte_order;
122 }
123
ptcl_get_ph_byte_order(unsigned int sel)124 enum byte_order ptcl_get_ph_byte_order(unsigned int sel)
125 {
126 return (enum byte_order)mipi_csi2_cfg[sel]->bits.ph_byte_ord;
127 }
128
ptcl_set_total_ch(unsigned int sel,unsigned char ch_num)129 void ptcl_set_total_ch(unsigned int sel, unsigned char ch_num)
130 {
131 mipi_csi2_cfg[sel]->bits.ch_mode = ch_num - 1;
132 }
133
ptcl_get_total_ch(unsigned int sel)134 unsigned char ptcl_get_total_ch(unsigned int sel)
135 {
136 return mipi_csi2_cfg[sel]->bits.ch_mode;
137 }
138
ptcl_set_vc(unsigned int sel,unsigned char ch,unsigned char vc)139 void ptcl_set_vc(unsigned int sel, unsigned char ch, unsigned char vc)
140 {
141 switch (ch) {
142 case 0:
143 mipi_csi2_vcdt_rx[sel]->bits.ch0_vc = vc;
144 break;
145 case 1:
146 mipi_csi2_vcdt_rx[sel]->bits.ch1_vc = vc;
147 break;
148 case 2:
149 mipi_csi2_vcdt_rx[sel]->bits.ch2_vc = vc;
150 break;
151 case 3:
152 mipi_csi2_vcdt_rx[sel]->bits.ch3_vc = vc;
153 break;
154 default:
155 break;
156 }
157 }
158
ptcl_get_vc(unsigned int sel,unsigned char ch)159 unsigned char ptcl_get_vc(unsigned int sel, unsigned char ch)
160 {
161 switch (ch) {
162 case 0:
163 return mipi_csi2_vcdt_rx[sel]->bits.ch0_vc;
164 case 1:
165 return mipi_csi2_vcdt_rx[sel]->bits.ch1_vc;
166 case 2:
167 return mipi_csi2_vcdt_rx[sel]->bits.ch2_vc;
168 case 3:
169 return mipi_csi2_vcdt_rx[sel]->bits.ch2_vc;
170 default:
171 return -1;
172 }
173 }
174
ptcl_set_dt(unsigned int sel,unsigned char ch,enum pkt_fmt dt)175 void ptcl_set_dt(unsigned int sel, unsigned char ch, enum pkt_fmt dt)
176 {
177 switch (ch) {
178 case 0:
179 mipi_csi2_vcdt_rx[sel]->bits.ch0_dt = dt;
180 break;
181 case 1:
182 mipi_csi2_vcdt_rx[sel]->bits.ch1_dt = dt;
183 break;
184 case 2:
185 mipi_csi2_vcdt_rx[sel]->bits.ch2_dt = dt;
186 break;
187 case 3:
188 mipi_csi2_vcdt_rx[sel]->bits.ch3_dt = dt;
189 break;
190 default:
191 break;
192 }
193 }
194
ptcl_get_dt(unsigned int sel,unsigned char ch)195 enum pkt_fmt ptcl_get_dt(unsigned int sel, unsigned char ch)
196 {
197 switch (ch) {
198 case 0:
199 return (enum pkt_fmt)mipi_csi2_vcdt_rx[sel]->bits.ch0_dt;
200 case 1:
201 return (enum pkt_fmt)mipi_csi2_vcdt_rx[sel]->bits.ch1_dt;
202 case 2:
203 return (enum pkt_fmt)mipi_csi2_vcdt_rx[sel]->bits.ch2_dt;
204 case 3:
205 return (enum pkt_fmt)mipi_csi2_vcdt_rx[sel]->bits.ch3_dt;
206 default:
207 return -1;
208 }
209 }
210
ptcl_set_src_type(unsigned int sel,unsigned char ch,enum source_type src_type)211 void ptcl_set_src_type(unsigned int sel, unsigned char ch,
212 enum source_type src_type)
213 {
214 (mipi_csi2_ch_cfg[sel] + ch * MIPI_CSI2_CH_OFF)->bits.src_sel =
215 src_type;
216 }
217
ptcl_get_src_type(unsigned int sel,unsigned char ch)218 enum source_type ptcl_get_src_type(unsigned int sel, unsigned char ch)
219 {
220 return (enum byte_order)(mipi_csi2_ch_cfg[sel] +
221 ch * MIPI_CSI2_CH_OFF)->bits.src_sel;
222 }
223
ptcl_set_line_sync(unsigned int sel,unsigned char ch,enum line_sync ls_mode)224 void ptcl_set_line_sync(unsigned int sel, unsigned char ch,
225 enum line_sync ls_mode)
226 {
227 (mipi_csi2_ch_cfg[sel] + ch * MIPI_CSI2_CH_OFF)->bits.line_sync =
228 ls_mode;
229 }
230
ptcl_get_line_sync(unsigned int sel,unsigned char ch)231 enum line_sync ptcl_get_line_sync(unsigned int sel, unsigned char ch)
232 {
233 return (enum line_sync)(mipi_csi2_ch_cfg[sel] +
234 ch * MIPI_CSI2_CH_OFF)->bits.line_sync;
235 }
236
ptcl_int_enable(unsigned int sel,unsigned char ch,enum protocol_int int_flag)237 void ptcl_int_enable(unsigned int sel, unsigned char ch,
238 enum protocol_int int_flag)
239 {
240 switch (int_flag) {
241 case FIFO_OVER_INT:
242 (mipi_csi2_ch_int_en[sel] +
243 ch * MIPI_CSI2_CH_OFF)->bits.fifo_over_int = 1;
244 break;
245 case FRAME_END_SYNC_INT:
246 (mipi_csi2_ch_int_en[sel] +
247 ch * MIPI_CSI2_CH_OFF)->bits.frame_end_sync_int = 1;
248 break;
249 case FRAME_START_SYNC_INT:
250 (mipi_csi2_ch_int_en[sel] +
251 ch * MIPI_CSI2_CH_OFF)->bits.frame_start_sync_int = 1;
252 break;
253 case LINE_END_SYNC_INT:
254 (mipi_csi2_ch_int_en[sel] +
255 ch * MIPI_CSI2_CH_OFF)->bits.line_end_sync_int = 1;
256 break;
257 case LINE_START_SYNC_INT:
258 (mipi_csi2_ch_int_en[sel] +
259 ch * MIPI_CSI2_CH_OFF)->bits.line_start_sync_int = 1;
260 break;
261 case PH_UPDATE_INT:
262 (mipi_csi2_ch_int_en[sel] +
263 ch * MIPI_CSI2_CH_OFF)->bits.ph_update_int = 1;
264 break;
265 case PF_INT:
266 (mipi_csi2_ch_int_en[sel] +
267 ch * MIPI_CSI2_CH_OFF)->bits.pf_int = 1;
268 break;
269 case EMB_DATA_INT:
270 (mipi_csi2_ch_int_en[sel] +
271 ch * MIPI_CSI2_CH_OFF)->bits.emb_data_int = 1;
272 break;
273 case FRAME_SYNC_ERR_INT:
274 (mipi_csi2_ch_int_en[sel] +
275 ch * MIPI_CSI2_CH_OFF)->bits.frame_sync_err_int = 1;
276 break;
277 case LINE_SYNC_ERR_INT:
278 (mipi_csi2_ch_int_en[sel] +
279 ch * MIPI_CSI2_CH_OFF)->bits.line_sync_err_int = 1;
280 break;
281 case ECC_ERR_INT:
282 (mipi_csi2_ch_int_en[sel] +
283 ch * MIPI_CSI2_CH_OFF)->bits.ecc_err_int = 1;
284 break;
285 case ECC_WRN_INT:
286 (mipi_csi2_ch_int_en[sel] +
287 ch * MIPI_CSI2_CH_OFF)->bits.ecc_wrn_int = 1;
288 break;
289 case CHKSUM_ERR_INT:
290 (mipi_csi2_ch_int_en[sel] +
291 ch * MIPI_CSI2_CH_OFF)->bits.chksum_err_int = 1;
292 break;
293 case EOT_ERR_INT:
294 (mipi_csi2_ch_int_en[sel] +
295 ch * MIPI_CSI2_CH_OFF)->bits.eot_err_int = 1;
296 break;
297 default:
298 break;
299 }
300 }
301
bsp_data_formats_enable(unsigned int sel,unsigned char type)302 void bsp_data_formats_enable(unsigned int sel, unsigned char type)
303 {
304 switch (type) {
305 case 0x0:
306 mipi_csi2_ch_dt_trm[sel]->bits.fs = 1;
307 break;
308 case 0x1:
309 mipi_csi2_ch_dt_trm[sel]->bits.fe = 1;
310 break;
311 case 0x2:
312 mipi_csi2_ch_dt_trm[sel]->bits.ls = 1;
313 break;
314 case 0x3:
315 mipi_csi2_ch_dt_trm[sel]->bits.le = 1;
316 break;
317 case 0x8:
318 mipi_csi2_ch_dt_trm[sel]->bits.gs0 = 1;
319 break;
320 case 0x9:
321 mipi_csi2_ch_dt_trm[sel]->bits.gs1 = 1;
322 break;
323 case 0xa:
324 mipi_csi2_ch_dt_trm[sel]->bits.gs2 = 1;
325 break;
326 case 0xb:
327 mipi_csi2_ch_dt_trm[sel]->bits.gs3 = 1;
328 break;
329 case 0xc:
330 mipi_csi2_ch_dt_trm[sel]->bits.gs4 = 1;
331 break;
332 case 0xd:
333 mipi_csi2_ch_dt_trm[sel]->bits.gs5 = 1;
334 break;
335 case 0xe:
336 mipi_csi2_ch_dt_trm[sel]->bits.gs6 = 1;
337 break;
338 case 0xf:
339 mipi_csi2_ch_dt_trm[sel]->bits.gs7 = 1;
340 break;
341 case 0x10:
342 mipi_csi2_ch_dt_trm[sel]->bits.gl = 1;
343 break;
344 case 0x11:
345 mipi_csi2_ch_dt_trm[sel]->bits.yuv = 1;
346 break;
347 case 0x12:
348 mipi_csi2_ch_dt_trm[sel]->bits.rgb = 1;
349 break;
350 case 0x13:
351 mipi_csi2_ch_dt_trm[sel]->bits.raw = 1;
352 break;
353 default:
354 mipi_csi2_ch_dt_trm[sel]->bits.raw = 1;
355 break;
356 }
357 }
358
bsp_data_formats_disable(unsigned int sel,unsigned char type)359 void bsp_data_formats_disable(unsigned int sel, unsigned char type)
360 {
361 switch (type) {
362 case 0x0:
363 mipi_csi2_ch_dt_trm[sel]->bits.fs = 0;
364 break;
365 case 0x1:
366 mipi_csi2_ch_dt_trm[sel]->bits.fe = 0;
367 break;
368 case 0x2:
369 mipi_csi2_ch_dt_trm[sel]->bits.ls = 0;
370 break;
371 case 0x3:
372 mipi_csi2_ch_dt_trm[sel]->bits.le = 0;
373 break;
374 case 0x8:
375 mipi_csi2_ch_dt_trm[sel]->bits.gs0 = 0;
376 break;
377 case 0x9:
378 mipi_csi2_ch_dt_trm[sel]->bits.gs1 = 0;
379 break;
380 case 0xa:
381 mipi_csi2_ch_dt_trm[sel]->bits.gs2 = 0;
382 break;
383 case 0xb:
384 mipi_csi2_ch_dt_trm[sel]->bits.gs3 = 0;
385 break;
386 case 0xc:
387 mipi_csi2_ch_dt_trm[sel]->bits.gs4 = 0;
388 break;
389 case 0xd:
390 mipi_csi2_ch_dt_trm[sel]->bits.gs5 = 0;
391 break;
392 case 0xe:
393 mipi_csi2_ch_dt_trm[sel]->bits.gs6 = 0;
394 break;
395 case 0xf:
396 mipi_csi2_ch_dt_trm[sel]->bits.gs7 = 0;
397 break;
398 case 0x10:
399 mipi_csi2_ch_dt_trm[sel]->bits.gl = 0;
400 break;
401 case 0x11:
402 mipi_csi2_ch_dt_trm[sel]->bits.yuv = 0;
403 break;
404 case 0x12:
405 mipi_csi2_ch_dt_trm[sel]->bits.rgb = 0;
406 break;
407 case 0x13:
408 mipi_csi2_ch_dt_trm[sel]->bits.raw = 0;
409 break;
410 default:
411 mipi_csi2_ch_dt_trm[sel]->bits.raw = 0;
412 break;
413 }
414 }
415
416
ptcl_int_disable(unsigned int sel,unsigned char ch,enum protocol_int int_flag)417 void ptcl_int_disable(unsigned int sel, unsigned char ch,
418 enum protocol_int int_flag)
419 {
420 switch (int_flag) {
421 case FIFO_OVER_INT:
422 (mipi_csi2_ch_int_en[sel] +
423 ch * MIPI_CSI2_CH_OFF)->bits.fifo_over_int = 0;
424 break;
425 case FRAME_END_SYNC_INT:
426 (mipi_csi2_ch_int_en[sel] +
427 ch * MIPI_CSI2_CH_OFF)->bits.frame_end_sync_int = 0;
428 break;
429 case FRAME_START_SYNC_INT:
430 (mipi_csi2_ch_int_en[sel] +
431 ch * MIPI_CSI2_CH_OFF)->bits.frame_start_sync_int = 0;
432 break;
433 case LINE_END_SYNC_INT:
434 (mipi_csi2_ch_int_en[sel] +
435 ch * MIPI_CSI2_CH_OFF)->bits.line_end_sync_int = 0;
436 break;
437 case LINE_START_SYNC_INT:
438 (mipi_csi2_ch_int_en[sel] +
439 ch * MIPI_CSI2_CH_OFF)->bits.line_start_sync_int = 0;
440 break;
441 case PH_UPDATE_INT:
442 (mipi_csi2_ch_int_en[sel] +
443 ch * MIPI_CSI2_CH_OFF)->bits.ph_update_int = 0;
444 break;
445 case PF_INT:
446 (mipi_csi2_ch_int_en[sel] +
447 ch * MIPI_CSI2_CH_OFF)->bits.pf_int = 0;
448 break;
449 case EMB_DATA_INT:
450 (mipi_csi2_ch_int_en[sel] +
451 ch * MIPI_CSI2_CH_OFF)->bits.emb_data_int = 0;
452 break;
453 case FRAME_SYNC_ERR_INT:
454 (mipi_csi2_ch_int_en[sel] +
455 ch * MIPI_CSI2_CH_OFF)->bits.frame_sync_err_int = 0;
456 break;
457 case LINE_SYNC_ERR_INT:
458 (mipi_csi2_ch_int_en[sel] +
459 ch * MIPI_CSI2_CH_OFF)->bits.line_sync_err_int = 0;
460 break;
461 case ECC_ERR_INT:
462 (mipi_csi2_ch_int_en[sel] +
463 ch * MIPI_CSI2_CH_OFF)->bits.ecc_err_int = 0;
464 break;
465 case ECC_WRN_INT:
466 (mipi_csi2_ch_int_en[sel] +
467 ch * MIPI_CSI2_CH_OFF)->bits.ecc_wrn_int = 0;
468 break;
469 case CHKSUM_ERR_INT:
470 (mipi_csi2_ch_int_en[sel] +
471 ch * MIPI_CSI2_CH_OFF)->bits.chksum_err_int = 0;
472 break;
473 case EOT_ERR_INT:
474 (mipi_csi2_ch_int_en[sel] +
475 ch * MIPI_CSI2_CH_OFF)->bits.eot_err_int = 0;
476 break;
477 default:
478 break;
479 }
480 }
481
ptcl_clear_int_status(unsigned int sel,unsigned char ch,enum protocol_int int_flag)482 void ptcl_clear_int_status(unsigned int sel, unsigned char ch,
483 enum protocol_int int_flag)
484 {
485 switch (int_flag) {
486 case FIFO_OVER_INT:
487 (mipi_csi2_ch_int_pd[sel] +
488 ch * MIPI_CSI2_CH_OFF)->bits.fifo_over_pd = 1;
489 break;
490 case FRAME_END_SYNC_INT:
491 (mipi_csi2_ch_int_pd[sel] +
492 ch * MIPI_CSI2_CH_OFF)->bits.frame_end_sync_pd = 1;
493 break;
494 case FRAME_START_SYNC_INT:
495 (mipi_csi2_ch_int_pd[sel] +
496 ch * MIPI_CSI2_CH_OFF)->bits.frame_start_sync_pd = 1;
497 break;
498 case LINE_END_SYNC_INT:
499 (mipi_csi2_ch_int_pd[sel] +
500 ch * MIPI_CSI2_CH_OFF)->bits.line_end_sync_pd = 1;
501 break;
502 case LINE_START_SYNC_INT:
503 (mipi_csi2_ch_int_pd[sel] +
504 ch * MIPI_CSI2_CH_OFF)->bits.line_start_sync_pd = 1;
505 break;
506 case PH_UPDATE_INT:
507 (mipi_csi2_ch_int_pd[sel] +
508 ch * MIPI_CSI2_CH_OFF)->bits.ph_update_pd = 1;
509 break;
510 case PF_INT:
511 (mipi_csi2_ch_int_pd[sel] + ch * MIPI_CSI2_CH_OFF)->bits.pf_pd =
512 1;
513 break;
514 case EMB_DATA_INT:
515 (mipi_csi2_ch_int_pd[sel] +
516 ch * MIPI_CSI2_CH_OFF)->bits.emb_data_pd = 1;
517 break;
518 case FRAME_SYNC_ERR_INT:
519 (mipi_csi2_ch_int_pd[sel] +
520 ch * MIPI_CSI2_CH_OFF)->bits.frame_sync_err_pd = 1;
521 break;
522 case LINE_SYNC_ERR_INT:
523 (mipi_csi2_ch_int_pd[sel] +
524 ch * MIPI_CSI2_CH_OFF)->bits.line_sync_err_pd = 1;
525 break;
526 case ECC_ERR_INT:
527 (mipi_csi2_ch_int_pd[sel] +
528 ch * MIPI_CSI2_CH_OFF)->bits.ecc_err_pd = 1;
529 break;
530 case ECC_WRN_INT:
531 (mipi_csi2_ch_int_pd[sel] +
532 ch * MIPI_CSI2_CH_OFF)->bits.ecc_wrn_pd = 1;
533 break;
534 case CHKSUM_ERR_INT:
535 (mipi_csi2_ch_int_pd[sel] +
536 ch * MIPI_CSI2_CH_OFF)->bits.chksum_err_pd = 1;
537 break;
538 case EOT_ERR_INT:
539 (mipi_csi2_ch_int_pd[sel] +
540 ch * MIPI_CSI2_CH_OFF)->bits.eot_err_pd = 1;
541 break;
542 default:
543 break;
544 }
545 }
546
ptcl_get_int_status(unsigned int sel,unsigned char ch,enum protocol_int int_flag)547 unsigned char ptcl_get_int_status(unsigned int sel, unsigned char ch,
548 enum protocol_int int_flag)
549 {
550 switch (int_flag) {
551 case FIFO_OVER_INT:
552 return (mipi_csi2_ch_int_pd[sel] +
553 ch * MIPI_CSI2_CH_OFF)->bits.fifo_over_pd;
554 case FRAME_END_SYNC_INT:
555 return (mipi_csi2_ch_int_pd[sel] +
556 ch * MIPI_CSI2_CH_OFF)->bits.frame_end_sync_pd;
557 case FRAME_START_SYNC_INT:
558 return (mipi_csi2_ch_int_pd[sel] +
559 ch * MIPI_CSI2_CH_OFF)->bits.frame_start_sync_pd;
560 case LINE_END_SYNC_INT:
561 return (mipi_csi2_ch_int_pd[sel] +
562 ch * MIPI_CSI2_CH_OFF)->bits.line_end_sync_pd;
563 case LINE_START_SYNC_INT:
564 return (mipi_csi2_ch_int_pd[sel] +
565 ch * MIPI_CSI2_CH_OFF)->bits.line_start_sync_pd;
566 case PH_UPDATE_INT:
567 return (mipi_csi2_ch_int_pd[sel] +
568 ch * MIPI_CSI2_CH_OFF)->bits.ph_update_pd;
569 case PF_INT:
570 return (mipi_csi2_ch_int_pd[sel] +
571 ch * MIPI_CSI2_CH_OFF)->bits.pf_pd;
572 case EMB_DATA_INT:
573 return (mipi_csi2_ch_int_pd[sel] +
574 ch * MIPI_CSI2_CH_OFF)->bits.emb_data_pd;
575 case FRAME_SYNC_ERR_INT:
576 return (mipi_csi2_ch_int_pd[sel] +
577 ch * MIPI_CSI2_CH_OFF)->bits.frame_sync_err_pd;
578 case LINE_SYNC_ERR_INT:
579 return (mipi_csi2_ch_int_pd[sel] +
580 ch * MIPI_CSI2_CH_OFF)->bits.line_sync_err_pd;
581 case ECC_ERR_INT:
582 return (mipi_csi2_ch_int_pd[sel] +
583 ch * MIPI_CSI2_CH_OFF)->bits.ecc_err_pd;
584 case ECC_WRN_INT:
585 return (mipi_csi2_ch_int_pd[sel] +
586 ch * MIPI_CSI2_CH_OFF)->bits.ecc_wrn_pd;
587 case CHKSUM_ERR_INT:
588 return (mipi_csi2_ch_int_pd[sel] +
589 ch * MIPI_CSI2_CH_OFF)->bits.chksum_err_pd;
590 case EOT_ERR_INT:
591 return (mipi_csi2_ch_int_pd[sel] +
592 ch * MIPI_CSI2_CH_OFF)->bits.eot_err_pd;
593 default:
594 return -1;
595 }
596 }
597