1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef __STM32F4xx_LL_BUS_H
39 #define __STM32F4xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32f4xx.h"
47
48 /** @addtogroup STM32F4xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
65 * @{
66 */
67
68 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
69 * @{
70 */
71 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
72 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
73 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
74 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
75 #if defined(GPIOD)
76 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
77 #endif /* GPIOD */
78 #if defined(GPIOE)
79 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
80 #endif /* GPIOE */
81 #if defined(GPIOF)
82 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
83 #endif /* GPIOF */
84 #if defined(GPIOG)
85 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
86 #endif /* GPIOG */
87 #if defined(GPIOH)
88 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
89 #endif /* GPIOH */
90 #if defined(GPIOI)
91 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
92 #endif /* GPIOI */
93 #if defined(GPIOJ)
94 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
95 #endif /* GPIOJ */
96 #if defined(GPIOK)
97 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
98 #endif /* GPIOK */
99 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
100 #if defined(RCC_AHB1ENR_BKPSRAMEN)
101 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
102 #endif /* RCC_AHB1ENR_BKPSRAMEN */
103 #if defined(RCC_AHB1ENR_CCMDATARAMEN)
104 #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
105 #endif /* RCC_AHB1ENR_CCMDATARAMEN */
106 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
107 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
108 #if defined(RCC_AHB1ENR_RNGEN)
109 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
110 #endif /* RCC_AHB1ENR_RNGEN */
111 #if defined(DMA2D)
112 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
113 #endif /* DMA2D */
114 #if defined(ETH)
115 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
116 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
117 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
118 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
119 #endif /* ETH */
120 #if defined(USB_OTG_HS)
121 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
122 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
123 #endif /* USB_OTG_HS */
124 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
125 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
126 #if defined(RCC_AHB1LPENR_SRAM2LPEN)
127 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
128 #endif /* RCC_AHB1LPENR_SRAM2LPEN */
129 #if defined(RCC_AHB1LPENR_SRAM3LPEN)
130 #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
131 #endif /* RCC_AHB1LPENR_SRAM3LPEN */
132 /**
133 * @}
134 */
135
136 #if defined(RCC_AHB2_SUPPORT)
137 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
138 * @{
139 */
140 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
141 #if defined(DCMI)
142 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
143 #endif /* DCMI */
144 #if defined(CRYP)
145 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
146 #endif /* CRYP */
147 #if defined(AES)
148 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
149 #endif /* AES */
150 #if defined(HASH)
151 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
152 #endif /* HASH */
153 #if defined(RCC_AHB2ENR_RNGEN)
154 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
155 #endif /* RCC_AHB2ENR_RNGEN */
156 #if defined(USB_OTG_FS)
157 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
158 #endif /* USB_OTG_FS */
159 /**
160 * @}
161 */
162 #endif /* RCC_AHB2_SUPPORT */
163
164 #if defined(RCC_AHB3_SUPPORT)
165 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
166 * @{
167 */
168 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
169 #if defined(FSMC_Bank1)
170 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
171 #endif /* FSMC_Bank1 */
172 #if defined(FMC_Bank1)
173 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
174 #endif /* FMC_Bank1 */
175 #if defined(QUADSPI)
176 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
177 #endif /* QUADSPI */
178 /**
179 * @}
180 */
181 #endif /* RCC_AHB3_SUPPORT */
182
183 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
184 * @{
185 */
186 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
187 #if defined(TIM2)
188 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
189 #endif /* TIM2 */
190 #if defined(TIM3)
191 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
192 #endif /* TIM3 */
193 #if defined(TIM4)
194 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
195 #endif /* TIM4 */
196 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
197 #if defined(TIM6)
198 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
199 #endif /* TIM6 */
200 #if defined(TIM7)
201 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
202 #endif /* TIM7 */
203 #if defined(TIM12)
204 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
205 #endif /* TIM12 */
206 #if defined(TIM13)
207 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
208 #endif /* TIM13 */
209 #if defined(TIM14)
210 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
211 #endif /* TIM14 */
212 #if defined(LPTIM1)
213 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
214 #endif /* LPTIM1 */
215 #if defined(RCC_APB1ENR_RTCAPBEN)
216 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
217 #endif /* RCC_APB1ENR_RTCAPBEN */
218 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
219 #if defined(SPI2)
220 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
221 #endif /* SPI2 */
222 #if defined(SPI3)
223 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
224 #endif /* SPI3 */
225 #if defined(SPDIFRX)
226 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
227 #endif /* SPDIFRX */
228 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
229 #if defined(USART3)
230 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
231 #endif /* USART3 */
232 #if defined(UART4)
233 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
234 #endif /* UART4 */
235 #if defined(UART5)
236 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
237 #endif /* UART5 */
238 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
239 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
240 #if defined(I2C3)
241 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
242 #endif /* I2C3 */
243 #if defined(FMPI2C1)
244 #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
245 #endif /* FMPI2C1 */
246 #if defined(CAN1)
247 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
248 #endif /* CAN1 */
249 #if defined(CAN2)
250 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
251 #endif /* CAN2 */
252 #if defined(CAN3)
253 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
254 #endif /* CAN3 */
255 #if defined(CEC)
256 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
257 #endif /* CEC */
258 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
259 #if defined(DAC1)
260 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
261 #endif /* DAC1 */
262 #if defined(UART7)
263 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
264 #endif /* UART7 */
265 #if defined(UART8)
266 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
267 #endif /* UART8 */
268 /**
269 * @}
270 */
271
272 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
273 * @{
274 */
275 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
276 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
277 #if defined(TIM8)
278 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
279 #endif /* TIM8 */
280 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
281 #if defined(USART6)
282 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
283 #endif /* USART6 */
284 #if defined(UART9)
285 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
286 #endif /* UART9 */
287 #if defined(UART10)
288 #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
289 #endif /* UART10 */
290 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
291 #if defined(ADC2)
292 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
293 #endif /* ADC2 */
294 #if defined(ADC3)
295 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
296 #endif /* ADC3 */
297 #if defined(SDIO)
298 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
299 #endif /* SDIO */
300 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
301 #if defined(SPI4)
302 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
303 #endif /* SPI4 */
304 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
305 #if defined(RCC_APB2ENR_EXTITEN)
306 #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
307 #endif /* RCC_APB2ENR_EXTITEN */
308 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
309 #if defined(TIM10)
310 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
311 #endif /* TIM10 */
312 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
313 #if defined(SPI5)
314 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
315 #endif /* SPI5 */
316 #if defined(SPI6)
317 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
318 #endif /* SPI6 */
319 #if defined(SAI1)
320 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
321 #endif /* SAI1 */
322 #if defined(SAI2)
323 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
324 #endif /* SAI2 */
325 #if defined(LTDC)
326 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
327 #endif /* LTDC */
328 #if defined(DSI)
329 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
330 #endif /* DSI */
331 #if defined(DFSDM1_Channel0)
332 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
333 #endif /* DFSDM1_Channel0 */
334 #if defined(DFSDM2_Channel0)
335 #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
336 #endif /* DFSDM2_Channel0 */
337 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
338 /**
339 * @}
340 */
341
342 /**
343 * @}
344 */
345
346 /* Exported macro ------------------------------------------------------------*/
347 /* Exported functions --------------------------------------------------------*/
348 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
349 * @{
350 */
351
352 /** @defgroup BUS_LL_EF_AHB1 AHB1
353 * @{
354 */
355
356 /**
357 * @brief Enable AHB1 peripherals clock.
358 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
359 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
360 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
361 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
362 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
363 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
364 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
365 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
366 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
367 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
368 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
369 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
370 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
371 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
372 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
373 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
374 * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
375 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
376 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
377 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
378 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
379 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
380 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
381 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
382 * @param Periphs This parameter can be a combination of the following values:
383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
388 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
389 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
390 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
391 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
392 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
393 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
394 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
395 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
396 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
397 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
398 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
399 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
400 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
401 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
402 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
403 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
404 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
405 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
406 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
407 *
408 * (*) value not defined in all devices.
409 * @retval None
410 */
LL_AHB1_GRP1_EnableClock(uint32_t Periphs)411 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
412 {
413 __IO uint32_t tmpreg;
414 SET_BIT(RCC->AHB1ENR, Periphs);
415 /* Delay after an RCC peripheral clock enabling */
416 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
417 (void)tmpreg;
418 }
419
420 /**
421 * @brief Check if AHB1 peripheral clock is enabled or not
422 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
423 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
424 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
425 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
426 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
427 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
428 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
429 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
430 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
431 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
432 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
433 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
434 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
435 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
436 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
437 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
438 * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
439 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
440 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
441 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
442 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
443 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
444 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
445 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
446 * @param Periphs This parameter can be a combination of the following values:
447 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
448 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
449 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
450 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
451 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
452 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
453 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
454 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
455 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
456 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
457 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
458 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
459 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
460 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
461 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
463 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
464 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
465 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
466 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
467 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
468 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
469 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
470 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
471 *
472 * (*) value not defined in all devices.
473 * @retval State of Periphs (1 or 0).
474 */
LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)475 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
476 {
477 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
478 }
479
480 /**
481 * @brief Disable AHB1 peripherals clock.
482 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
483 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
484 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
485 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
486 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
487 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
488 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
489 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
490 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
491 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
492 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
493 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
494 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
495 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
496 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
497 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
498 * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
499 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
500 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
501 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
502 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
503 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
504 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
505 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
506 * @param Periphs This parameter can be a combination of the following values:
507 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
508 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
509 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
510 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
511 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
512 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
513 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
514 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
515 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
516 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
517 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
518 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
519 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
520 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
521 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
522 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
523 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
524 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
525 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
526 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
527 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
528 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
529 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
530 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
531 *
532 * (*) value not defined in all devices.
533 * @retval None
534 */
LL_AHB1_GRP1_DisableClock(uint32_t Periphs)535 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
536 {
537 CLEAR_BIT(RCC->AHB1ENR, Periphs);
538 }
539
540 /**
541 * @brief Force AHB1 peripherals reset.
542 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
543 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
544 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
545 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
546 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
547 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
548 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
549 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
550 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
551 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
552 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
553 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
554 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
555 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
556 * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
557 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
558 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
559 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
560 * @param Periphs This parameter can be a combination of the following values:
561 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
562 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
563 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
564 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
565 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
566 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
567 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
568 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
569 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
570 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
571 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
572 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
573 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
574 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
575 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
576 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
577 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
578 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
579 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
580 *
581 * (*) value not defined in all devices.
582 * @retval None
583 */
LL_AHB1_GRP1_ForceReset(uint32_t Periphs)584 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
585 {
586 SET_BIT(RCC->AHB1RSTR, Periphs);
587 }
588
589 /**
590 * @brief Release AHB1 peripherals reset.
591 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
592 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
593 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
594 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
595 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
596 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
597 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
598 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
599 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
600 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
601 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
602 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
603 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
604 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
605 * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
606 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
607 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
608 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
609 * @param Periphs This parameter can be a combination of the following values:
610 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
611 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
612 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
613 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
614 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
615 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
616 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
617 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
618 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
619 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
620 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
621 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
622 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
623 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
624 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
625 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
626 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
627 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
628 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
629 *
630 * (*) value not defined in all devices.
631 * @retval None
632 */
LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)633 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
634 {
635 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
636 }
637
638 /**
639 * @brief Enable AHB1 peripheral clocks in low-power mode
640 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
641 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
642 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
643 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
644 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
645 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
646 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
647 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
648 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
649 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
650 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
651 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
652 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
653 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
654 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
655 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
656 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
657 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
658 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
659 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
660 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
661 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
662 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
663 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
664 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
665 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
666 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
667 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
668 * @param Periphs This parameter can be a combination of the following values:
669 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
670 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
671 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
672 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
673 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
674 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
675 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
676 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
677 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
678 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
679 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
680 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
681 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
682 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
683 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
684 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
685 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
686 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
687 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
688 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
689 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
690 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
691 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
692 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
693 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
694 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
695 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
696 *
697 * (*) value not defined in all devices.
698 * @retval None
699 */
LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)700 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
701 {
702 __IO uint32_t tmpreg;
703 SET_BIT(RCC->AHB1LPENR, Periphs);
704 /* Delay after an RCC peripheral clock enabling */
705 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
706 (void)tmpreg;
707 }
708
709 /**
710 * @brief Disable AHB1 peripheral clocks in low-power mode
711 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
712 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
713 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
714 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
715 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
716 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
717 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
718 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
719 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
720 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
721 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
722 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
723 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
724 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
725 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
726 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
727 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
728 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
729 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
730 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
731 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
732 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
733 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
734 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
735 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
736 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
737 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
738 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
739 * @param Periphs This parameter can be a combination of the following values:
740 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
741 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
742 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
743 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
744 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
745 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
746 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
747 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
748 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
749 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
750 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
751 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
752 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
753 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
754 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
755 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
756 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
757 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
758 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
759 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
760 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
761 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
762 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
763 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
764 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
765 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
766 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
767 *
768 * (*) value not defined in all devices.
769 * @retval None
770 */
LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)771 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
772 {
773 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
774 }
775
776 /**
777 * @}
778 */
779
780 #if defined(RCC_AHB2_SUPPORT)
781 /** @defgroup BUS_LL_EF_AHB2 AHB2
782 * @{
783 */
784
785 /**
786 * @brief Enable AHB2 peripherals clock.
787 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
788 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
789 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
790 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
791 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
792 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
793 * @param Periphs This parameter can be a combination of the following values:
794 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
795 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
796 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
797 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
798 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
799 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
800 *
801 * (*) value not defined in all devices.
802 * @retval None
803 */
LL_AHB2_GRP1_EnableClock(uint32_t Periphs)804 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
805 {
806 __IO uint32_t tmpreg;
807 SET_BIT(RCC->AHB2ENR, Periphs);
808 /* Delay after an RCC peripheral clock enabling */
809 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
810 (void)tmpreg;
811 }
812
813 /**
814 * @brief Check if AHB2 peripheral clock is enabled or not
815 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
816 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
817 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
818 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
819 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
820 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
821 * @param Periphs This parameter can be a combination of the following values:
822 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
823 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
824 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
825 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
826 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
827 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
828 *
829 * (*) value not defined in all devices.
830 * @retval State of Periphs (1 or 0).
831 */
LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)832 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
833 {
834 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
835 }
836
837 /**
838 * @brief Disable AHB2 peripherals clock.
839 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
840 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
841 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
842 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
843 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
844 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
845 * @param Periphs This parameter can be a combination of the following values:
846 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
847 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
848 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
849 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
850 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
851 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
852 *
853 * (*) value not defined in all devices.
854 * @retval None
855 */
LL_AHB2_GRP1_DisableClock(uint32_t Periphs)856 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
857 {
858 CLEAR_BIT(RCC->AHB2ENR, Periphs);
859 }
860
861 /**
862 * @brief Force AHB2 peripherals reset.
863 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
864 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
865 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
866 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
867 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
868 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
869 * @param Periphs This parameter can be a combination of the following values:
870 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
871 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
872 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
873 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
874 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
875 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
876 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
877 *
878 * (*) value not defined in all devices.
879 * @retval None
880 */
LL_AHB2_GRP1_ForceReset(uint32_t Periphs)881 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
882 {
883 SET_BIT(RCC->AHB2RSTR, Periphs);
884 }
885
886 /**
887 * @brief Release AHB2 peripherals reset.
888 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
889 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
890 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
891 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
892 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
893 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
894 * @param Periphs This parameter can be a combination of the following values:
895 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
896 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
897 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
898 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
899 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
900 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
901 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
902 *
903 * (*) value not defined in all devices.
904 * @retval None
905 */
LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)906 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
907 {
908 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
909 }
910
911 /**
912 * @brief Enable AHB2 peripheral clocks in low-power mode
913 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
914 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
915 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
916 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
917 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
918 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
919 * @param Periphs This parameter can be a combination of the following values:
920 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
921 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
922 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
923 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
924 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
925 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
926 *
927 * (*) value not defined in all devices.
928 * @retval None
929 */
LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)930 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
931 {
932 __IO uint32_t tmpreg;
933 SET_BIT(RCC->AHB2LPENR, Periphs);
934 /* Delay after an RCC peripheral clock enabling */
935 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
936 (void)tmpreg;
937 }
938
939 /**
940 * @brief Disable AHB2 peripheral clocks in low-power mode
941 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
942 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
943 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
944 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
945 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
946 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
947 * @param Periphs This parameter can be a combination of the following values:
948 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
949 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
950 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
951 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
952 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
953 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
954 *
955 * (*) value not defined in all devices.
956 * @retval None
957 */
LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)958 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
959 {
960 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
961 }
962
963 /**
964 * @}
965 */
966 #endif /* RCC_AHB2_SUPPORT */
967
968 #if defined(RCC_AHB3_SUPPORT)
969 /** @defgroup BUS_LL_EF_AHB3 AHB3
970 * @{
971 */
972
973 /**
974 * @brief Enable AHB3 peripherals clock.
975 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
976 * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
977 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
978 * @param Periphs This parameter can be a combination of the following values:
979 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
980 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
981 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
982 *
983 * (*) value not defined in all devices.
984 * @retval None
985 */
LL_AHB3_GRP1_EnableClock(uint32_t Periphs)986 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
987 {
988 __IO uint32_t tmpreg;
989 SET_BIT(RCC->AHB3ENR, Periphs);
990 /* Delay after an RCC peripheral clock enabling */
991 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
992 (void)tmpreg;
993 }
994
995 /**
996 * @brief Check if AHB3 peripheral clock is enabled or not
997 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
998 * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
999 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
1000 * @param Periphs This parameter can be a combination of the following values:
1001 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1002 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1003 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1004 *
1005 * (*) value not defined in all devices.
1006 * @retval State of Periphs (1 or 0).
1007 */
LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)1008 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1009 {
1010 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
1011 }
1012
1013 /**
1014 * @brief Disable AHB3 peripherals clock.
1015 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
1016 * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
1017 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
1018 * @param Periphs This parameter can be a combination of the following values:
1019 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1020 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1021 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1022 *
1023 * (*) value not defined in all devices.
1024 * @retval None
1025 */
LL_AHB3_GRP1_DisableClock(uint32_t Periphs)1026 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
1027 {
1028 CLEAR_BIT(RCC->AHB3ENR, Periphs);
1029 }
1030
1031 /**
1032 * @brief Force AHB3 peripherals reset.
1033 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
1034 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
1035 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
1036 * @param Periphs This parameter can be a combination of the following values:
1037 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1038 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1039 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1040 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1041 *
1042 * (*) value not defined in all devices.
1043 * @retval None
1044 */
LL_AHB3_GRP1_ForceReset(uint32_t Periphs)1045 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
1046 {
1047 SET_BIT(RCC->AHB3RSTR, Periphs);
1048 }
1049
1050 /**
1051 * @brief Release AHB3 peripherals reset.
1052 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
1053 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
1054 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
1055 * @param Periphs This parameter can be a combination of the following values:
1056 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1057 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1058 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1059 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1060 *
1061 * (*) value not defined in all devices.
1062 * @retval None
1063 */
LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)1064 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
1065 {
1066 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
1067 }
1068
1069 /**
1070 * @brief Enable AHB3 peripheral clocks in low-power mode
1071 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1072 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1073 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
1074 * @param Periphs This parameter can be a combination of the following values:
1075 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1076 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1077 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1078 *
1079 * (*) value not defined in all devices.
1080 * @retval None
1081 */
LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)1082 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
1083 {
1084 __IO uint32_t tmpreg;
1085 SET_BIT(RCC->AHB3LPENR, Periphs);
1086 /* Delay after an RCC peripheral clock enabling */
1087 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
1088 (void)tmpreg;
1089 }
1090
1091 /**
1092 * @brief Disable AHB3 peripheral clocks in low-power mode
1093 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1094 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1095 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
1096 * @param Periphs This parameter can be a combination of the following values:
1097 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1098 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1099 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1100 *
1101 * (*) value not defined in all devices.
1102 * @retval None
1103 */
LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)1104 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
1105 {
1106 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
1107 }
1108
1109 /**
1110 * @}
1111 */
1112 #endif /* RCC_AHB3_SUPPORT */
1113
1114 /** @defgroup BUS_LL_EF_APB1 APB1
1115 * @{
1116 */
1117
1118 /**
1119 * @brief Enable APB1 peripherals clock.
1120 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1121 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1122 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1123 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1124 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1125 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1126 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1127 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1128 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1129 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1130 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1131 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1132 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1133 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1134 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1135 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1136 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1137 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1138 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1139 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1140 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1141 * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
1142 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1143 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1144 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1145 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1146 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1147 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1148 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1149 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1150 * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
1151 * @param Periphs This parameter can be a combination of the following values:
1152 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1153 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1154 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1155 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1156 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1157 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1158 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1159 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1160 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1161 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1162 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1163 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1164 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1165 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1166 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1167 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1168 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1169 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1170 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1171 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1172 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1173 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1174 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1175 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1176 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1177 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1178 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1179 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1180 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1181 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1182 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1183 *
1184 * (*) value not defined in all devices.
1185 * @retval None
1186 */
LL_APB1_GRP1_EnableClock(uint32_t Periphs)1187 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1188 {
1189 __IO uint32_t tmpreg;
1190 SET_BIT(RCC->APB1ENR, Periphs);
1191 /* Delay after an RCC peripheral clock enabling */
1192 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1193 (void)tmpreg;
1194 }
1195
1196 /**
1197 * @brief Check if APB1 peripheral clock is enabled or not
1198 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1199 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1200 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1201 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1202 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1203 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1204 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1205 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1206 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1207 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1208 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1209 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1210 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1211 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1212 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1213 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1214 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1215 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1216 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1217 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1218 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1219 * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
1220 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1221 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1222 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1223 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1224 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1225 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1226 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1227 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1228 * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
1229 * @param Periphs This parameter can be a combination of the following values:
1230 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1231 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1232 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1233 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1234 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1235 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1236 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1237 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1238 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1239 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1240 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1241 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1242 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1243 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1244 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1245 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1246 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1247 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1248 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1249 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1250 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1251 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1252 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1253 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1254 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1255 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1256 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1257 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1258 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1259 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1260 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1261 *
1262 * (*) value not defined in all devices.
1263 * @retval State of Periphs (1 or 0).
1264 */
LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)1265 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1266 {
1267 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1268 }
1269
1270 /**
1271 * @brief Disable APB1 peripherals clock.
1272 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1273 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1274 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1275 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1276 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1277 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1278 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1279 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1280 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1281 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1282 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1283 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1284 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1285 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1286 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1287 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1288 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1289 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1290 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1291 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1292 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1293 * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
1294 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1295 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1296 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1297 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1298 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1299 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1300 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1301 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1302 * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
1303 * @param Periphs This parameter can be a combination of the following values:
1304 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1305 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1306 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1307 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1308 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1309 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1310 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1311 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1312 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1313 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1314 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1315 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1316 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1317 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1318 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1319 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1320 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1321 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1322 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1323 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1324 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1325 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1326 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1327 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1328 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1329 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1330 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1331 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1332 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1333 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1334 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1335 *
1336 * (*) value not defined in all devices.
1337 * @retval None
1338 */
LL_APB1_GRP1_DisableClock(uint32_t Periphs)1339 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1340 {
1341 CLEAR_BIT(RCC->APB1ENR, Periphs);
1342 }
1343
1344 /**
1345 * @brief Force APB1 peripherals reset.
1346 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1347 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1348 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1349 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1350 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1351 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1352 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1353 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1354 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1355 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1356 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1357 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1358 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1359 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1360 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1361 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1362 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1363 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1364 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1365 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1366 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1367 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
1368 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1369 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1370 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1371 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1372 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1373 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1374 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1375 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1376 * @param Periphs This parameter can be a combination of the following values:
1377 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1378 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1379 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1380 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1381 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1382 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1383 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1384 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1385 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1386 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1387 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1388 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1389 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1390 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1391 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1392 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1393 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1394 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1395 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1396 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1397 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1398 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1399 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1400 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1401 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1402 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1403 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1404 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1405 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1406 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1407 *
1408 * (*) value not defined in all devices.
1409 * @retval None
1410 */
LL_APB1_GRP1_ForceReset(uint32_t Periphs)1411 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1412 {
1413 SET_BIT(RCC->APB1RSTR, Periphs);
1414 }
1415
1416 /**
1417 * @brief Release APB1 peripherals reset.
1418 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1419 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1420 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1421 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1422 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1423 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1424 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1425 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1426 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1427 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1428 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1429 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1430 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1431 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1432 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1433 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1434 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1435 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1436 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1437 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1438 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1439 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
1440 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1441 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1442 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1443 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1444 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1445 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1446 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1447 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1448 * @param Periphs This parameter can be a combination of the following values:
1449 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1450 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1451 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1452 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1453 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1454 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1455 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1456 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1457 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1458 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1459 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1460 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1461 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1462 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1463 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1464 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1465 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1466 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1467 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1468 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1469 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1470 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1471 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1472 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1473 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1474 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1475 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1476 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1477 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1478 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1479 *
1480 * (*) value not defined in all devices.
1481 * @retval None
1482 */
LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)1483 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1484 {
1485 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1486 }
1487
1488 /**
1489 * @brief Enable APB1 peripheral clocks in low-power mode
1490 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1491 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1492 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1493 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1494 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1495 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1496 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1497 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1498 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1499 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1500 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1501 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1502 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1503 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1504 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1505 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1506 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1507 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1508 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1509 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1510 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1511 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1512 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1513 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1514 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1515 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1516 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1517 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1518 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1519 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1520 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
1521 * @param Periphs This parameter can be a combination of the following values:
1522 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1523 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1528 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1529 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1530 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1531 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1532 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1533 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1534 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1535 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1536 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1537 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1538 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1539 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1540 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1541 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1542 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1543 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1544 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1545 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1546 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1547 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1548 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1549 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1550 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1551 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1552 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1553 *
1554 * (*) value not defined in all devices.
1555 * @retval None
1556 */
LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)1557 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1558 {
1559 __IO uint32_t tmpreg;
1560 SET_BIT(RCC->APB1LPENR, Periphs);
1561 /* Delay after an RCC peripheral clock enabling */
1562 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1563 (void)tmpreg;
1564 }
1565
1566 /**
1567 * @brief Disable APB1 peripheral clocks in low-power mode
1568 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1569 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1570 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1571 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1572 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1573 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1574 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1575 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1576 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1577 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1578 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1579 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1580 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1581 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1582 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1583 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1584 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1585 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1586 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1587 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1588 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1589 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1590 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1591 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1592 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1593 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1594 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1595 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1596 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1597 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1598 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
1599 * @param Periphs This parameter can be a combination of the following values:
1600 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1601 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1602 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1603 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1604 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1605 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1606 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1607 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1608 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1609 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1610 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1611 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1612 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1613 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1614 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1615 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1616 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1617 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1618 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1619 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1620 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1621 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1622 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1623 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1624 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1625 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1626 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1627 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1628 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1629 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1630 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1631 *
1632 * (*) value not defined in all devices.
1633 * @retval None
1634 */
LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)1635 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1636 {
1637 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1638 }
1639
1640 /**
1641 * @}
1642 */
1643
1644 /** @defgroup BUS_LL_EF_APB2 APB2
1645 * @{
1646 */
1647
1648 /**
1649 * @brief Enable APB2 peripherals clock.
1650 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1651 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1652 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1653 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1654 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
1655 * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
1656 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1657 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1658 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1659 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
1660 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1661 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1662 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1663 * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
1664 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1665 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1666 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1667 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1668 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1669 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1670 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1671 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1672 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1673 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1674 * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
1675 * @param Periphs This parameter can be a combination of the following values:
1676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1677 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1678 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1679 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1680 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1681 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1682 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1683 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1684 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1685 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1686 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1687 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1688 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1689 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1690 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1691 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1692 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1693 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1694 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1695 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1696 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1697 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1698 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1699 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1700 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1701
1702 *
1703 * (*) value not defined in all devices.
1704 * @retval None
1705 */
LL_APB2_GRP1_EnableClock(uint32_t Periphs)1706 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1707 {
1708 __IO uint32_t tmpreg;
1709 SET_BIT(RCC->APB2ENR, Periphs);
1710 /* Delay after an RCC peripheral clock enabling */
1711 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1712 (void)tmpreg;
1713 }
1714
1715 /**
1716 * @brief Check if APB2 peripheral clock is enabled or not
1717 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1718 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1719 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1720 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1721 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
1722 * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
1723 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1724 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1725 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1726 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
1727 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1728 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1729 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1730 * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
1731 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1732 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1733 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1734 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1735 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1736 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1737 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1738 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1739 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1740 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1741 * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
1742 * @param Periphs This parameter can be a combination of the following values:
1743 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1744 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1745 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1746 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1747 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1748 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1749 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1750 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1751 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1752 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1753 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1754 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1755 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1756 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1757 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1758 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1759 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1760 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1761 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1762 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1763 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1764 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1765 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1766 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1767 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1768 *
1769 * (*) value not defined in all devices.
1770 * @retval State of Periphs (1 or 0).
1771 */
LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)1772 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1773 {
1774 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1775 }
1776
1777 /**
1778 * @brief Disable APB2 peripherals clock.
1779 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1780 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1781 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1782 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1783 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
1784 * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
1785 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1786 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1787 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1788 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
1789 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1790 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1791 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1792 * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
1793 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1794 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1795 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1796 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1797 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1798 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1799 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1800 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1801 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1802 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1803 * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
1804 * @param Periphs This parameter can be a combination of the following values:
1805 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1806 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1807 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1808 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1809 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1810 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1811 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1812 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1813 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1814 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1815 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1816 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1817 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1818 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1819 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1820 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1821 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1822 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1823 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1824 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1825 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1826 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1827 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1828 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1829 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1830 *
1831 * (*) value not defined in all devices.
1832 * @retval None
1833 */
LL_APB2_GRP1_DisableClock(uint32_t Periphs)1834 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1835 {
1836 CLEAR_BIT(RCC->APB2ENR, Periphs);
1837 }
1838
1839 /**
1840 * @brief Force APB2 peripherals reset.
1841 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1842 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1843 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1844 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1845 * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
1846 * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
1847 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1848 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
1849 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1850 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1851 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1852 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1853 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1854 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1855 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1856 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1857 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1858 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1859 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1860 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1861 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1862 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
1863 * @param Periphs This parameter can be a combination of the following values:
1864 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1866 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1867 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1868 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1869 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1870 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1871 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1872 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1873 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1874 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1875 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1876 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1877 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1878 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1879 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1880 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1881 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1882 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1883 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1884 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1885 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1886 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1887 *
1888 * (*) value not defined in all devices.
1889 * @retval None
1890 */
LL_APB2_GRP1_ForceReset(uint32_t Periphs)1891 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1892 {
1893 SET_BIT(RCC->APB2RSTR, Periphs);
1894 }
1895
1896 /**
1897 * @brief Release APB2 peripherals reset.
1898 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1899 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1900 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1901 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1902 * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
1903 * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
1904 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1905 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
1906 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1907 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1908 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1909 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1910 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1911 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1912 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1913 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1914 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1915 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1916 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1917 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1918 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1919 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
1920 * @param Periphs This parameter can be a combination of the following values:
1921 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1922 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1923 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1924 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1925 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1926 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1927 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1928 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1929 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1930 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1931 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1932 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1933 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1935 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1936 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1937 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1938 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1939 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1940 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1941 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1942 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1943 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1944 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1945 *
1946 * (*) value not defined in all devices.
1947 * @retval None
1948 */
LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)1949 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1950 {
1951 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1952 }
1953
1954 /**
1955 * @brief Enable APB2 peripheral clocks in low-power mode
1956 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1957 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1958 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1959 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1960 * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1961 * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1962 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1963 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1964 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1965 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
1966 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1967 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1968 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1969 * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
1970 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1971 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1972 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1973 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1974 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1975 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1976 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1977 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1978 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1979 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1980 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1981 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
1982 * @param Periphs This parameter can be a combination of the following values:
1983 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1984 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1985 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1986 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1987 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1988 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1989 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1990 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1991 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1992 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1993 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1994 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1995 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1996 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1997 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1998 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1999 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2000 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2001 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2002 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2003 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2004 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2005 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2006 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2007 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2008 *
2009 * (*) value not defined in all devices.
2010 * @retval None
2011 */
LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)2012 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
2013 {
2014 __IO uint32_t tmpreg;
2015 SET_BIT(RCC->APB2LPENR, Periphs);
2016 /* Delay after an RCC peripheral clock enabling */
2017 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2018 (void)tmpreg;
2019 }
2020
2021 /**
2022 * @brief Disable APB2 peripheral clocks in low-power mode
2023 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2024 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
2025 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2026 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2027 * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2028 * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2029 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2030 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2031 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
2032 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
2033 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2034 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
2035 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
2036 * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
2037 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2038 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2039 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
2040 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
2041 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2042 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2043 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2044 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
2045 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2046 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2047 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2048 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
2049 * @param Periphs This parameter can be a combination of the following values:
2050 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2051 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2052 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2053 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
2054 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2055 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
2056 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
2057 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
2058 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
2059 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
2060 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2061 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2062 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
2063 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
2064 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2065 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
2066 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2067 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2068 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2069 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2070 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2071 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2072 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2073 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2074 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2075 *
2076 * (*) value not defined in all devices.
2077 * @retval None
2078 */
LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)2079 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
2080 {
2081 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2082 }
2083
2084 /**
2085 * @}
2086 */
2087
2088 /**
2089 * @}
2090 */
2091
2092 /**
2093 * @}
2094 */
2095
2096 #endif /* defined(RCC) */
2097
2098 /**
2099 * @}
2100 */
2101
2102 #ifdef __cplusplus
2103 }
2104 #endif
2105
2106 #endif /* __STM32F4xx_LL_BUS_H */
2107
2108 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2109