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1 /*
2  * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3  * Licensed under the Apache License, Version 2.0 (the "License");
4  * you may not use this file except in compliance with the License.
5  * You may obtain a copy of the License at
6  *
7  *     http://www.apache.org/licenses/LICENSE-2.0
8  *
9  * Unless required by applicable law or agreed to in writing, software
10  * distributed under the License is distributed on an "AS IS" BASIS,
11  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12  * See the License for the specific language governing permissions and
13  * limitations under the License.
14  */
15 
16 #ifndef __UART_DRV_H__
17 #define __UART_DRV_H__
18 
19 #include <hi_event.h>
20 #include <hi_config.h>
21 #include <hi_mem.h>
22 #include <hi_mdm.h>
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 #define UART_RD_EVENT        0x1
28 #define UART_WD_EVENT        0x2
29 #define UART_RD_QUIT_EVENT   (1 << 2)
30 #define BUF_CIRCLED          (1 << 0)
31 #define BUF_OVERFLOWED       (1 << 1)
32 #define BUF_EMPTIED          (1 << 2)
33 #define UART_FLG_RD_NONBLOCK 1
34 #define UART_FLG_RD_BLOCK    2
35 #define UART_FLG_WD_NONBLOCK 1
36 #define UART_FLG_WD_BLOCK    2
37 #define UART_TX_INT_BIT      (1 << 5)
38 #define UART_RX_INT_ENABLE   0x50
39 
40 #define GPIO_SEL_UART        0
41 #define GPIO_SEL_GPIO        1
42 
43 #define UART_ERR_PARA_INVALID          1
44 #define UART_ERR_INIT_CIRC_FAILED      2
45 #define UART_ERR_START_FAILED          3
46 #define UART_ERR_IOCTL_FAILED          4
47 #define UART_ERR_PTR_NULL              5
48 #define UART_ERR_OPEN_AGAIN            6
49 #define UART_ERR_NOT_OPENED            7
50 #define UART_ERR_NOT_IDLE              8
51 
52 /* Read Block: */
53 #define UART_RD_BLOCK        1
54 #define UART_RD_NONBLOCK     0
55 
56 /* Write Block: */
57 #define UART_WD_BLOCK        1
58 #define UART_WD_NONBLOCK     0
59 #define UART_TX_USE_DMA      2
60 #define UART_RX_USE_DMA      2
61 #define UART_CFG_SET_ATTR    0x101
62 #define UART_CFG_RD_BLOCK    0x102
63 #define UART_CFG_WD_BLOCK    0x103
64 #define UART_CFG_GET_ATTR    0x104
65 #define UART_CFG_SET_ACT     0x105
66 #define UART_CFG_GET_ACT     0x106
67 #define UART_CFG_GET_BUF_EMPTY    0x107
68 #define HI_UART_LAST_RECORD_BYTE_COUNT 32
69 typedef struct {
70     hi_u32 baud_rate;
71     hi_u8  data_bits;
72     hi_u8  stop_bits;
73     hi_u8  parity;
74     hi_u8  tx_fifo_line;   /**< 0: tx FIFO≤1/8full; 1:tx FIFO≤1/4full; 2:tx FIFO≤1/2full; 3:tx FIFO≤3/4full;
75                                 4:tx FIFO≤7/8full : default: 2 */
76     hi_u8  rx_fifo_line;   /**< 0: rx FIFO≥1/8full; 1:rx FIFO≥1/4full; 2:rx FIFO≥1/2full; 3:rx FIFO≥3/4full;
77                                 4:rx FIFO≥7/8full : default: 1 */
78     hi_u8  flow_fifo_line; /**< 0: rx FIFO≥1/8full; 1:rx FIFO≥1/4full; 2:rx FIFO≥1/2full; 3:rx FIFO≥3/4full;
79                                 4:rx FIFO≥7/8full : default: 3 */
80     hi_u8  flow_ctrl;      /**< 0: disable flow ctrl; 1: enable rts and cts; 2: enable rts only; 3: enable cts only.
81                                 notice: uart0 not support flow ctrl. */
82     hi_u8  pad;            /**< reserved:currently not used. */
83 } uart_attr_t;
84 
85 typedef struct {
86     hi_u16 tx_buffer_size;
87     hi_u16 rx_buffer_size;
88     hi_u8 tx_use_dma;
89     hi_u8 rx_use_dma;
90     hi_u8 tx_block;
91     hi_u8 rx_block;
92 } uart_act_t;
93 
94 typedef struct uart_circ_buf {
95     hi_u32 rp;
96     hi_u32 wp;
97     hi_u32 flags;
98     hi_char *data;
99     hi_u32 size;
100 } uart_circ_buf;
101 
102 typedef enum uart_status {
103     UART_STATE_NOT_OPENED = 0,
104     UART_STATE_USEABLE
105 } uart_status;
106 
107 typedef enum uart_mode {
108     UART_232 = 0
109 } uart_mode;
110 
111 typedef struct uart_driver_data uart_driver_data_t;
112 
113 typedef struct uart_ops {
114     hi_u32(*startup) (uart_driver_data_t *udd);
115     hi_void(*shutdown) (uart_driver_data_t *udd);
116     hi_s32(*start_tx) (uart_driver_data_t *udd, const hi_char *buf, hi_u32 count);
117     hi_u32(*ioctl) (uart_driver_data_t *udd);
118 } uart_ops;
119 
120 typedef hi_s32(*recv_notify) (uart_circ_buf *transfer, const hi_char *buf, hi_u32 count);
121 typedef hi_s32(*send_buf) (uart_circ_buf *transfer, hi_char *buf, hi_u32 count);
122 
123 #ifdef CONFIG_UART_DEBUG_INFO
124 #define uart_set_errno(err) ((udd->uart_stat_info.uart_errno) = (err))
125 #else
126 #define unused_param(p) ((p) = (p))
127 #define uart_set_errno(err)
128 #endif
129 
130 typedef struct {
131     hi_char data[HI_UART_LAST_RECORD_BYTE_COUNT];
132     hi_u32 num;
133 } uart_recv_send_last_data;
134 
135 typedef struct uart_drv_stat_info {
136     hi_u32 uart_errno;
137     hi_u32 recv_irq_cnt;
138     hi_u32 recv_irq_data_cnt;
139     hi_u32 read_circ_cnt;
140     hi_u32 send_irq_cnt;
141     hi_u32 send_irq_data_cnt;
142     hi_u32 write_circ_cnt;
143     hi_u32 recv_irq_err_overrun;
144     hi_u32 recv_irq_err_parity;
145     hi_u32 recv_irq_err_frame;
146     hi_u32 recv_irq_err_break;
147     hi_u32 recv_irq_err_busy;
148     hi_u32 recv_irq_err_emptyfifo_cnt;
149     hi_u32 send_dma_err_cnt;
150     hi_u32 recv_dma_err_cnt;
151     uart_recv_send_last_data recv_last_context;
152     uart_recv_send_last_data send_last_context;
153 } uart_drv_stat_info;
154 
155 struct uart_driver_data {
156 #ifdef CONFIG_UART_DEBUG_INFO
157     uart_drv_stat_info uart_stat_info;
158 #endif
159     hi_char num;
160     hi_bool receive_tx_int;
161     hi_u16 pad;
162     uart_mode type;
163     hi_u32 phys_base;
164     hi_u32 irq_num;
165     uart_circ_buf *rx_transfer;
166     uart_circ_buf *tx_transfer;
167     hi_u32 event_id;
168     hi_u32 count;
169     hi_u32 state;
170     recv_notify rx_recv;
171     send_buf tx_send;
172     uart_ops *ops;
173     hi_bool tx_use_int;
174     uart_attr_t attr;
175     uart_act_t act;
176 };
177 
178 #ifdef UART_DEBUG_PRINT
179 #define uart_error(msg...) do { \
180         dprintf("\n"); \
181         dprintf("<uart,err>:%s,%d: ", __func__, __LINE__); \
182         dprintf(msg); \
183         dprintf("\n"); \
184     }while (0)
185 #else
186 #define uart_error(msg...)
187 #endif
188 
189 hi_void uart_tx_interrupt_enable(const uart_driver_data_t *udd);
190 hi_u32 uart_circ_buf_empty(const uart_circ_buf *transfer);
191 hi_u32 uart_init_circ_buf(uart_driver_data_t *udd, hi_u32 rx_fifo_size, hi_u32 tx_fifo_size);
192 hi_void uart_deinit_circ_buf(uart_driver_data_t *udd);
193 hi_s32 uart_read_circ_buf(uart_circ_buf *transfer, hi_char *buf, hi_u32 count);
194 hi_s32 uart_write_circ_buf(uart_circ_buf *transfer, const hi_char *buf, hi_u32 count);
195 hi_void uart_set_tx_mode(uart_driver_data_t *udd);
196 hi_u32 uart_buf_empty(const uart_driver_data_t *udd);
197 hi_void uart_tx_interrupt_disable(uart_driver_data_t *udd);
198 hi_void uart_tx_interrupt_clear(const uart_driver_data_t *udd);
199 hi_void uart_tf_interrupt_disable(uart_driver_data_t *udd);
200 hi_void uart_rx_interrupt_disable(const uart_driver_data_t *udd);
201 #ifdef __cplusplus
202 }
203 #endif
204 #endif /* __UART_DRV_H__ */
205