1 /* 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3 * processor CORE configuration 4 * 5 * See <xtensa/config/core.h>, which includes this file, for more details. 6 */ 7 8 /* Xtensa processor core configuration information. 9 10 Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. 11 12 Permission is hereby granted, free of charge, to any person obtaining 13 a copy of this software and associated documentation files (the 14 "Software"), to deal in the Software without restriction, including 15 without limitation the rights to use, copy, modify, merge, publish, 16 distribute, sublicense, and/or sell copies of the Software, and to 17 permit persons to whom the Software is furnished to do so, subject to 18 the following conditions: 19 20 The above copyright notice and this permission notice shall be included 21 in all copies or substantial portions of the Software. 22 23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30 31 #ifndef _XTENSA_CORE_CONFIGURATION_H 32 #define _XTENSA_CORE_CONFIGURATION_H 33 34 35 /**************************************************************************** 36 Parameters Useful for Any Code, USER or PRIVILEGED 37 ****************************************************************************/ 38 39 /* 40 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 41 * configured, and a value of 0 otherwise. These macros are always defined. 42 */ 43 44 45 /*---------------------------------------------------------------------- 46 ISA 47 ----------------------------------------------------------------------*/ 48 49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 50 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 51 #define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ 52 #define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ 53 #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 54 #define XCHAL_HAVE_DEBUG 1 /* debug option */ 55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 57 #define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ 58 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 59 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 60 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 61 #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ 62 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 63 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 64 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 65 #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ 66 #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 67 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 68 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 69 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 70 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 71 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 72 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 73 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 74 #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 75 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 76 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 77 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 78 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 79 #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 80 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 81 #define XCHAL_NUM_CONTEXTS 1 /* */ 82 #define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ 83 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 84 #define XCHAL_HAVE_PRID 1 /* processor ID register */ 85 #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 86 #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 87 #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 88 #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 90 #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 91 #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 92 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 93 #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 94 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 95 #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 96 #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 97 98 #define XCHAL_HAVE_FUSION 0 /* Fusion*/ 99 #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ 100 #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ 101 #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ 102 #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ 103 #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ 104 #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ 105 #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ 106 #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ 107 #define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ 108 #define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ 109 #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 110 #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ 111 #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ 112 #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ 113 #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ 114 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 115 #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 116 #define XCHAL_HAVE_HIFI_MINI 0 117 118 119 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ 120 #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ 121 #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ 122 #define XCHAL_HAVE_FP 1 /* single prec floating point */ 123 #define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ 124 #define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ 125 #define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ 126 #define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ 127 #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 128 #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 129 #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 130 #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 131 #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 132 #define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */ 133 #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ 134 135 #define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */ 136 #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ 137 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 138 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 139 #define XCHAL_HAVE_PDX4 0 /* PDX4 */ 140 #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 141 #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ 142 #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 143 #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 144 #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 145 #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 146 #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 147 #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 148 #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 149 #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 150 #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 151 #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 152 #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 153 #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 154 #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ 155 #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ 156 157 158 /*---------------------------------------------------------------------- 159 MISC 160 ----------------------------------------------------------------------*/ 161 162 #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 163 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ 164 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 165 #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 166 #define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay 167 (1 = 5-stage, 2 = 7-stage) */ 168 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ 169 #define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ 170 /* In T1050, applies to selected core load and store instructions (see ISA): */ 171 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ 172 #define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/ 173 #define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ 174 #define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/ 175 176 #define XCHAL_SW_VERSION 1100003 /* sw version of this header */ 177 178 #define XCHAL_CORE_ID "esp32_v3_49_prod" /* alphanum core name 179 (CoreID) set in the Xtensa 180 Processor Generator */ 181 182 #define XCHAL_BUILD_UNIQUE_ID 0x0005FE96 /* 22-bit sw build ID */ 183 184 /* 185 * These definitions describe the hardware targeted by this software. 186 */ 187 #define XCHAL_HW_CONFIGID0 0xC2BCFFFE /* ConfigID hi 32 bits*/ 188 #define XCHAL_HW_CONFIGID1 0x1CC5FE96 /* ConfigID lo 32 bits*/ 189 #define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */ 190 #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ 191 #define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */ 192 #define XCHAL_HW_VERSION 260003 /* major*100+minor */ 193 #define XCHAL_HW_REL_LX6 1 194 #define XCHAL_HW_REL_LX6_0 1 195 #define XCHAL_HW_REL_LX6_0_3 1 196 #define XCHAL_HW_CONFIGID_RELIABLE 1 197 /* If software targets a *range* of hardware versions, these are the bounds: */ 198 #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ 199 #define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */ 200 #define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ 201 #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ 202 #define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */ 203 #define XCHAL_HW_MAX_VERSION 260003 /* latest targeted hw */ 204 205 206 /*---------------------------------------------------------------------- 207 CACHE 208 ----------------------------------------------------------------------*/ 209 210 #define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ 211 #define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ 212 #define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ 213 #define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ 214 215 #define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ 216 #define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ 217 218 #define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ 219 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 220 221 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 222 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 223 #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ 224 #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ 225 #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ 226 #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ 227 #define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ 228 #define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ 229 #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ 230 #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ 231 232 233 234 235 /**************************************************************************** 236 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 237 ****************************************************************************/ 238 239 240 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 241 242 /*---------------------------------------------------------------------- 243 CACHE 244 ----------------------------------------------------------------------*/ 245 246 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 247 #define XCHAL_HAVE_AXI 0 /* AXI bus */ 248 249 #define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ 250 #define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */ 251 252 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 253 254 /* Number of cache sets in log2(lines per way): */ 255 #define XCHAL_ICACHE_SETWIDTH 0 256 #define XCHAL_DCACHE_SETWIDTH 0 257 258 /* Cache set associativity (number of ways): */ 259 #define XCHAL_ICACHE_WAYS 1 260 #define XCHAL_DCACHE_WAYS 1 261 262 /* Cache features: */ 263 #define XCHAL_ICACHE_LINE_LOCKABLE 0 264 #define XCHAL_DCACHE_LINE_LOCKABLE 0 265 #define XCHAL_ICACHE_ECC_PARITY 0 266 #define XCHAL_DCACHE_ECC_PARITY 0 267 268 /* Cache access size in bytes (affects operation of SICW instruction): */ 269 #define XCHAL_ICACHE_ACCESS_SIZE 1 270 #define XCHAL_DCACHE_ACCESS_SIZE 1 271 272 #define XCHAL_DCACHE_BANKS 0 /* number of banks */ 273 274 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 275 #define XCHAL_CA_BITS 4 276 277 278 /*---------------------------------------------------------------------- 279 INTERNAL I/D RAM/ROMs and XLMI 280 ----------------------------------------------------------------------*/ 281 282 #define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ 283 #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ 284 #define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ 285 #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ 286 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 287 #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ 288 289 /* Instruction ROM 0: */ 290 #define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ 291 #define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ 292 #define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ 293 #define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 294 295 /* Instruction RAM 0: */ 296 #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ 297 #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ 298 #define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ 299 #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 300 301 /* Instruction RAM 1: */ 302 #define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ 303 #define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ 304 #define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ 305 #define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ 306 307 /* Data ROM 0: */ 308 #define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ 309 #define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ 310 #define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ 311 #define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 312 #define XCHAL_DATAROM0_BANKS 1 /* number of banks */ 313 314 /* Data RAM 0: */ 315 #define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ 316 #define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ 317 #define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ 318 #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 319 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ 320 321 /* Data RAM 1: */ 322 #define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ 323 #define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ 324 #define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ 325 #define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ 326 #define XCHAL_DATARAM1_BANKS 1 /* number of banks */ 327 328 /* XLMI Port 0: */ 329 #define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */ 330 #define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */ 331 #define XCHAL_XLMI0_SIZE 524288 /* size in bytes */ 332 #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 333 334 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 335 336 337 /*---------------------------------------------------------------------- 338 INTERRUPTS and TIMERS 339 ----------------------------------------------------------------------*/ 340 341 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 342 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 343 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 344 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 345 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 346 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ 347 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 348 #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ 349 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 350 (not including level zero) */ 351 #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 352 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 353 354 /* Masks of interrupts at each interrupt level: */ 355 #define XCHAL_INTLEVEL1_MASK 0x000637FF 356 #define XCHAL_INTLEVEL2_MASK 0x00380000 357 #define XCHAL_INTLEVEL3_MASK 0x28C08800 358 #define XCHAL_INTLEVEL4_MASK 0x53000000 359 #define XCHAL_INTLEVEL5_MASK 0x84010000 360 #define XCHAL_INTLEVEL6_MASK 0x00000000 361 #define XCHAL_INTLEVEL7_MASK 0x00004000 362 363 /* Masks of interrupts at each range 1..n of interrupt levels: */ 364 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF 365 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF 366 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF 367 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF 368 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF 369 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF 370 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF 371 372 /* Level of each interrupt: */ 373 #define XCHAL_INT0_LEVEL 1 374 #define XCHAL_INT1_LEVEL 1 375 #define XCHAL_INT2_LEVEL 1 376 #define XCHAL_INT3_LEVEL 1 377 #define XCHAL_INT4_LEVEL 1 378 #define XCHAL_INT5_LEVEL 1 379 #define XCHAL_INT6_LEVEL 1 380 #define XCHAL_INT7_LEVEL 1 381 #define XCHAL_INT8_LEVEL 1 382 #define XCHAL_INT9_LEVEL 1 383 #define XCHAL_INT10_LEVEL 1 384 #define XCHAL_INT11_LEVEL 3 385 #define XCHAL_INT12_LEVEL 1 386 #define XCHAL_INT13_LEVEL 1 387 #define XCHAL_INT14_LEVEL 7 388 #define XCHAL_INT15_LEVEL 3 389 #define XCHAL_INT16_LEVEL 5 390 #define XCHAL_INT17_LEVEL 1 391 #define XCHAL_INT18_LEVEL 1 392 #define XCHAL_INT19_LEVEL 2 393 #define XCHAL_INT20_LEVEL 2 394 #define XCHAL_INT21_LEVEL 2 395 #define XCHAL_INT22_LEVEL 3 396 #define XCHAL_INT23_LEVEL 3 397 #define XCHAL_INT24_LEVEL 4 398 #define XCHAL_INT25_LEVEL 4 399 #define XCHAL_INT26_LEVEL 5 400 #define XCHAL_INT27_LEVEL 3 401 #define XCHAL_INT28_LEVEL 4 402 #define XCHAL_INT29_LEVEL 3 403 #define XCHAL_INT30_LEVEL 4 404 #define XCHAL_INT31_LEVEL 5 405 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 406 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 407 #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 408 EXCSAVE/EPS/EPC_n, RFI n) */ 409 410 /* Type of each interrupt: */ 411 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 412 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 413 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 414 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 415 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 416 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 417 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 418 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 419 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 420 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 421 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE 422 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING 423 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 424 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 425 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 426 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER 427 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER 428 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 429 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 430 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 431 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 432 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 433 #define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE 434 #define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 435 #define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 436 #define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 437 #define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 438 #define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 439 #define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE 440 #define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE 441 #define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE 442 #define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 443 444 /* Masks of interrupts for each type of interrupt: */ 445 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 446 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 447 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 448 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F 449 #define XCHAL_INTTYPE_MASK_TIMER 0x00018040 450 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 451 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 452 #define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 453 454 /* Interrupt numbers assigned to specific interrupt sources: */ 455 #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 456 #define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ 457 #define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ 458 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 459 #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 460 #define XCHAL_PROFILING_INTERRUPT 11 /* profiling interrupt */ 461 462 /* Interrupt numbers for levels at which only one interrupt is configured: */ 463 #define XCHAL_INTLEVEL7_NUM 14 464 /* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ 465 466 467 /* 468 * External interrupt mapping. 469 * These macros describe how Xtensa processor interrupt numbers 470 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 471 * map to external BInterrupt<n> pins, for those interrupts 472 * configured as external (level-triggered, edge-triggered, or NMI). 473 * See the Xtensa processor databook for more details. 474 */ 475 476 /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 477 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 478 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 479 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 480 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 481 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 482 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 483 #define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ 484 #define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ 485 #define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ 486 #define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ 487 #define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ 488 #define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ 489 #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 490 #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 491 #define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ 492 #define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ 493 #define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ 494 #define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ 495 #define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ 496 #define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ 497 #define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ 498 #define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ 499 #define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ 500 #define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ 501 #define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ 502 #define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ 503 /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 504 #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 505 #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 506 #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 507 #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 508 #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 509 #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 510 #define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ 511 #define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ 512 #define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ 513 #define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ 514 #define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ 515 #define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ 516 #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ 517 #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ 518 #define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ 519 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ 520 #define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ 521 #define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ 522 #define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ 523 #define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ 524 #define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ 525 #define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ 526 #define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ 527 #define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ 528 #define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ 529 #define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ 530 531 532 /*---------------------------------------------------------------------- 533 EXCEPTIONS and VECTORS 534 ----------------------------------------------------------------------*/ 535 536 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 537 number: 1 == XEA1 (old) 538 2 == XEA2 (new) 539 0 == XEAX (extern) or TX */ 540 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 541 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 542 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 543 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 544 #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 545 #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 546 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 547 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 548 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 549 #define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ 550 #define XCHAL_VECBASE_RESET_PADDR 0x40000000 551 #define XCHAL_RESET_VECBASE_OVERLAP 0 552 553 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 554 #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 555 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 556 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 557 #define XCHAL_RESET_VECTOR_VADDR 0x40000400 558 #define XCHAL_RESET_VECTOR_PADDR 0x40000400 559 #define XCHAL_USER_VECOFS 0x00000340 560 #define XCHAL_USER_VECTOR_VADDR 0x40000340 561 #define XCHAL_USER_VECTOR_PADDR 0x40000340 562 #define XCHAL_KERNEL_VECOFS 0x00000300 563 #define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 564 #define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 565 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 566 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 567 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 568 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 569 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 570 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 571 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 572 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 573 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 574 #define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 575 #define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 576 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 577 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 578 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 579 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 580 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 581 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 582 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 583 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 584 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 585 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 586 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 587 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 588 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 589 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 590 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 591 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 592 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 593 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 594 #define XCHAL_NMI_VECOFS 0x000002C0 595 #define XCHAL_NMI_VECTOR_VADDR 0x400002C0 596 #define XCHAL_NMI_VECTOR_PADDR 0x400002C0 597 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 598 #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 599 #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 600 601 602 /*---------------------------------------------------------------------- 603 DEBUG MODULE 604 ----------------------------------------------------------------------*/ 605 606 /* Misc */ 607 #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 608 #define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ 609 #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 610 611 /* On-Chip Debug (OCD) */ 612 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 613 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 614 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 615 #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 616 #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 617 618 /* TRAX (in core) */ 619 #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 620 #define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ 621 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ 622 #define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ 623 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 624 625 /* Perf counters */ 626 #define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ 627 628 629 /*---------------------------------------------------------------------- 630 MMU 631 ----------------------------------------------------------------------*/ 632 633 /* See core-matmap.h header file for more details. */ 634 635 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 636 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 637 #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ 638 #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ 639 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 640 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ 641 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 642 #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table 643 [autorefill] and protection) 644 usable for an MMU-based OS */ 645 /* If none of the above last 4 are set, it's a custom TLB configuration. */ 646 647 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ 648 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ 649 #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ 650 651 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 652 653 654 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 655