1 /* 2 * Copyright (C) 2021–2022 Beijing OSWare Technology Co., Ltd 3 * This file contains confidential and proprietary information of 4 * OSWare Technology Co., Ltd 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef IMX8MM_PLATFORM_H 20 #define IMX8MM_PLATFORM_H 21 22 #include <linux/platform_device.h> 23 #include <linux/dmaengine.h> 24 #include "audio_core.h" 25 #include "sai_driver.h" 26 #include "dma_driver.h" 27 28 #define AIAO_BUFF_OFFSET (128) 29 #define AIAO_BUFF_POINT (320) 30 #define AIAO_BUFF_TRANS (16 * 1024) 31 #define AIAO_BUFF_SIZE (128 * 1024) 32 #define RENDER_TRAF_BUF_SIZE (1024) 33 #define CAPTURE_TRAF_BUF_SIZE (1024 * 16) 34 35 #define AUDIO_BUFF_MIN (128) 36 #define AUDIO_RECORD_MIN (1024 * 16) 37 38 #define MAX_PERIOD_SIZE (1024 * 16) 39 #define MIN_PERIOD_COUNT (8) 40 #define MAX_PERIOD_COUNT (32) 41 #define MAX_AIAO_BUFF_SIZE (128 * 1024) 42 #define MIN_AIAO_BUFF_SIZE (16 * 1024) 43 #define MMAP_MAX_FRAME_SIZE (4096 * 2 * 3) 44 #define AUDIO_CACHE_ALIGN_SIZE (64) 45 #define DELAY_TIME (5) 46 #define LOOP_COUNT (100) 47 48 #define TRIGGER_TX (0) 49 #define TRIGGER_RX (1) 50 #define TRIGGER_START (0) 51 #define TRIGGER_STOP (1) 52 53 struct PrivPlatformData { 54 struct platform_device *pdev; 55 const char *sai_name; 56 struct fsl_sai sai; 57 dma_cookie_t cookie_tx; 58 dma_cookie_t cookie_rx; 59 struct dma_chan *dma_chan_rx; 60 struct dma_chan *dma_chan_tx; 61 dma_addr_t dma_addr_src; 62 dma_addr_t dma_addr_dst; 63 u32 dma_maxburst_rx; 64 u32 dma_maxburst_tx; 65 struct dma_async_tx_descriptor *rx_desc; 66 struct dma_async_tx_descriptor *tx_desc; 67 unsigned int rx_dma_pos; 68 unsigned int tx_dma_pos; 69 unsigned int rx_read_pos; 70 unsigned int tx_write_pos; 71 }; 72 73 #endif 74