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Searched refs:BIT0 (Results 1 – 25 of 82) sorted by relevance

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/device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/include/
DHal8821APwrSeq.h56 …PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b…
61 …K, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB…
63 …{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0
64 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
67 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling unti…
68 …_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},/**/ \
69 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x…
75 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR …
86 …{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0
88 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON…
[all …]
Drtw_qos.h20 #define DRV_CFG_UAPSD_VO BIT0
25 #define WMM_IE_UAPSD_VO BIT0
30 #define WMM_TID0 BIT0
Dpci_osintf.h31 #define PCI_BC_CLK_REQ BIT0
Drtw_sreset.h50 #define USB_VEN_REQ_CMD_FAIL BIT0
Dhal_com.h276 #define DUMP_DRV_RX_COUNTER BIT0
287 #define BAND_CAP_2G BIT0
292 #define BW_CAP_5M BIT0
301 #define PROTO_CAP_11B BIT0
307 #define WL_FUNC_P2P BIT0
Ddrv_types.h861 #define SEC_CAP_CHK_BMC BIT0
865 #define MACID_DROP BIT0
868 #define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0
1011 #define TXPWR_LMT_REF_VHT_FROM_HT BIT0
1014 #define TXPWR_LMT_HAS_CCK_1T BIT0
1034 #define COUNTRY_IE_SLAVE_EN_ROLE_STA BIT0 /* pure STA mode */
1196 #define WOW_CAP_TKIP_OL BIT0
2079 #define DF_TX_BIT BIT0 /*write_port_cancel*/
Drtw_vht.h21 #define LDPC_VHT_ENABLE_RX BIT0
26 #define STBC_VHT_ENABLE_RX BIT0
Drtw_ht.h80 #define LDPC_HT_ENABLE_RX BIT0
85 #define STBC_HT_ENABLE_RX BIT0
Dhal_phy.h47 #define ANT_DETECT_BY_SINGLE_TONE BIT0
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/sdio/
Dsdio_device.h85 #define AHBSOFT_RST_INT BIT0
99 #define INT_FRM_SOFT_RESET BIT0
104 #define FN1_WR_OVER BIT0
120 #define UHS_SUPPORT BIT0
161 #define SDIO_ADMA_VALID BIT0
167 #define SDIO_ADMA_PARAM_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
/device/soc/esp/esp32/components/esp_rom/include/esp32/rom/
Drtc.h78 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
103 EXT_EVENT0_TRIG = BIT0,
133 WAKEUP_INT = BIT0,
Dgpio.h69 … ((gpio_no < 32) ? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))…
Duart.h40 #define UART_RCV_INTEN BIT0
56 #define UART_RCV_DATA_RDY_FLAG BIT0
/device/soc/chipsea/cst85/liteos_m/sdk/modules/btdm/ble/ble_dbg/
Dcsble_dbg.h33 #define CSBLE_HCI_VAL BIT0
44 #define CSBLE_TX_ACL_AREA BIT0
/device/soc/esp/esp32/components/bt/host/bluedroid/external/sbc/decoder/include/
Doi_stddefs.h184 #ifndef BIT0
186 #define BIT0 0x00000001 /**< preprocessor alias for 32-bit value with bit 0 set, used to specify… macro
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/hmac/
Dhmac_rx_filter.c186 hi_u32 def_value = (BIT0 << 21); /* 默认开启FCS ERROR过滤 21: 左移21位 */ in hmac_get_single_vap_rx_filter()
218 return def_value | BIT0; /* 混杂模式需要置BIT0 和FCS ERROR */ in hmac_get_single_vap_rx_filter()
335 rx_filter_val |= (BIT0); in hmac_send_rx_filter_event()
Dhmac_uapsd.c175 if (BIT0 == (puc_mac_hdr[idx + HMAC_UAPSD_WME_LEN] & BIT0)) { in hmac_uapsd_update_user_para()
Dhmac_11i.h38 #define DMAC_WPA_802_11I BIT0 /* 安全加密: bss_info中记录AP能力标识,WPA or WPA2 */
/device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/common/
Dmac_user.c112 g_us_user_res_map |= (hi_u16)(BIT0 << user_idx); in mac_user_alloc_user_res()
168 g_us_user_res_map &= (~((hi_u16)BIT0 << idx)); // ~操作符表达式中所有变量都是无符号数,误报告警,lin_t e502告警屏蔽 in mac_user_free_user_res()
569 return (g_us_user_res_map & ((hi_u16)BIT0 << idx)) ? HI_TRUE : HI_FALSE; in mac_user_is_user_valid()
Dmac_regdomain.h134 MAC_RC_DFS = BIT0,
Dmac_ie.c329 ht_hdl->imbf_receive_cap = (tmp_txbf_elem & BIT0); in mac_ie_txbf_set_ht_hdl()
376 ht_hdl->ht_capinfo.ldpc_coding_cap = (*pus_ht_cap_info & BIT0); in mac_ie_proc_ht_sta()
/device/soc/esp/esp32/components/esp_common/include/
Desp_bit_defs.h49 #define BIT0 0x00000001 macro
/device/soc/esp/esp32/components/soc/esp32/include/soc/
Dboot_mode.h101 #define SEL_SDIO_BOOT BIT0
/device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/core/
Drtw_chplan.h71 #define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */
183 #define CHPLAN_PROTO_EN_AC BIT0
/device/soc/chipsea/cst85/liteos_m/sdk/modules/common/api/
Dwb_co_int.h56 #define BIT0 ((uint32_t)(1ul << 0)) macro

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