| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/sdio/ |
| D | sdio_device.h | 90 #define FN0_WR_TRN_OVER BIT5
109 #define FN1_ACK_TO_ARM BIT5
165 #define SDIO_ADMA_TRAN BIT5
166 #define SDIO_ADMA_LINK (BIT5 | BIT4)
167 #define SDIO_ADMA_PARAM_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
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| /device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/include/ |
| D | Hal8821APwrSeq.h | 59 …K, PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b…
70 …R_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5 | BIT4), (BIT5 | BIT4)},/*…
91 …PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b…
166 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK …
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| D | rtw_qos.h | 35 #define WMM_TID5 BIT5
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| D | rtw_sreset.h | 55 #define WIFI_RX_HANG BIT5
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| D | hal_com_phycfg.h | 325 #define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5
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| D | rtw_mlme_ext.h | 187 SS_BACKOP_TX_RESUME = BIT5,
355 RTW_CHF_NO_HT40L = BIT5,
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| D | hal_com.h | 297 #define BW_CAP_160M BIT5
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| /device/soc/esp/esp32/components/esp_common/include/ |
| D | esp_bit_defs.h | 44 #define BIT5 0x00000020 macro
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| /device/soc/chipsea/cst85/liteos_m/sdk/modules/common/api/ |
| D | wb_co_int.h | 51 #define BIT5 ((uint32_t)(1ul << 5)) macro
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| /device/soc/esp/esp32/components/esp_rom/include/esp32/rom/ |
| D | rtc.h | 108 MAC_TRIG = BIT5,
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| D | uart.h | 61 #define UART_TRX_FIFO_EMPTY_FLAG BIT5
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| D | spi_flash.h | 124 #define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2)
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| /device/soc/chipsea/cst85/liteos_m/sdk/modules/btdm/ble/ble_dbg/ |
| D | csble_dbg.h | 38 #define CSBLE_SMP_VAL BIT5
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| /device/soc/esp/esp32/components/bt/host/bluedroid/external/sbc/decoder/include/ |
| D | oi_stddefs.h | 191 #define BIT5 0x00000020 /**< preprocessor alias for 32-bit value with bit 5 set, used to specify… macro
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| /device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/common/ |
| D | mac_ie.c | 334 ht_hdl->imbf_cap = ((tmp_txbf_elem & BIT5) >> 5); /* 右移5 bit获取imbf_cap */ in mac_ie_txbf_set_ht_hdl()
385 …ht_hdl->ht_capinfo.short_gi_20mhz = ((*pus_ht_cap_info & BIT5) >> 5); /* 提取AP支持20MHz Short-GI情况,右移… in mac_ie_proc_ht_sta()
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| /device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/frw/ |
| D | frw_event.h | 42 #define HI_EVENT_SLEEP_REQUEST_ACK BIT5
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| /device/soc/esp/esp32/components/bt/host/bluedroid/external/sbc/decoder/srce/ |
| D | decoder-private.c | 140 frame->blocks = (d1 & (BIT5 | BIT4)) >> 4; in OI_SBC_ReadHeader()
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| D | decoder-sbc.c | 393 blocks = block_values[(blocks & (BIT5 | BIT4)) >> 4]; in OI_CODEC_SBC_FrameCount()
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| /device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/core/ |
| D | rtw_chplan.h | 76 #define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */
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| /device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/mac/hmac/ |
| D | hmac_wapi.c | 110 puc_mic[0] &= ~(BIT4 | BIT5 | BIT6); /* sub type */ in hmac_wapi_calc_mic_data()
111 puc_mic[1] &= ~(BIT3 | BIT4 | BIT5); /* retry, pwr Mgmt, more data */ in hmac_wapi_calc_mic_data()
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| D | hmac_vap.c | 601 ht_hdl->ht_capinfo.short_gi_20mhz = ((tmp_info_elem & BIT5) >> 5); in hmac_search_ht_cap_ie_ap()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/include/ |
| D | hi_types_base.h | 452 #define BIT5 ((hi_u32)(1 << 5)) macro
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| /device/soc/hisilicon/common/platform/wifi/hi3881v100/driver/include/ |
| D | hi_types_base.h | 453 #define BIT5 ((hi_u32)(1 << 5)) macro
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| /device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/hal/rtl8822c/ |
| D | rtl8822c_ops.c | 642 u8 extTypeLNA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT5 | BIT4)) >> 4; in Hal_ReadAmplifierType()
644 u8 extTypeLNA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT5 | BIT4)) >> 4; in Hal_ReadAmplifierType()
649 if ((hal->PAType_2G & (BIT5 | BIT4)) == (BIT5 | BIT4)) in Hal_ReadAmplifierType()
2061 rtw_write8(adapter, REG_CR_EXT, (rtw_read8(adapter, REG_CR_EXT)& (~BIT5)) | BIT4); in hw_var_vendor_wow_mode()
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| /device/board/unionman/unionpi_tiger/kernel/drivers/rtl88x2cs/hal/phydm/ |
| D | phydm_adc_sampling.c | 93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
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