1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef CTRL_H 17 #define CTRL_H 18 19 #include "eth_mac.h" 20 #include "osal.h" 21 22 #ifdef __cplusplus 23 #if __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 #endif /* __cplusplus */ 27 28 #define GLB_HOSTMAC_L32 0x1300 29 #define BITS_HOSTMAC_L32 MK_BITS(0, 32) 30 #define GLB_HOSTMAC_H16 0x1304 31 #define BITS_HOSTMAC_H16 MK_BITS(0, 16) 32 33 #define GLB_SOFT_RESET 0x1308 34 #define BITS_ETH_SOFT_RESET_ALL MK_BITS(0, 1) 35 #define BITS_ETH_SOFT_RESET_UP MK_BITS(2, 1) 36 #define BITS_ETH_SOFT_RESET_DOWN MK_BITS(3, 1) 37 38 #define GLB_FWCTRL 0x1310 39 #define BITS_VLAN_ENABLE MK_BITS(0, 1) 40 #define BITS_FW2CPU_ENA_U MK_BITS(5, 1) 41 #define BITS_FW2CPU_ENA_UP MK_BITS(5, 1) 42 #define BITS_FW2CPU_ENA_D MK_BITS(9, 1) 43 #define BITS_FW2CPU_ENA_DOWN MK_BITS(9, 1) 44 #define BITS_FWALL2CPU_U MK_BITS(7, 1) 45 #define BITS_FWALL2CPU_UP MK_BITS(7, 1) 46 #define BITS_FWALL2CPU_D MK_BITS(11, 1) 47 #define BITS_FWALL2CPU_DOWN MK_BITS(11, 1) 48 #define BITS_FW2OTHPORT_ENA_U MK_BITS(4, 1) 49 #define BITS_FW2OTHPORT_ENA_D MK_BITS(8, 1) 50 #define BITS_FW2OTHPORT_FORCE_U MK_BITS(6, 1) 51 #define BITS_FW2OTHPORT_FORCE_D MK_BITS(10, 1) 52 53 #define GLB_MACTCTRL 0x1314 54 #define BITS_MACT_ENA_U MK_BITS(7, 1) 55 #define BITS_MACT_ENA_D MK_BITS(15, 1) 56 #define BITS_BROAD2CPU_U MK_BITS(5, 1) 57 #define BITS_BROAD2CPU_UP MK_BITS(5, 1) 58 #define BITS_BROAD2CPU_D MK_BITS(13, 1) 59 #define BITS_BROAD2CPU_DOWN MK_BITS(13, 1) 60 #define BITS_BROAD2OTHPORT_U MK_BITS(4, 1) 61 #define BITS_BROAD2OTHPORT_D MK_BITS(12, 1) 62 #define BITS_MULTI2CPU_U MK_BITS(3, 1) 63 #define BITS_MULTI2CPU_D MK_BITS(11, 1) 64 #define BITS_MULTI2OTHPORT_U MK_BITS(2, 1) 65 #define BITS_MULTI2OTHPORT_D MK_BITS(10, 1) 66 #define BITS_UNI2CPU_U MK_BITS(1, 1) 67 #define BITS_UNI2CPU_D MK_BITS(9, 1) 68 #define BITS_UNI2OTHPORT_U MK_BITS(0, 1) 69 #define BITS_UNI2OTHPORT_D MK_BITS(8, 1) 70 71 /* ENDIAN */ 72 #define GLB_ENDIAN_MOD 0x1318 73 #define BITS_ENDIAN MK_BITS(0, 2) 74 #define HIETH_BIG_ENDIAN 0 75 #define HIETH_LITTLE_ENDIAN 3 76 77 /* IRQs */ 78 #define GLB_RO_IRQ_STAT 0x1330 79 #define GLB_RW_IRQ_ENA 0x1334 80 #define GLB_RW_IRQ_RAW 0x1338 81 82 /* IRQs mask bits */ 83 #define BITS_IRQS_U MK_BITS(0, 8) 84 #define BITS_VLAN_IRQS MK_BITS(11, 1) 85 #define BITS_MDIO_IRQS MK_BITS(13, 2) 86 #define BITS_IRQS_ENA_D MK_BITS(17, 1) 87 #define BITS_IRQS_ENA_U MK_BITS(18, 1) 88 #define BITS_IRQS_ENA_ALLPORT MK_BITS(19, 1) 89 #define BITS_IRQS_D MK_BITS(20, 8) 90 91 #define BITS_IRQS_MASK_U (0xFF) 92 #define BITS_IRQS_MASK_D (0xFF << 20) 93 94 /* IRQs bit name */ 95 #define HIETH_INT_RX_RDY_U (1 << 0) 96 #define HIETH_INT_RX_RDY_D (1 << 20) 97 #define HIETH_INT_TX_FIN_U (1 << 1) 98 #define HIETH_INT_TX_FIN_D (1 << 21) 99 #define HIETH_INT_LINK_CH_U (1 << 2) 100 #define HIETH_INT_LINK_CH_D (1 << 22) 101 #define HIETH_INT_SPEED_CH_U (1 << 3) 102 #define HIETH_INT_SPEED_CH_D (1 << 23) 103 #define HIETH_INT_DUPLEX_CH_U (1 << 4) 104 #define HIETH_INT_DUPLEX_CH_D (1 << 24) 105 #define HIETH_INT_STATE_CH_U (1 << 5) 106 #define HIETH_INT_STATE_CH_D (1 << 25) 107 #define HIETH_INT_TXQUE_RDY_U (1 << 6) 108 #define HIETH_INT_TXQUE_RDY_D (1 << 26) 109 #define HIETH_INT_MULTI_RXRDY_U (1 << 7) 110 #define HIETH_INT_MULTI_RXRDY_D (1 << 27) 111 #define HIETH_INT_TX_ERR_U (1 << 8) 112 #define HIETH_INT_TX_ERR_D (1 << 28) 113 114 #define HIETH_INT_MDIO_FINISH (1 << 12) 115 #define HIETH_INT_UNKNOW_VLANID (1 << 13) 116 #define HIETH_INT_UNKNOW_VLANM (1 << 14) 117 118 #define GLB_DN_HOSTMAC_L32 0x1340 119 #define GLB_DN_HOSTMAC_H16 0x1344 120 #define GLB_DN_HOSTMAC_ENA 0x1348 121 #define BITS_DN_HOST_ENA MK_BITS(0, 1) 122 123 #define GLB_MAC_L32_BASE (0x1400) 124 #define GLB_MAC_H16_BASE (0x1404) 125 #define GLB_MAC_L32_BASE_D (0x1400 + 16 * 0x8) 126 #define GLB_MAC_H16_BASE_D (0x1404 + 16 * 0x8) 127 #define BITS_MACFLT_HI16 MK_BITS(0, 16) 128 #define BITS_MACFLT_FW2CPU_U MK_BITS(21, 1) 129 #define BITS_MACFLT_FW2PORT_U MK_BITS(20, 1) 130 #define BITS_MACFLT_ENA_U MK_BITS(17, 1) 131 #define BITS_MACFLT_FW2CPU_D MK_BITS(19, 1) 132 #define BITS_MACFLT_FW2PORT_D MK_BITS(18, 1) 133 #define BITS_MACFLT_ENA_D MK_BITS(16, 1) 134 135 /* Tx/Rx Queue depth */ 136 #define U_GLB_QLEN_SET 0x0344 137 #define D_GLB_QLEN_SET 0x2344 138 #define BITS_TXQ_DEP MK_BITS(0, 6) 139 #define BITS_RXQ_DEP MK_BITS(8, 6) 140 141 #define U_GLB_FC_LEVEL 0x0348 142 #define D_GLB_FC_LEVEL 0x2348 143 #define BITS_FC_DEACTIVE_THR MK_BITS(0, 6) 144 #define BITS_FC_ACTIVE_THR MK_BITS(8, 6) 145 #define BITS_FC_EN MK_BITS(14, 1) 146 147 #define BITS_PAUSE_EN MK_BITS(18, 1) 148 149 /* Rx (read only) Queue-ID and LEN */ 150 #define U_GLB_RO_IQFRM_DES 0x0354 151 #define D_GLB_RO_IQFRM_DES 0x2354 152 153 /* rx buffer addr. */ 154 #define U_GLB_RXFRM_SADDR 0x0350 155 #define D_GLB_RXFRM_SADDR 0x2350 156 /* bits of U_GLB_RO_IQFRM_DES */ 157 #define BITS_RXPKG_LEN MK_BITS(0, 11) 158 #define BITS_RXPKG_ID MK_BITS(12, 6) 159 #define BITS_FRM_VLAN_VID MK_BITS(18, 1) 160 #define BITS_FD_VID_VID MK_BITS(19, 1) 161 #define BITS_FD_VLANID MK_BITS(20, 12) 162 #define BITS_RXPKG_LEN_OFFSET 0 163 #define BITS_RXPKG_LEN_MASK 0xFFF 164 #define BITS_PAYLOAD_ERR_OFFSET 20 165 #define BITS_PAYLOAD_ERR_MASK 0x1 166 #define BITS_HEADER_ERR_OFFSET 21 167 #define BITS_HEADER_ERR_MASK 0x1 168 #define BITS_PAYLOAD_DONE_OFFSET 22 169 #define BITS_PAYLOAD_DONE_MASK 0x1 170 #define BITS_HEADER_DONE_OFFSET 23 171 #define BITS_HEADER_DONE_MASK 0x1 172 173 /* Rx ADDR */ 174 #define U_GLB_IQ_ADDR 0x0358 175 #define D_GLB_IQ_ADDR 0x2358 176 177 /* Tx ADDR and LEN */ 178 #define U_GLB_EQ_ADDR 0x0360 179 #define D_GLB_EQ_ADDR 0x2360 180 #define U_GLB_EQFRM_LEN 0x0364 181 #define D_GLB_EQFRM_LEN 0x2364 182 /* bits of U_GLB_EQFRM_LEN */ 183 #ifdef HIETH_TSO_SUPPORTED 184 #define BITS_TXINQ_LEN MK_BITS(0, 32) 185 #else 186 #define BITS_TXINQ_LEN MK_BITS(0, 11) 187 #endif 188 189 #ifdef HIETH_TSO_SUPPORTED 190 /* TSO debug enable */ 191 #define U_GLB_TSO_DBG_EN 0x03A4 192 #define D_GLB_TSO_DBG_EN 0x23A4 193 #define BITS_TSO_DBG_EN MK_BITS(31, 1) 194 /* TSO debug state */ 195 #define U_GLB_TSO_DBG_STATE 0x03A8 196 #define D_GLB_TSO_DBG_STATE 0x23A8 197 #define BITS_TSO_DBG_STATE MK_BITS(31, 1) 198 /* TSO debug addr */ 199 #define U_GLB_TSO_DBG_ADDR 0x03AC 200 #define D_GLB_TSO_DBG_ADDR 0x23AC 201 /* TSO debug tx info */ 202 #define U_GLB_TSO_DBG_TX_INFO 0x03B0 203 #define D_GLB_TSO_DBG_TX_INFO 0x23B0 204 /* TSO debug tx err */ 205 #define U_GLB_TSO_DBG_TX_ERR 0x03B4 206 #define D_GLB_TSO_DBG_TX_ERR 0x23B4 207 #endif 208 209 /* Rx/Tx Queue ID */ 210 #define U_GLB_RO_QUEUE_ID 0x0368 211 #define D_GLB_RO_QUEUE_ID 0x2368 212 /* bits of U_GLB_RO_QUEUE_ID */ 213 #define BITS_TXOUTQ_ID MK_BITS(0, 6) 214 #define BITS_TXINQ_ID MK_BITS(8, 6) 215 #define BITS_RXINQ_ID MK_BITS(16, 6) 216 217 /* Rx/Tx Queue staus */ 218 #define U_GLB_RO_QUEUE_STAT 0x036C 219 #define D_GLB_RO_QUEUE_STAT 0x236C 220 /* bits of U_GLB_RO_QUEUE_STAT */ 221 /* check this bit to see if we can add a Tx package */ 222 #define BITS_XMITQ_RDY MK_BITS(24, 1) 223 /* check this bit to see if we can add a Rx addr */ 224 #define BITS_RECVQ_RDY MK_BITS(25, 1) 225 /* counts in queue, include currently sending */ 226 #define BITS_XMITQ_CNT_INUSE MK_BITS(0, 6) 227 /* counts in queue, include currently receving */ 228 #define BITS_RECVQ_CNT_RXOK MK_BITS(8, 6) 229 230 #ifdef HIETH_TSO_SUPPORTED 231 #define E_MAC_TX_FAIL 2 232 #define E_MAC_SW_GSO 3 233 #endif 234 235 #define HIETH_CSUM_ENABLE 1 236 #define HIETH_CSUM_DISABLE 0 237 #if LWIP_TX_CSUM_OFFLOAD 238 #define HIETH_IPV4_VERSION_HW 0 239 #define HIETH_IPV6_VERSION_HW 1 240 #define HIETH_TRANS_TCP_TYPE_HW 0 241 #define HIETH_TRANS_UDP_TYPE_HW 1 242 #endif 243 #define FCS_BYTES 4 244 245 /* Rx COE control */ 246 #define U_GLB_RX_COE_CTRL 0x0380 247 #define D_GLB_RX_COE_CTRL 0x2380 248 #define BITS_COE_IPV6_UDP_ZERO_DROP MK_BITS(13, 1) 249 #define BITS_COE_PAYLOAD_DROP MK_BITS(14, 1) 250 #define BITS_COE_IPHDR_DROP MK_BITS(15, 1) 251 252 /* fephy trim */ 253 #define REG_LD_AM 0x3050 254 #define BIT_MASK_LD_SET MK_BITS(0, 0x1f) 255 #define REG_LDO_AM 0x3051 256 #define BIT_MASK_LDO_SET MK_BITS(0, 0x7) 257 #define REG_R_TUNING 0x3052 258 #define BIT_MASK_R_TUNING MK_BITS(0, 0x3f) 259 260 #define BIT_OFFSET_LD_SET 25 261 #define BIT_OFFSET_LDO_SET 22 262 #define BIT_OFFSET_R_TUNING 16 263 264 #define REG_DEF_ATE 0x3057 265 #define BIT_AUTOTRIM_DONE (0x1 << 0) 266 267 #define MII_EXPMD 0x1d 268 #define MII_EXPMA 0x1e 269 270 #define REG_WR_DONE 0x3053 271 #define BIT_CFG_DONE (0x1 << 0) 272 #define BIT_CFG_ACK (0x1 << 1) 273 274 #define IsRecvPacket(ld) (HiethRead(ld, GLB_RW_IRQ_RAW) & (UD_BIT_NAME(HIETH_INT_RX_RDY))) 275 276 #define HwSetRxpkgFinish(ld) HiethWrite(ld, UD_BIT_NAME(HIETH_INT_RX_RDY), GLB_RW_IRQ_RAW) 277 278 #define HwGetRxpkgInfo(ld) HiethRead(ld, UD_REG_NAME(GLB_RO_IQFRM_DES)) 279 280 #define HwXmitqCntInUse(ld) HiethReadlBits(ld, UD_REG_NAME(GLB_RO_QUEUE_STAT), BITS_XMITQ_CNT_INUSE) 281 282 #define HwXmitqPkg(ld, addr, len) \ 283 do { \ 284 HiethWrite(ld, (addr), UD_REG_NAME(GLB_EQ_ADDR)); \ 285 HiethWritelBits(ld, (len), UD_REG_NAME(GLB_EQFRM_LEN), BITS_TXINQ_LEN); \ 286 } while (0) 287 288 struct HiethPriv; 289 290 void HiethHwExternalPhyReset(void); 291 void HiethHwMacCoreInit(struct HiethNetdevLocal *ld); 292 void HiethFephyTrim(struct HiethNetdevLocal *ld, const EthPhyAccess *f); 293 294 int32_t TestXmitQueueReady(struct HiethNetdevLocal *ld); 295 296 /* return last irq_enable status */ 297 int32_t HiethIrqEnable(struct HiethNetdevLocal *ld, int32_t irqs); 298 299 /* return last irq_enable status */ 300 int32_t HiethIrqDisable(struct HiethNetdevLocal *ld, int32_t irqs); 301 302 /* return irqstatus */ 303 int32_t HiethReadIrqstatus(struct HiethNetdevLocal *ld); 304 305 /* return irqstatus after clean */ 306 int32_t HiethClearIrqstatus(struct HiethNetdevLocal *ld, int32_t irqs); 307 308 int32_t HiethSetEndianMode(struct HiethNetdevLocal *ld, int32_t mode); 309 310 /* Tx/Rx queue operation */ 311 int32_t HiethSetHwqDepth(struct HiethNetdevLocal *ld); 312 313 int32_t HiethHwSetMacAddress(struct HiethNetdevLocal *ld, int32_t ena, const uint8_t *mac); 314 int32_t HiethHwGetMacAddress(struct HiethNetdevLocal *ld, uint8_t *mac); 315 316 int32_t HiethFeedHw(struct HiethNetdevLocal *ld, HiethPriv *priv); 317 int32_t HiethXmitGso(struct HiethNetdevLocal *ld, const HiethPriv *priv, NetBuf *netBuf); 318 int32_t HiethXmitReleasePkt(struct HiethNetdevLocal *ld, const HiethPriv *priv); 319 void RegisterHiethData(struct EthDevice *ethDevice); 320 321 #ifdef __cplusplus 322 #if __cplusplus 323 } 324 #endif /* __cplusplus */ 325 #endif /* __cplusplus */ 326 327 #endif /* CTRL_H */ 328