Searched refs:CFG (Results 1 – 17 of 17) sorted by relevance
173 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_DACEN_MASK) in acmp_channel_enable_dac()188 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HPMODE_MASK) in acmp_channel_enable_hpmode()201 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HYST_MASK) in acmp_channel_set_hyst()216 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPEN_MASK) in acmp_channel_enable_cmp()231 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPOEN_MASK) in acmp_channel_enable_cmp_output()246 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTBYPS_MASK) in acmp_channel_cmp_output_bypass_filter()261 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_WINEN_MASK) in acmp_channel_enable_cmp_window_mode()276 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_OPOL_MASK) in acmp_channel_invert_output()289 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTMODE_MASK) in acmp_channel_set_filter_mode()304 ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_SYNCEN_MASK) in acmp_channel_enable_sync()[all …]
106 ptr->CFG = 0; in jpeg_clear_cfg()116 ptr->CFG &= ~JPEG_CFG_JPEG_EN_MASK; in jpeg_disable()126 ptr->CFG |= JPEG_CFG_JPEG_EN_MASK; in jpeg_enable()136 ptr->CFG &= ~JPEG_CFG_START_MASK; in jpeg_stop()146 ptr->CFG |= JPEG_CFG_START_MASK; in jpeg_start()194 ptr->CFG |= JPEG_CFG_JPEG_SFTRST_MASK; in jpeg_software_reset()195 ptr->CFG &= ~JPEG_CFG_JPEG_SFTRST_MASK; in jpeg_software_reset()
148 return 16 << ((ptr->CFG & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT); in uart_get_fifo_size()
111 DMA->CFG |= 0x1; // dma enable in duet_dma_mem2mem()162 DMA->CFG |= 0x1; // dma enable in duet_dma_uart_rx()208 DMA->CFG |= 0x1; // dma enable in duet_dma_uart_tx()254 DMA->CFG |= 0x1; // dma enable in duet_dma_spi_tx()301 DMA->CFG |= 0x1; // dma enable in duet_dma_spi_rx()
805 DMA->CFG |= 0x1; // dma enable in duet_i2c_master_dma_send()843 DMA->CFG |= 0x1; // dma enable in duet_i2c_master_dma_recv()
29 ptr->CFG &= ~(JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK); in jpeg_disable_irq()44 ptr->CFG |= JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK; in jpeg_enable_irq()207 ptr->CFG = JPEG_CFG_CFG_IPATH_SEL_SET(config->in_pixel_format) in jpeg_start_encode()266 ptr->CFG = JPEG_CFG_CFG_OPATH_SEL_SET(config->out_pixel_format) in jpeg_start_decode()
13 ptr->CHANNEL[ch].CFG = ACMP_CHANNEL_CFG_CMPEN_SET(enable) in acmp_channel_config()
45 ; unlock CFG
14 __RW uint32_t CFG; /* 0xC00: Configure Register */ member
14 __RW uint32_t CFG; /* 0x0: Configure Register */ member
14 __RW uint32_t CFG; /* 0x10: Configuration Register */ member
27 __RW uint32_t CFG; /* 0x40: Configuration Register */ member
360 WRITE_REG(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN); in ll_dma_enable()379 WRITE_REG(DMAx->MISCELLANEOU.CFG, 0); in ll_dma_disable()394 return (READ_BITS(DMAx->MISCELLANEOU.CFG, DMA_MODULE_CFG_EN) == DMA_MODULE_CFG_EN); in ll_dma_is_enable()
244 __O uint32_t CFG; member
188 DMA_REG(CFG); /**< DMA Configuration, Address offset: 0x00 */