Searched refs:CR0 (Results 1 – 4 of 4) sorted by relevance
99 SPIx->CR0 &= ~(0x3 << 6); // reset SPI clk phase/polarity setting to mode 0 in duet_spi_cpol_cpha_config()100 SPIx->CR0 |= (cpol << SPI_CLK_POLARITY_POS) | (cpha << SPI_CLK_PHASE_POS); in duet_spi_cpol_cpha_config()135 SPIx->CR0 &= ~(0x3 << 4); // reset FRF to 0 in duet_spi_init()136 SPIx->CR0 |= SPI_FRAME_FORMAT_SPI; in duet_spi_init()140 SPIx->CR0 &= (0x00ff); // reset SCR to 0 in duet_spi_init()141 …SPIx->CR0 |= (spi_clk / 2 / spi->config.freq - 1) << 8; // set SCR to 0x7, serial clk = 16M/2/(1+7… in duet_spi_init()165 SPIx->CR0 &= ~(0x3 << 6); // reset SPI clk phase/polarity setting to mode 0 in duet_spi_init()166 SPIx->CR0 |= (cpol << SPI_CLK_POLARITY_POS) | (cpha << SPI_CLK_PHASE_POS); in duet_spi_init()169 SPIx->CR0 &= ~(0xf); // reset data size to 0 in duet_spi_init()170 SPIx->CR0 |= SPI_DATA_SIZE_8BIT; in duet_spi_init()[all …]
73 #define CR0 (0u << 8) /** Carriage-return delay type 0. */ macro
82 #define CR0 0000000 macro
345 __IO uint32_t CR0 ; /* 0x0 */ member