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Searched refs:DIV (Results 1 – 25 of 33) sorted by relevance

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/device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/
Drockchip_vop2_clk.c53 #define DIV(cname, pname, f, w) \ macro
98 DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
99 DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
102 DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
103 DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
106 DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
107 DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
110 DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
111 DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
118 DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2),
[all …]
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
Drockchip_vop2_clk.c46 #define DIV(cname, pname, f, w) … macro
87 DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
88 DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
91 DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
92 DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
95 DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
96 DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
99 DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
100 DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
106 DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2),
[all …]
/device/board/isoftstone/yangfan/kernel/src/driv/gpu/rockchip/
Drockchip_vop2_clk.c53 #define DIV(cname, pname, f, w) \ macro
98 DIV("dclk_core0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
99 DIV("dclk_out0", "port0_dclk_src", CLK_SET_RATE_PARENT, 2),
102 DIV("dclk_core1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
103 DIV("dclk_out1", "port1_dclk_src", CLK_SET_RATE_PARENT, 2),
106 DIV("dclk_core2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
107 DIV("dclk_out2", "port2_dclk_src", CLK_SET_RATE_PARENT, 2),
110 DIV("dclk_core3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
111 DIV("dclk_out3", "port3_dclk_src", CLK_SET_RATE_PARENT, 2),
118 DIV("hdmi_edp0_dclk", "hdmi_edp0_clk_src", 0, 2),
[all …]
/device/soc/st/stm32f407zg/uniproton/board/common/STM32F4xx_StdPeriph_Driver/inc/
Dstm32f4xx_rcc.h473 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ argument
474 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
475 ((DIV) == RCC_MCO1Div_5))
495 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ argument
496 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
497 ((DIV) == RCC_MCO2Div_5))
Dstm32f4xx_fmc.h605 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15)) argument
Dstm32f4xx_fsmc.h467 #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) argument
Dstm32f4xx_tim.h306 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ argument
307 ((DIV) == TIM_CKD_DIV2) || \
308 ((DIV) == TIM_CKD_DIV4))
/device/soc/hpmicro/sdk/hpm_sdk/drivers/src/
Dhpm_pllctlv2_drv.c56 ptr->PLL[pll].DIV[div_index] = in pllctlv2_set_postdiv()
57 … (ptr->PLL[pll].DIV[div_index] & PLLCTLV2_DIV_DIV_MASK) | PLLCTLV2_DIV_DIV_SET(div_value) | in pllctlv2_set_postdiv()
78 uint32_t postdiv = PLLCTLV2_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); in pllctlv2_get_pll_postdiv_freq_in_hz()
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
Dclk-rk3368.c283 … DIV(0, "aclkm_core_b", "armclkb", 0, RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
284 … DIV(0, "atclk_core_b", "armclkb", 0, RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
285 DIV(0, "pclk_dbg_b", "armclkb", 0, RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
287 … DIV(0, "aclkm_core_l", "armclkl", 0, RK3368_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
288 … DIV(0, "atclk_core_l", "armclkl", 0, RK3368_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
289 DIV(0, "pclk_dbg_l", "armclkl", 0, RK3368_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
382 DIV(0, "hclk_vio", "aclk_vio0", 0, RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
418 DIV(0, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL, RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
Dclk-rk3228.c200 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
258 DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0, RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
315 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, RK2928_CLKSEL_CON(12), 0, 8, DFLAGS),
319 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, RK2928_CLKSEL_CON(12), 8, 8, DFLAGS),
328 DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0, RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
329 DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
Dclk-rk3036.c205 DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IS_CRITICAL, RK2928_CLKSEL_CON(10), 12, 2,
208 DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IS_CRITICAL, RK2928_CLKSEL_CON(10), 8, 2,
251 DIV(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_src", 0, RK2928_CLKSEL_CON(11), 0, 7, DFLAGS),
255 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, RK2928_CLKSEL_CON(11), 8, 7, DFLAGS),
Dclk-rk3288.c261 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
348 DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
360 … DIV(PCLK_PD_ALIVE, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL, RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
472 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0, RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
641 DIV(0, "hclk_vio", "aclk_vio1", 0, RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
645 DIV(0, "hclk_vio", "aclk_vio0", 0, RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
Dclk-rk3188.c482 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, RK2928_CLKSEL_CON(1), 12, 2,
484 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, RK2928_CLKSEL_CON(1), 8, 2,
563 …DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_…
564 …DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0, RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_O…
590 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0, RK2928_CLKSEL_CON(11), 8, 6, DFLAGS),
Dclk-rk3128.c192 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
277 DIV(SCLK_PVTM, "clk_pvtm", "clk_pvtm_func", 0, RK2928_CLKSEL_CON(2), 0, 7, DFLAGS),
294 DIV(SCLK_CIF_OUT, "sclk_cif_out", "sclk_cif_out_src", 0, RK2928_CLKSEL_CON(29), 2, 5, DFLAGS),
Dclk-rk3328.c215 DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED, RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
414 DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
431 DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0, RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
Dclk-rk3399.c463 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED, RK3399_CLKSEL_CON(3), 13, 2,
1009 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1043 DIV(0, "clk_test_24m", "xin24m", 0, RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1137 …DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS…
1149 …DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IS_CRITICAL, RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
/device/soc/st/common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/
Dstm32mp1xx_hal_rcc.h333 #define IS_RCC_HSIDIV(DIV) (((DIV) == RCC_HSI_DIV1) || ((DIV) == RCC_HSI_DIV2) || \ argument
334 ((DIV) == RCC_HSI_DIV4) || ((DIV) == RCC_HSI_DIV8) )
431 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ argument
432 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
433 ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \
434 ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \
435 ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \
436 ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \
437 ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \
438 ((DIV) == RCC_MCODIV_15) || ((DIV) == RCC_MCODIV_16) )
/device/soc/st/stm32f4xx/sdk/Drivers/STM32F4xx_HAL_Driver/Inc/
Dstm32f4xx_hal_rcc.h1435 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ argument
1436 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
1437 ((DIV) == RCC_MCODIV_5))
Dstm32f4xx_ll_fsmc.h917 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) argument
Dstm32f4xx_ll_fmc.h1184 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) argument
Dstm32f4xx_ll_sdmmc.h391 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) argument
/device/soc/rockchip/common/vendor/drivers/power/
Drk817_battery.c58 #define DIV(x) ((x) ? (x) : 1) macro
878 battery->voltage_k = (0x41A - 0x258) * 0x3E8 / DIV(vcalib1 - vcalib0); in rk817_bat_init_voltage_kb()
881 battery->voltage_k = (0xFB9 - 0x8FC) * 0x3E8 / DIV(vcalib1 - vcalib0); in rk817_bat_init_voltage_kb()
1351 return remain_cap * 0x64 / DIV(battery->fcc); in rk817_bat_get_rsoc()
1595 linek = 0x3E8 * (delta + diff) / DIV(diff); in rk817_bat_calc_sm_linek()
1597 linek = 0x3E8 * diff / DIV(delta + diff); in rk817_bat_calc_sm_linek()
1603 linek = -0x3E8 * diff / DIV(delta + diff); in rk817_bat_calc_sm_linek()
1605 linek = -0x3E8 * (delta + diff) / DIV(diff); in rk817_bat_calc_sm_linek()
2481 ydsoc = battery->sm_linek * abs(delta_cap / 0x0A) / DIV(battery->fcc); in rk817_bat_smooth_algorithm()
2611 battery->zero_linek = (battery->zero_dsoc + xsoc / 0x02) / DIV(xsoc); in rk817_bat_calc_zero_linek()
[all …]
/device/soc/rockchip/rk3588/kernel/drivers/power/supply/
Drk817_battery.c58 #define DIV(x) ((x) ? (x) : 1) macro
795 battery->voltage_k = (1050 - 600) * 1000 / DIV(vcalib1 - vcalib0); in rk817_bat_init_voltage_kb()
798 battery->voltage_k = (4025 - 2300) * 1000 / DIV(vcalib1 - vcalib0); in rk817_bat_init_voltage_kb()
1280 return remain_cap * 100 / DIV(battery->fcc); in rk817_bat_get_rsoc()
1534 linek = 1000 * (delta + diff) / DIV(diff); in rk817_bat_calc_sm_linek()
1536 linek = 1000 * diff / DIV(delta + diff); in rk817_bat_calc_sm_linek()
1541 linek = -1000 * diff / DIV(delta + diff); in rk817_bat_calc_sm_linek()
1543 linek = -1000 * (delta + diff) / DIV(diff); in rk817_bat_calc_sm_linek()
2437 ydsoc = battery->sm_linek * abs(delta_cap / 10) / DIV(battery->fcc); in rk817_bat_smooth_algorithm()
2572 (battery->zero_dsoc + xsoc / 2) / DIV(xsoc); in rk817_bat_calc_zero_linek()
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/soc/ip/
Dhpm_pllctlv2_regs.h26 …__RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration registe… member
/device/soc/rockchip/common/vendor/drivers/clk/
Dclk-rk1808.c414 DIV(HSCLK_PCIE, "hsclk_pcie", "clk_pcie_src", 0, RK1808_CLKSEL_CON(12), 0, 5, DFLAGS),
415 DIV(LSCLK_PCIE, "lsclk_pcie", "clk_pcie_src", 0, RK1808_CLKSEL_CON(12), 8, 5, DFLAGS),
425 DIV(0, "pclk_pcie_pre", "aclk_pcie", 0, RK1808_CLKSEL_CON(15), 4, 4, DFLAGS),

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