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Searched refs:DR_REG_SLC_BASE (Results 1 – 2 of 2) sorted by relevance

/device/soc/esp/esp32/components/soc/esp32/include/soc/
Dslc_reg.h19 #define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0)
213 #define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
377 #define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
541 #define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC)
705 #define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
869 #define SLC_1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
1021 #define SLC_1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
1173 #define SLC_1INT_ENA_REG (DR_REG_SLC_BASE + 0x1C)
1325 #define SLC_1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
1477 #define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
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Dsoc.h63 #define DR_REG_SLC_BASE 0x3ff58000 macro