1 /*
2 * include/linux/sunxi-gpio.h
3 *
4 * (C) Copyright 2015-2020
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Wim Hwang <huangwei@allwinnertech.com>
7 *
8 * sunxi gpio utils
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 */
15
16 #ifndef __SW_GPIO_H
17 #define __SW_GPIO_H
18
19 #define SUNXI_PINCTRL "pio"
20 #define SUNXI_R_PINCTRL "r_pio"
21 #include <linux/pinctrl/pinconf-generic.h>
22
23 /* pin group base number name space,
24 * the max pin number : 26*32=832.
25 */
26 #define SUNXI_BANK_SIZE 32
27 #define SUNXI_PA_BASE 0
28 #define SUNXI_PB_BASE 32
29 #define SUNXI_PC_BASE 64
30 #define SUNXI_PD_BASE 96
31 #define SUNXI_PE_BASE 128
32 #define SUNXI_PF_BASE 160
33 #define SUNXI_PG_BASE 192
34 #define SUNXI_PH_BASE 224
35 #define SUNXI_PI_BASE 256
36 #define SUNXI_PJ_BASE 288
37 #define SUNXI_PK_BASE 320
38 #define SUNXI_PL_BASE 352
39 #define SUNXI_PM_BASE 384
40 #define SUNXI_PN_BASE 416
41 #define SUNXI_PO_BASE 448
42 #define AXP_PIN_BASE 1024
43
44 #define SUNXI_PIN_NAME_MAX_LEN 8
45
46 /* sunxi gpio name space */
47 #define GPIOA(n) (SUNXI_PA_BASE + (n))
48 #define GPIOB(n) (SUNXI_PB_BASE + (n))
49 #define GPIOC(n) (SUNXI_PC_BASE + (n))
50 #define GPIOD(n) (SUNXI_PD_BASE + (n))
51 #define GPIOE(n) (SUNXI_PE_BASE + (n))
52 #define GPIOF(n) (SUNXI_PF_BASE + (n))
53 #define GPIOG(n) (SUNXI_PG_BASE + (n))
54 #define GPIOH(n) (SUNXI_PH_BASE + (n))
55 #define GPIOI(n) (SUNXI_PI_BASE + (n))
56 #define GPIOJ(n) (SUNXI_PJ_BASE + (n))
57 #define GPIOK(n) (SUNXI_PK_BASE + (n))
58 #define GPIOL(n) (SUNXI_PL_BASE + (n))
59 #define GPIOM(n) (SUNXI_PM_BASE + (n))
60 #define GPION(n) (SUNXI_PN_BASE + (n))
61 #define GPIOO(n) (SUNXI_PO_BASE + (n))
62 #define GPIO_AXP(n) (AXP_PIN_BASE + (n))
63
64 /* sunxi specific input/output/eint functions */
65 #define SUNXI_PIN_INPUT_FUNC (0)
66 #define SUNXI_PIN_OUTPUT_FUNC (1)
67 #define SUNXI_PIN_EINT_FUNC (6)
68 #define SUNXI_PIN_IO_DISABLE (7)
69
70 /* axp group base number name space,
71 * axp pinctrl number space coherent to sunxi-pinctrl.
72 */
73 #define AXP_PINCTRL "axp-pinctrl"
74 #define AXP_CFG_GRP (0xFFFF)
75 #define AXP_PIN_INPUT_FUNC (0)
76 #define AXP_PIN_OUTPUT_FUNC (1)
77 #define IS_AXP_PIN(pin) (pin >= AXP_PIN_BASE)
78
79 /* sunxi specific pull up/down */
80 enum sunxi_pull_up_down {
81 SUNXI_PULL_DISABLE = 0,
82 SUNXI_PULL_UP,
83 SUNXI_PULL_DOWN,
84 };
85
86 /* sunxi specific data types */
87 enum sunxi_data_type {
88 SUNXI_DATA_LOW = 0,
89 SUNXI_DATA_HIGH = 0,
90 };
91
92 /* sunxi specific pull status */
93 enum sunxi_pin_pull {
94 SUNXI_PIN_PULL_DISABLE = 0x00,
95 SUNXI_PIN_PULL_UP = 0x01,
96 SUNXI_PIN_PULL_DOWN = 0x02,
97 SUNXI_PIN_PULL_RESERVED = 0x03,
98 };
99
100 /* sunxi specific driver levels */
101 enum sunxi_pin_drv_level {
102 SUNXI_DRV_LEVEL0 = 10,
103 SUNXI_DRV_LEVEL1 = 20,
104 SUNXI_DRV_LEVEL2 = 30,
105 SUNXI_DRV_LEVEL3 = 40,
106 };
107
108 /* sunxi specific data bit status */
109 enum sunxi_pin_data_status {
110 SUNXI_PIN_DATA_LOW = 0x00,
111 SUNXI_PIN_DATA_HIGH = 0x01,
112 };
113
114 /* sunxi pin interrupt trigger mode */
115 enum sunxi_pin_int_trigger_mode {
116 SUNXI_PIN_EINT_POSITIVE_EDGE = 0x0,
117 SUNXI_PIN_EINT_NEGATIVE_EDGE = 0x1,
118 SUNXI_PIN_EINT_HIGN_LEVEL = 0x2,
119 SUNXI_PIN_EINT_LOW_LEVEL = 0x3,
120 SUNXI_PIN_EINT_DOUBLE_EDGE = 0x4
121 };
122
123 /* the source clock of pin int */
124 enum sunxi_pin_int_source_clk {
125 SUNXI_PIN_INT_SRC_CLK_32K = 0x0,
126 SUNXI_PIN_INT_SRC_CLK_24M = 0x1
127 };
128
129 /*
130 * pin configuration (pull up/down and drive strength) type and its value are
131 * packed together into a 32-bits. The lower 8-bits represent the configuration
132 * type and the upper 24-bits hold the value of the configuration type.
133 */
134 #define SUNXI_PINCFG_PACK(type, value) (((value) << 8) | (type & 0xFF))
135 #define SUNXI_PINCFG_UNPACK_TYPE(cfg) ((cfg) & 0xFF)
136 #define SUNXI_PINCFG_UNPACK_VALUE(cfg) (((cfg) & 0xFFFFFF00) >> 8)
137
sunxi_gpio_to_name(int gpio,char * name)138 static inline int sunxi_gpio_to_name(int gpio, char *name)
139 {
140 int bank, index;
141
142 if (!name)
143 return -EINVAL;
144
145 if (IS_AXP_PIN(gpio)) {
146 /* axp gpio name like this : GPIO0/GPIO1/.. */
147 index = gpio - AXP_PIN_BASE;
148 sprintf(name, "GPIO%d", index);
149 } else {
150 /* sunxi gpio name like this : PA0/PA1/PB0 */
151 bank = gpio / SUNXI_BANK_SIZE;
152 index = gpio % SUNXI_BANK_SIZE;
153 sprintf(name, "P%c%d", ('A' + bank), index);
154 }
155
156 return 0;
157 }
158
159 /* pio end, invalid macro */
160 #define GPIO_INDEX_INVALID (0xFFFFFFF0)
161 #define GPIO_CFG_INVALID (0xEEEEEEEE)
162 #define GPIO_PULL_INVALID (0xDDDDDDDD)
163 #define GPIO_DRVLVL_INVALID (0xCCCCCCCC)
164 #define IRQ_NUM_INVALID (0xFFFFFFFF)
165 #define AXP_PORT_VAL (0x0000FFFF)
166
167 /* pio default macro */
168 #define GPIO_PULL_DEFAULT ((u32)-1)
169 #define GPIO_DRVLVL_DEFAULT ((u32)-1)
170 #define GPIO_DATA_DEFAULT ((u32)-1)
171
172 /*
173 * struct gpio_config - gpio config info
174 * @gpio: gpio global index, must be unique
175 * @mul_sel: multi sel val: 0 - input, 1 - output.
176 * @pull: pull val: 0 - pull up/down disable, 1 - pull up
177 * @drv_level: driver level val: 0 - level 0, 1 - level 1
178 * @data: data val: 0 - low, 1 - high, only valid when mul_sel is input/output
179 */
180 struct gpio_config {
181 u32 data;
182 u32 gpio;
183 u32 mul_sel;
184 u32 pull;
185 u32 drv_level;
186 };
187
188 #endif
189