1 /*
2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 /**
17 * @file wm_regs.h
18 *
19 * @brief register & operation file
20 *
21 * @author winnermicro
22 *
23 * Copyright (c) 2015 Winner Microelectronics Co., Ltd.
24 */
25 #ifndef WM_REGS_H
26 #define WM_REGS_H
27
28 typedef volatile unsigned char vu8;
29 typedef volatile unsigned short vu16;
30 typedef volatile unsigned long vu32;
31
32 #define M8(adr) (*((vu8 *) (adr)))
33 #define M16(adr) (*((vu16*) (adr)))
34 #define M32(adr) (*((vu32*) (adr)))
35
36 #define ATTRIBUTE_ISR // __attribute__((isr))
37
38 typedef enum IRQn {
39 /****** W800 specific Interrupt Numbers *********************************************************/
40 SDIO_IRQn = 0, /*!< SDIO Receiver/Transmit/Command Receiver/SDIO Command Transmit Interrupt */
41 MAC_IRQn = 1, /*!< MAC Interrupt */
42 RF_CFG_IRQn = 2, /*!< RF_CFG Interrupt */
43 SEC_IRQn = 3, /*!< SEC RX/TX_MNGT/TX_DATA Interrupt */
44 DMA_Channel0_IRQn = 4, /*!< DMA Channel 0 global Interrupt */
45 DMA_Channel1_IRQn = 5, /*!< DMA Channel 1 global Interrupt */
46 DMA_Channel2_IRQn = 6, /*!< DMA Channel 2 global Interrupt */
47 DMA_Channel3_IRQn = 7, /*!< DMA Channel 3 global Interrupt */
48 DMA_Channel4_7_IRQn = 8, /*!< DMA Channel 4~7 global Interrupt */
49 DMA_BRUST_IRQn = 9, /*!< DMA Burst global Interrupt */
50 I2C_IRQn = 10, /*!< I2C Interrupts */
51 ADC_IRQn = 11, /*!< ADC Convert Interrupts */
52 SPI_LS_IRQn = 12, /*!< Low Speed SPI Interrupt */
53 SPI_HS_IRQn = 13, /*!< High Speed SPI Interrupt */
54 GPIOA_IRQn = 14, /*!< GPIO A Interrupt */
55 GPIOB_IRQn = 15, /*!< GPIO B Interrupt */
56 UART0_IRQn = 16, /*!< UART0 Interrupts */
57 UART1_IRQn = 17, /*!< UART1 Interrupt */
58 TOUCH_IRQn = 18, /*!< Touch Sensor Iterrupt */
59 UART24_IRQn = 19, /*!< UART2/3/4/5 Interrupt */
60 BLE_IRQn = 20, /*!< BLE Interrupt */
61 BT_IRQn = 21, /*!< BT Interrupt */
62 PWM_IRQn = 22, /*!< PWM Interrupt */
63 I2S_IRQn = 23, /*!< I2S Interrupts */
64 SIDO_HOST_IRQn = 24, /*!< SDIO Host Interrupts */
65 SYS_TICK_IRQn = 25, /*!< SYS Tick Interrupts */
66 RSA_IRQn = 26, /*!< RSA Interrupts */
67 CRYPTION_IRQn = 27, /*!< GPSEC Interrupts */
68 FLASH_IRQn = 28, /*!< Flash Interrupt */
69 PMU_IRQn = 29, /*!< PMU Interrupt */
70 TIMER_IRQn = 30, /*!< Timer0~5 Trigger */
71 WDG_IRQn = 31, /*!< Watch Dog Interrupt */
72 } IRQn_Type;
73
74 #include "wm_type_def.h"
75 #ifdef __cplusplus
76 #define __I volatile /*!< Defines 'read only' permissions */
77 #else
78 #define __I volatile const /*!< Defines 'read only' permissions */
79 #endif
80 #define __O volatile /*!< Defines 'write only' permissions */
81 #define __IO volatile /*!< Defines 'read / write' permissions */
82
83 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
84 typedef volatile unsigned int TLS_REG; /* Hardware register definition */
85
86 #ifndef BIT
87 #define BIT(x) (1UL << (x))
88 #endif
89
90 #define APB_CLK (40000000) /* 40MHz */
91
92 #define DEVICE_BASE_ADDR 0x40000000
93
94 /***************************************************************
95 * SDIO Reg
96 ***************************************************************/
97 #define HR_SDIO_BASE_ADDR (DEVICE_BASE_ADDR + 0x2400)
98 #define HR_SDIO_CIS0 (HR_SDIO_BASE_ADDR + 0x008)
99 #define HR_SDIO_CIS1 (HR_SDIO_BASE_ADDR + 0x00C)
100 #define HR_SDIO_CSA (HR_SDIO_BASE_ADDR + 0x010)
101 #define HR_SDIO_READ (HR_SDIO_BASE_ADDR + 0x014)
102 #define HR_SDIO_WRITE (HR_SDIO_BASE_ADDR + 0x018)
103 #define HR_SDIO_INTEN (HR_SDIO_BASE_ADDR + 0x030)
104 #define HR_SDIO_OCR (HR_SDIO_BASE_ADDR + 0x034)
105 #define HR_SDIO_CIA (HR_SDIO_BASE_ADDR + 0x024)
106 #define HR_SDIO_PROG (HR_SDIO_BASE_ADDR + 0x028)
107
108 /***************************************************************
109 * SDIO HOST Reg
110 ***************************************************************/
111 #define HR_SDIO_HOST_BASE_ADDR (DEVICE_BASE_ADDR + 0xA00)
112 #define HR_SDIO_HOST_MMC_CTRL (HR_SDIO_HOST_BASE_ADDR + 0x0)
113
114 /***************************************************************
115 * HSPI Reg
116 ***************************************************************/
117 #define HR_HSPI_BASE_ADDR (DEVICE_BASE_ADDR + 0x2600)
118 #define HR_HSPI_CLEAR_FIFO (HR_HSPI_BASE_ADDR)
119 #define HR_HSPI_SPI_CFG (HR_HSPI_BASE_ADDR + 0x04)
120 #define HR_HSPI_MODE_CFG (HR_HSPI_BASE_ADDR + 0x08)
121 #define HR_HSPI_INT_MASK (HR_HSPI_BASE_ADDR + 0x0C)
122 #define HR_HSPI_INT_STTS (HR_HSPI_BASE_ADDR + 0x10)
123 #define HR_HSPI_RXDAT_LEN (HR_HSPI_BASE_ADDR + 0x18)
124
125 /***************************************************************
126 * Inner Flash Reg
127 ***************************************************************/
128 #define HR_FLASH_BASE_ADDR (DEVICE_BASE_ADDR + 0x2000)
129 #define HR_FLASH_CMD_ADDR (HR_FLASH_BASE_ADDR + 0x000)
130 #define HR_FLASH_CMD_START (HR_FLASH_BASE_ADDR + 0x004)
131 #define HR_FLASH_CR (HR_FLASH_BASE_ADDR + 0x008)
132 #define HR_FLASH_ADDR (HR_FLASH_BASE_ADDR + 0x010)
133 /***************************************************************
134 * SDIO WRAPPER Register
135 ***************************************************************/
136 #define HR_SDIO_WRAPPER_BASE_ADDR (DEVICE_BASE_ADDR + 0x2800)
137 #define HR_SDIO_INT_SRC (HR_SDIO_WRAPPER_BASE_ADDR + 0x000)
138 #define HR_SDIO_INT_MASK (HR_SDIO_WRAPPER_BASE_ADDR + 0x004)
139 #define HR_SDIO_UPCMDVALID (HR_SDIO_WRAPPER_BASE_ADDR + 0x008)
140 #define HR_SDIO_DOWNCMDVALID (HR_SDIO_WRAPPER_BASE_ADDR + 0x00C)
141 #define HR_SDIO_TXBD_LINKEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x010)
142 #define HR_SDIO_TXBD_ADDR (HR_SDIO_WRAPPER_BASE_ADDR + 0x014)
143 #define HR_SDIO_TXEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x018)
144 #define HR_SDIO_TX_STTS (HR_SDIO_WRAPPER_BASE_ADDR + 0x01C)
145 #define HR_SDIO_RXBD_LINKEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x020)
146 #define HR_SDIO_RXBD_ADDR (HR_SDIO_WRAPPER_BASE_ADDR + 0x024)
147 #define HR_SDIO_RXEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x028)
148 #define HR_SDIO_RX_STTS (HR_SDIO_WRAPPER_BASE_ADDR + 0x02C)
149 #define HR_SDIO_CMD_ADDR (HR_SDIO_WRAPPER_BASE_ADDR + 0x030)
150 #define HR_SDIO_CMD_SIZE (HR_SDIO_WRAPPER_BASE_ADDR + 0x034)
151
152 /* SDIO interrupt bit definition */
153 #define SDIO_WP_INT_SRC_CMD_DOWN (1UL<<3)
154 #define SDIO_WP_INT_SRC_CMD_UP (1UL<<2)
155 #define SDIO_WP_INT_SRC_DATA_DOWN (1UL<<1)
156 #define SDIO_WP_INT_SRC_DATA_UP (1UL<<0)
157
158 /***************************************************************
159 * DMA Reg
160 ***************************************************************/
161 #define HR_DMA_BASE_ADDR (DEVICE_BASE_ADDR + 0x800)
162 #define HR_DMA_INT_MASK (HR_DMA_BASE_ADDR + 0x0)
163 #define HR_DMA_INT_SRC (HR_DMA_BASE_ADDR + 0x4)
164 #define HR_DMA_CHNL_SEL (HR_DMA_BASE_ADDR + 0x08)
165 #define HR_DMA_CHNL0_SRC_ADDR (HR_DMA_BASE_ADDR + 0x10)
166 #define HR_DMA_CHNL0_DEST_ADDR (HR_DMA_BASE_ADDR + 0x14)
167 #define HR_DMA_CHNL0_SRC_WRAP_ADDR (HR_DMA_BASE_ADDR + 0x18)
168 #define HR_DMA_CHNL0_DEST_WRAP_ADDR (HR_DMA_BASE_ADDR + 0x1C)
169 #define HR_DMA_CHNL0_WRAP_SIZE (HR_DMA_BASE_ADDR + 0x20)
170 #define HR_DMA_CHNL0_CHNL_CTRL (HR_DMA_BASE_ADDR + 0x24)
171 #define HR_DMA_CHNL0_DMA_MODE (HR_DMA_BASE_ADDR + 0x28)
172 #define HR_DMA_CHNL0_DMA_CTRL (HR_DMA_BASE_ADDR + 0x2C)
173 #define HR_DMA_CHNL0_DMA_STATUS (HR_DMA_BASE_ADDR + 0x30)
174 #define HR_DMA_CHNL0_LINK_DEST_ADDR (HR_DMA_BASE_ADDR + 0x34)
175 #define HR_DMA_CHNL0_CURRENT_DEST_ADDR (HR_DMA_BASE_ADDR + 0x38)
176
177 #define DMA_STARTADDRESS HR_DMA_BASE_ADDR
178 #define DMA_INTMASK_REG (*(volatile unsigned int*)(DMA_STARTADDRESS+0x000))
179 #define DMA_INTSRC_REG (*(volatile unsigned int*)(DMA_STARTADDRESS+0x004))
180 #define DMA_CHANNEL_SEL (*(volatile unsigned int*)(DMA_STARTADDRESS+0x008))
181 #define DMA_CHNL_REG_BASE (DMA_STARTADDRESS+0x010)
182 #define DMA_SRCADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x00))
183 #define DMA_DESTADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x04))
184 #define DMA_SRCWRAPADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x08))
185 #define DMA_DESTWRAPADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x0C))
186 #define DMA_WRAPSIZE_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x10))
187 #define DMA_CHNLCTRL_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x14))
188 #define DMA_MODE_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x18))
189 #define DMA_CTRL_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x1C))
190 #define DMA_STATUS_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x20))
191 #define DMA_DESC_ADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x24))
192 #define DMA_CURRDESTADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /* - 1 */) +0x28))
193
194 #define DMA_CHNL_CTRL_CHNL_ON (1<<0)
195 #define DMA_CHNL_CTRL_CHNL_OFF (1<<1)
196
197 #define DMA_MODE_HARD_MODE (1<<0)
198 #define DMA_MODE_CHAIN_MODE (1<<1)
199
200 #define DMA_MODE_SEL_MASK (0xF<<2)
201 #define DMA_MODE_SEL_UART_RX (0<<2)
202 #define DMA_MODE_SEL_UART_TX (1<<2)
203 #define DMA_MODE_SEL_PWM0 (2<<2)
204 #define DMA_DODE_SEL_PWM1 (3<<2)
205 #define DMA_MODE_SEL_LSSPI_RX (4<<2)
206 #define DMA_MODE_SEL_LSSPI_TX (5<<2)
207 #define DMA_MODE_SEL_SDADC_CH0 (6<<2)
208 #define DMA_MODE_SEL_SDADC_CH1 (7<<2)
209 #define DMA_MODE_SEL_SDADC_CH2 (8<<2)
210 #define DMA_MODE_SEL_SDADC_CH3 (9<<2)
211 #define DMA_MODE_SEL_I2S_RX (10<<2)
212 #define DMA_MODE_SEL_I2S_TX (11<<2)
213 #define DMA_MODE_SEL_SDIOHOST (12<<2)
214
215 #define DMA_MODE_CHAIN_LINK_EN (1<<6)
216
217 #define DMA_CTRL_AUTO_RELOAD (1<<0)
218 #define DMA_CTRL_SRC_ADDR_INC (1<<1)
219 #define DMA_CTRL_SRC_ADDR_CIR (3<<1)
220 #define DMA_CTRL_DEST_ADDR_INC (1<<3)
221 #define DMA_CTRL_DEST_ADDR_CIR (3<<3)
222 #define DMA_CTRL_DATA_SIZE_BYTE (0<<5)
223 #define DMA_CTRL_DATA_SIZE_SHORT (1<<5)
224 #define DMA_CTRL_DATA_SIZE_WORD (2<<5)
225 #define DMA_CTRL_BURST_SIZE1 (0<<7)
226 #define DMA_CTRL_BURST_SIZE4 (1<<7)
227
228 #define DMA_CTRL_TOTAL_MASK (0xFFF<<8)
229 #define DMA_CTRL_TOTAL_SIZE(n) ((n)<<8)
230
231 /***************************************************************
232 * PMU Reg
233 ***************************************************************/
234 #define HR_PMU_BASE_ADDR (DEVICE_BASE_ADDR + 0xD00)
235 #define HR_PMU_PS_CR (HR_PMU_BASE_ADDR + 0x00)
236 #define HR_PMU_TIMER0 (HR_PMU_BASE_ADDR + 0x04)
237 #define HR_PMU_TIMER1 (HR_PMU_BASE_ADDR + 0x08)
238 #define HR_PMU_RTC_CTRL1 (HR_PMU_BASE_ADDR + 0x0C)
239 #define HR_PMU_RTC_CTRL2 (HR_PMU_BASE_ADDR + 0x10)
240 #define HR_PMU_INTERRUPT_SRC (HR_PMU_BASE_ADDR + 0x14)
241 #define HR_PMU_INTERRUPT_MASK (HR_PMU_BASE_ADDR + 0x18)
242 #define HR_PMU_WLAN_STTS (HR_PMU_BASE_ADDR + 0x1C)
243 #define HR_PMU_BK_REG (HR_PMU_BASE_ADDR + 0x20)
244
245 #define PMU_TIMER0_NTERRUPT_SRC (1UL << 0)
246 #define PMU_TIMER1_NTERRUPT_SRC (1UL << 1)
247 #define PMU_GPIO_NTERRUPT_SRC (1UL << 2)
248
249 /***************************************************************
250 * system clock and bus clock Reg
251 ***************************************************************/
252 #define HR_CLK_BASE_ADDR (DEVICE_BASE_ADDR + 0xE00)
253 #define HR_CLK_GATE_EN HR_CLK_BASE_ADDR
254 #define HR_CLK_SOFT_CLK_MASK (HR_CLK_BASE_ADDR + 0x04)
255 #define HR_CLK_BBP_CLT_CTRL (HR_CLK_BASE_ADDR + 0x08)
256 #define HR_CLK_RST_CTL (HR_CLK_BASE_ADDR + 0x0c)
257 #define HR_CLK_DIV_CTL (HR_CLK_BASE_ADDR + 0x10)
258 #define HR_CLK_SEL_CTL (HR_CLK_BASE_ADDR + 0x14)
259 #define HR_OSC_32K_REG (HR_CLK_BASE_ADDR + 0x14)
260 #define HR_CLK_I2S_CTL (HR_CLK_BASE_ADDR + 0x18)
261 #define HR_CLK_RST_STA (HR_CLK_BASE_ADDR + 0x1C)
262
263 /***************************************************************
264 * �ڴ�ģ��Ĵ�������
265 ***************************************************************/
266 #define HR_MEM_BASE_ADDR (DEVICE_BASE_ADDR + 0xF00)
267 #define HR_MEM_TXBUF_BASE_ADDR (HR_MEM_BASE_ADDR + 0x00)
268 #define HR_MEM_RXBUF_BASE_ADDR (HR_MEM_BASE_ADDR + 0x04)
269 #define HR_MEM_BUF_NUM_CFG (HR_MEM_BASE_ADDR + 0x08)
270 #define HR_MEM_BUF_SIZE_CFG (HR_MEM_BASE_ADDR + 0x0C)
271 #define HR_MEM_AGGR_CFG (HR_MEM_BASE_ADDR + 0x10)
272 #define HR_MEM_BUF_EN (HR_MEM_BASE_ADDR + 0x14)
273
274 /***************************************************************
275 * PSRAM CTRL Register
276 ****************************************************************/
277 #define HR_PSRRAM_BASE_ADDR (DEVICE_BASE_ADDR + 0x2200)
278 #define HR_PSRAM_CTRL_ADDR (HR_PSRRAM_BASE_ADDR+ 0x00)
279 #define HR_PSRAM_OVERTIMER_ADDR (HR_PSRRAM_BASE_ADDR+ 0x04)
280
281 /* APB BaseAddr */
282 #define HR_APB_BASE_ADDR 0x40010000
283
284 /***************************************************************
285 * I2C Reg
286 ***************************************************************/
287 #define HR_I2C_BASE_ADDR (HR_APB_BASE_ADDR)
288 #define HR_I2C_PRER_LO (HR_I2C_BASE_ADDR + 0x0)
289 #define HR_I2C_PRER_HI (HR_I2C_BASE_ADDR + 0x04)
290 #define HR_I2C_CTRL (HR_I2C_BASE_ADDR + 0x08)
291 #define HR_I2C_TX_RX (HR_I2C_BASE_ADDR + 0x0C)
292 #define HR_I2C_CR_SR (HR_I2C_BASE_ADDR + 0x10)
293 #define HR_I2C_TXR (HR_I2C_BASE_ADDR + 0x14)
294 #define HR_I2C_CR (HR_I2C_BASE_ADDR + 0x18)
295
296 #define I2C_CTRL_INT_DISABLE (0x1UL<<6)
297 #define I2C_CTRL_ENABLE (0x1UL<<7)
298
299 #define I2C_CR_STA (0x1UL<<7)
300 #define I2C_CR_STO (0x1UL<<6)
301 #define I2C_CR_RD (0x1UL<<5)
302 #define I2C_CR_WR (0x1UL<<4)
303 #define I2C_CR_NAK (0x1UL<<3)
304 #define I2C_CR_IACK (0x1UL)
305
306 #define I2C_SR_NAK (0x1UL<<7)
307 #define I2C_SR_BUSY (0x1UL<<6)
308 #define I2C_SR_TIP (0x1UL<<1)
309 #define I2C_SR_IF (0x1UL)
310
311 /***************************************************************
312 * SD ADC Reg
313 ***************************************************************/
314 #define HR_SD_ADC_BASE_ADDR (HR_APB_BASE_ADDR + 0x200)
315 #define HR_SD_ADC_RESULT_REG ((HR_SD_ADC_BASE_ADDR+0x000))
316 #define HR_SD_ADC_ANA_CTRL ((HR_SD_ADC_BASE_ADDR+0x004))
317 #define HR_SD_ADC_PGA_CTRL ((HR_SD_ADC_BASE_ADDR+0x008))
318 #define HR_SD_ADC_TEMP_CTRL ((HR_SD_ADC_BASE_ADDR+0x00C))
319 #define HR_SD_ADC_CTRL ((HR_SD_ADC_BASE_ADDR+0x010))
320 #define HR_SD_ADC_INT_STATUS ((HR_SD_ADC_BASE_ADDR+0x014))
321 #define HR_SD_ADC_CMP_VALUE ((HR_SD_ADC_BASE_ADDR+0x018))
322
323 /***************************************************************
324 * Low Speed SPI Reg
325 ***************************************************************/
326 #define HR_SPI_BASE_ADDR (HR_APB_BASE_ADDR + 0x400)
327 #define HR_SPI_CHCFG_REG (HR_SPI_BASE_ADDR + 0x000)
328 #define HR_SPI_SPICFG_REG (HR_SPI_BASE_ADDR + 0x004)
329 #define HR_SPI_CLKCFG_REG (HR_SPI_BASE_ADDR + 0x008)
330 #define HR_SPI_MODECFG_REG (HR_SPI_BASE_ADDR + 0x00C)
331 #define HR_SPI_INT_MASK_REG (HR_SPI_BASE_ADDR + 0x010)
332 #define HR_SPI_INT_STATUS_REG (HR_SPI_BASE_ADDR + 0x014)
333 #define HR_SPI_STATUS_REG (HR_SPI_BASE_ADDR + 0x018)
334 #define HR_SPI_TIMEOUT_REG (HR_SPI_BASE_ADDR + 0x01C)
335 #define HR_SPI_TXDATA_REG (HR_SPI_BASE_ADDR + 0x020)
336 #define HR_SPI_TRANSLEN_REG (HR_SPI_BASE_ADDR + 0x024)
337 #define HR_SPI_SLV_XMIT_LEN_REG (HR_SPI_BASE_ADDR + 0x028)
338 #define HR_SPI_RXDATA_REG (HR_SPI_BASE_ADDR + 0x030)
339
340 #define SPIM_STARTADDRESS (HR_APB_BASE_ADDR + 0x400)
341 #define SPIM_CHCFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x000))
342 #define SPIM_SPICFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x004))
343 #define SPIM_CLKCFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x008))
344 #define SPIM_MODECFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x00C))
345 #define SPIM_INTEN_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x010))
346 #define SPIM_INTSRC_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x014))
347 #define SPIM_SPISTATUS_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x018))
348 #define SPIM_SPITIMEOUT_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x01C))
349 #define SPIM_TXDATA_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x020))
350 #define SPIM_TRANSLEN_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x024))
351 #define SPIM_RXDATA_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x030))
352
353 /* RSA Reg */
354 #define RSA_BASE_ADDRESS 0x40000000
355 #define RSAXBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x0)))
356 #define RSAYBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x100)))
357 #define RSAMBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x200)))
358 #define RSADBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x300)))
359 #define RSACON (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x400)))
360 #define RSAMC (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x404)))
361 #define RSAN (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x408))) /* Bits Definitions of "CH_CFG" */
362 #define SPI_RX_INVALID_BITS(n) ((n) << 23)
363 #define SPI_CLEAR_FIFOS (1U << 22)
364 #define SPI_CONTINUE_MODE (1U << 21)
365 #define SPI_RX_CHANNEL_ON (1U << 20)
366 #define SPI_RX_CHANNEL_OFF (0U << 20)
367 #define SPI_TX_CHANNEL_ON (1U << 19)
368 #define SPI_TX_CHANNEL_OFF (0U << 19)
369 #define SPI_VALID_CLKS_NUM(n) ((n) << 3)
370 #define SPI_CS_LOW (0U << 2)
371 #define SPI_CS_HIGH (1U << 2)
372 #define SPI_FORCE_SPI_CS_OUT (1U << 1)
373 #define SPI_START (1U << 0)
374
375 /* Bits Definitions of "SPI_CFG" */
376 #define SPI_FRAME_FORMAT_MOTO (0U << 17)
377 #define SPI_FRAME_FORMAT_TI (1U << 17)
378 #define SPI_FRAME_FORMAT_MICROWAIRE (2U << 17)
379 #define SPI_TX_PIN_ALWS_DRIVER (1U << 16)
380 #define SPI_CS_HOLD(n) ((n) << 12)
381 #define CS_HOLD_1_CLKS 0
382 #define CS_HOLD_2_CLKS 1
383 #define CS_HOLD_4_CLKS 2
384 #define CS_HOLD_8_CLKS 3
385 #define CS_HOLD_16_CLKS 4
386 #define CS_HOLD_32_CLKS 5
387 #define CS_HOLD_64_CLKS 6
388 #define CS_HOLD_127_CLKS 7
389 #define SPI_CS_SETUP(n) ((n) << 9)
390 #define CS_SETUP_1_CLKS 0
391 #define CS_SETUP_2_CLKS 1
392 #define CS_SETUP_4_CLKS 2
393 #define CS_SETUP_8_CLKS 3
394 #define CS_SETUP_16_CLKS 4
395 #define CS_SETUP_32_CLKS 5
396 #define CS_SETUP_64_CLKS 6
397 #define CS_SETUP_127_CLKS 7
398 #define SPI_DATA_OUT_DELAY(n) ((n) << 7)
399 #define DATA_OUT_DELAY_1_CLKS 0
400 #define DATA_OUT_DELAY_2_CLKS 1
401 #define DATA_OUT_DELAY_3_CLKS 2
402 #define DATA_OUT_DELAY_0_CLKS 3
403 #define SPI_FRAME_DELAY(n) ((n) << 4)
404 #define FRAME_DELAY_1_CLKS 0
405 #define FRAME_DELAY_2_CLKS 1
406 #define FRAME_DELAY_4_CLKS 2
407 #define FRAME_DELAY_8_CLKS 3
408 #define FRAME_DELAY_16_CLKS 4
409 #define FRAME_DELAY_32_CLKS 5
410 #define FRAME_DELAY_64_CLKS 6
411 #define FRAME_DELAY_127_CLKS 7
412 #define SPI_LITTLE_ENDIAN (0 << 3)
413 #define SPI_BIG_ENDIAN (1 << 3)
414 #define SPI_SET_MASTER_SLAVE(mode) ((mode) << 2)
415 #define SPI_MASTER 1
416 #define SPI_SLAVE 0
417 #define SPI_SET_CPHA(n) ((n) << 1)
418 #define SPI_SET_CPOL(n) ((n) << 0)
419
420 /* Bits Definitions of "CLK_CFG" */
421 #define SPI_GET_SCLK_DIVIDER(clk) ((APB_CLK)/((clk) * 2) - 1) /* In HZ */
422 #define SPI_SCLK_DIVIDER(n) ((n) << 0)
423
424 /* Bits Definitions of "MODE_CFG" */
425 #define SPI_RX_TRIGGER_LEVEL(n) ((n) << 6)
426 #define SPI_TX_TRIGGER_LEVEL(n) ((n) << 2)
427 #define SPI_RX_DMA_ON (1 << 1)
428 #define SPI_RX_DMA_OFF (0 << 1)
429 #define SPI_TX_DMA_ON (1 << 0)
430 #define SPI_TX_DMA_OFF (0 << 0)
431
432 /* Bits Definitions of SPI interrupt register(SPI_INT_MASK and SPI_INT_SOURCE) */
433 #define SPI_INT_MASK_ALL 0xffU
434 #define SPI_INT_CLEAR_ALL 0xffU
435 #define SPI_INT_TIMEOUT (1U << 7)
436 #define SPI_INT_TRANSFER_DONE (1U << 6)
437 #define SPI_INT_RX_OVERRUN (1U << 5)
438 #define SPI_INT_RX_UNDERRUN (1U << 4)
439 #define SPI_INT_TX_OVERRUN (1U << 3)
440 #define SPI_INT_TX_UNDERRUN (1U << 2)
441 #define SPI_INT_RX_FIFO_RDY (1U << 1)
442 #define SPI_INT_TX_FIFO_RDY (1U << 0)
443
444 /* Bits Definitions of "SPI_STATUS" */
445 #define SPI_IS_BUSY(value) ((((value) & (1 << 12)) != 0) ? 1 : 0)
446 #define SPI_GET_RX_FIFO_CNT(value) (((value) & 0xFC0) >> 6)
447 #define SPI_GET_TX_FIFO_CNT(value) ((value) & 0x3F)
448
449 /* Bits Definitions of "SPI_TIMEOUT" */
450 #define SPI_TIMER_EN (1U << 31)
451 #define SPI_TIME_OUT(n) (((((n) * (APB_CLK)) / 1000) & ~(0x01U << 31)) << 0)
452
453 /***************************************************************
454 * UART Reg
455 ***************************************************************/
456 #define HR_UART0_BASE_ADDR (HR_APB_BASE_ADDR + 0x600)
457 #define HR_UART1_BASE_ADDR (HR_APB_BASE_ADDR + 0x800)
458 #define HR_UART2_BASE_ADDR (HR_APB_BASE_ADDR + 0xA00)
459 #define HR_UART3_BASE_ADDR (HR_APB_BASE_ADDR + 0xC00)
460 #define HR_UART4_BASE_ADDR (HR_APB_BASE_ADDR + 0xE00)
461
462 #define HR_UART0_LINE_CTRL (HR_UART0_BASE_ADDR + 0x0)
463 #define HR_UART0_FLOW_CTRL (HR_UART0_BASE_ADDR + 0x04)
464 #define HR_UART0_DMA_CTRL (HR_UART0_BASE_ADDR + 0x08)
465 #define HR_UART0_FIFO_CTRL (HR_UART0_BASE_ADDR + 0x0C)
466 #define HR_UART0_BAUD_RATE_CTRL (HR_UART0_BASE_ADDR + 0x10)
467 #define HR_UART0_INT_MASK (HR_UART0_BASE_ADDR + 0x14)
468 #define HR_UART0_INT_SRC (HR_UART0_BASE_ADDR + 0x18)
469 #define HR_UART0_FIFO_STATUS (HR_UART0_BASE_ADDR + 0x1C)
470 #define HR_UART0_TX_WIN (HR_UART0_BASE_ADDR + 0x20)
471 #define HR_UART0_RX_WIN (HR_UART0_BASE_ADDR + 0x30)
472
473 #define HR_UART1_LINE_CTRL (HR_UART1_BASE_ADDR + 0x0)
474 #define HR_UART1_FLOW_CTRL (HR_UART1_BASE_ADDR + 0x04)
475 #define HR_UART1_DMA_CTRL (HR_UART1_BASE_ADDR + 0x08)
476 #define HR_UART1_FIFO_CTRL (HR_UART1_BASE_ADDR + 0x0C)
477 #define HR_UART1_BAUD_RATE_CTRL (HR_UART1_BASE_ADDR + 0x10)
478 #define HR_UART1_INT_MASK (HR_UART1_BASE_ADDR + 0x14)
479 #define HR_UART1_INT_SRC (HR_UART1_BASE_ADDR + 0x18)
480 #define HR_UART1_FIFO_STATUS (HR_UART1_BASE_ADDR + 0x1C)
481 #define HR_UART1_TX_WIN (HR_UART1_BASE_ADDR + 0x20)
482 #define HR_UART1_RX_WIN (HR_UART1_BASE_ADDR + 0x30)
483
484 #define HR_UART2_LINE_CTRL (HR_UART2_BASE_ADDR + 0x0)
485 #define HR_UART2_FLOW_CTRL (HR_UART2_BASE_ADDR + 0x04)
486 #define HR_UART2_DMA_CTRL (HR_UART2_BASE_ADDR + 0x08)
487 #define HR_UART2_FIFO_CTRL (HR_UART2_BASE_ADDR + 0x0C)
488 #define HR_UART2_BAUD_RATE_CTRL (HR_UART2_BASE_ADDR + 0x10)
489 #define HR_UART2_INT_MASK (HR_UART2_BASE_ADDR + 0x14)
490 #define HR_UART2_INT_SRC (HR_UART2_BASE_ADDR + 0x18)
491 #define HR_UART2_FIFO_STATUS (HR_UART2_BASE_ADDR + 0x1C)
492 #define HR_UART2_TX_WIN (HR_UART2_BASE_ADDR + 0x20)
493 #define HR_UART2_RX_WIN (HR_UART2_BASE_ADDR + 0x30)
494 #define HR_UART2_GUARD_TIME (HR_UART2_BASE_ADDR + 0x40)
495 #define HR_UART2_WAIT_TIME (HR_UART2_BASE_ADDR + 0x44)
496 #define HR_UART2_GT (HR_UART2_BASE_ADDR + 0x40)
497 #define HR_UART2_WT (HR_UART2_BASE_ADDR + 0x44)
498
499 #define HR_UART3_LINE_CTRL (HR_UART3_BASE_ADDR + 0x0)
500 #define HR_UART3_FLOW_CTRL (HR_UART3_BASE_ADDR + 0x04)
501 #define HR_UART3_DMA_CTRL (HR_UART3_BASE_ADDR + 0x08)
502 #define HR_UART3_FIFO_CTRL (HR_UART3_BASE_ADDR + 0x0C)
503 #define HR_UART3_BAUD_RATE_CTRL (HR_UART3_BASE_ADDR + 0x10)
504 #define HR_UART3_INT_MASK (HR_UART3_BASE_ADDR + 0x14)
505 #define HR_UART3_INT_SRC (HR_UART3_BASE_ADDR + 0x18)
506 #define HR_UART3_FIFO_STATUS (HR_UART3_BASE_ADDR + 0x1C)
507 #define HR_UART3_TX_WIN (HR_UART3_BASE_ADDR + 0x20)
508 #define HR_UART3_RX_WIN (HR_UART3_BASE_ADDR + 0x30)
509
510 #define HR_UART4_LINE_CTRL (HR_UART4_BASE_ADDR + 0x0)
511 #define HR_UART4_FLOW_CTRL (HR_UART4_BASE_ADDR + 0x04)
512 #define HR_UART4_DMA_CTRL (HR_UART4_BASE_ADDR + 0x08)
513 #define HR_UART4_FIFO_CTRL (HR_UART4_BASE_ADDR + 0x0C)
514 #define HR_UART4_BAUD_RATE_CTRL (HR_UART4_BASE_ADDR + 0x10)
515 #define HR_UART4_INT_MASK (HR_UART4_BASE_ADDR + 0x14)
516 #define HR_UART4_INT_SRC (HR_UART4_BASE_ADDR + 0x18)
517 #define HR_UART4_FIFO_STATUS (HR_UART4_BASE_ADDR + 0x1C)
518 #define HR_UART4_TX_WIN (HR_UART4_BASE_ADDR + 0x20)
519 #define HR_UART4_RX_WIN (HR_UART4_BASE_ADDR + 0x30)
520
521 /*
522 * Line Control Register bits definition
523 * ULCON0 ULCON1 Register
524 */
525 /* bit 0-1 : Word length */
526 #define ULCON_WL5 0x00
527 #define ULCON_WL6 0x01
528 #define ULCON_WL7 0x02
529 #define ULCON_WL8 0x03
530 #define ULCON_WL_MASK 0x03
531 /* bit 2 : Number of stop bits */
532 #define ULCON_STOP_2 0x04 /* 2 stop bit */
533 /* bit 3-4 : Parity mode */
534 #define ULCON_PMD_MASK 0x18
535 #define ULCON_PMD_EN 0x08 /* no parity */
536 #define ULCON_PMD_ODD 0x18 /* odd parity */
537 #define ULCON_PMD_EVEN 0x08 /* even parity */
538 /* bit 6 uart tx enable */
539 #define ULCON_TX_EN 0x40
540 #define ULCON_RX_EN 0x80
541 /* bit 6 : Infra-red mode */
542 #define ULCON_INFRA_RED 0x80
543
544 /*
545 * auto flow control register bits definition
546 */
547 #define UFC_ENABLE 0x01
548 #define UFC_SW_RTS_SET 0x02
549 #define UFC_RTS_TRIGGER_LVL_4_BYTE (0<<2)
550 #define UFC_RTS_TRIGGER_LVL_8_BYTE (1<<2)
551 #define UFC_RTS_TRIGGER_LVL_12_BYTE (2<<2)
552 #define UFC_RTS_TRIGGER_LVL_16_BYTE (3<<2)
553 #define UFC_RTS_TRIGGER_LVL_20_BYTE (4<<2)
554 #define UFC_RTS_TRIGGER_LVL_24_BYTE (5<<2)
555 #define UFC_RTS_TRIGGER_LVL_28_BYTE (6<<2)
556 #define UFC_RTS_TRIGGER_LVL_31_BYTE (7<<2)
557
558 #define UFC_TX_FIFO_RESET 0x01
559 #define UFC_RX_FIFO_RESET 0x02
560 #define UFC_TX_FIFO_LVL_ZERO (0<<2)
561 #define UFC_TX_FIFO_LVL_4_BYTE (1<<2)
562 #define UFC_TX_FIFO_LVL_8_BYTE (2<<2)
563 #define UFC_TX_FIFO_LVL_16_BYTE (3<<2)
564 #define UFC_RX_FIFO_LVL_ZERO (0<<4)
565 #define UFC_RX_FIFO_LVL_4_BYTE (1<<4)
566 #define UFC_RX_FIFO_LVL_8_BYTE (2<<4)
567 #define UFC_RX_FIFO_LVL_16_BYTE (3<<4)
568
569 /* dma control */
570 #define UDMA_RX_FIFO_TIMEOUT (1<<2)
571 #define UDMA_RX_FIFO_TIMEOUT_SHIFT (3)
572
573 /*
574 * uart interrupt source register bits definition
575 */
576 #define UIS_TX_FIFO_EMPTY (1UL<<0)
577 #define UIS_TX_FIFO (1UL<<1)
578 #define UIS_RX_FIFO (1UL<<2)
579 #define UIS_RX_FIFO_TIMEOUT (1UL<<3)
580 #define UIS_CTS_CHNG (1UL<<4)
581 #define UIS_BREAK (1UL<<5)
582 #define UIS_FRM_ERR (1UL<<6)
583 #define UIS_PARITY_ERR (1UL<<7)
584 #define UIS_OVERRUN (1UL<<8)
585
586 /*
587 * fifo status register bits definition
588 */
589 /* bit 0-5 : tx fifo count */
590 #define UFS_TX_FIFO_CNT_MASK 0x3F
591 /* bit 6-11 : rx fifo count */
592 #define UFS_RX_FIFO_CNT_MASK 0x3C0
593 #define UFS_CST_STS (1UL<<12)
594
595 /***************************************************************
596 * GPIO Reg
597 ***************************************************************/
598 #define HR_GPIO_BASE_ADDR (HR_APB_BASE_ADDR + 0x1200)
599 #define HR_GPIO_DATA (HR_GPIO_BASE_ADDR + 0x0)
600 #define HR_GPIO_DATA_EN (HR_GPIO_BASE_ADDR + 0x04)
601 #define HR_GPIO_DIR (HR_GPIO_BASE_ADDR + 0x08)
602 #define HR_GPIO_PULLUP_EN (HR_GPIO_BASE_ADDR + 0x0C)
603 #define HR_GPIO_AF_SEL (HR_GPIO_BASE_ADDR + 0x10)
604 #define HR_GPIO_AF_S1 (HR_GPIO_BASE_ADDR + 0x14)
605 #define HR_GPIO_AF_S0 (HR_GPIO_BASE_ADDR + 0x18)
606 #define HR_GPIO_PULLDOWN_EN (HR_GPIO_BASE_ADDR + 0x1C)
607 #define HR_GPIO_IS (HR_GPIO_BASE_ADDR + 0x20)
608 #define HR_GPIO_IBE (HR_GPIO_BASE_ADDR + 0x24)
609 #define HR_GPIO_IEV (HR_GPIO_BASE_ADDR + 0x28)
610 #define HR_GPIO_IE (HR_GPIO_BASE_ADDR + 0x2c)
611 #define HR_GPIO_RIS (HR_GPIO_BASE_ADDR + 0x30)
612 #define HR_GPIO_MIS (HR_GPIO_BASE_ADDR + 0x34)
613 #define HR_GPIO_IC (HR_GPIO_BASE_ADDR + 0x38)
614
615 #define HR_GPIOA_BASE_ADDR (HR_APB_BASE_ADDR + 0x1200)
616 #define HR_GPIOA_DATA (HR_GPIOA_BASE_ADDR + 0x0)
617 #define HR_GPIOA_DATA_EN (HR_GPIOA_BASE_ADDR + 0x04)
618 #define HR_GPIOA_DATA_DIR (HR_GPIOA_BASE_ADDR + 0x08)
619 #define HR_GPIOA_DATA_PULLEN (HR_GPIOA_BASE_ADDR + 0x0c)
620 #define HR_GPIOA_AFSEL (HR_GPIOA_BASE_ADDR + 0x10)
621 #define HR_GPIOA_AFS1 (HR_GPIOA_BASE_ADDR + 0x14)
622 #define HR_GPIOA_AFS0 (HR_GPIOA_BASE_ADDR + 0x18)
623 #define HR_GPIOA_IS (HR_GPIOA_BASE_ADDR + 0x20)
624 #define HR_GPIOA_IBE (HR_GPIOA_BASE_ADDR + 0x24)
625 #define HR_GPIOA_IEV (HR_GPIOA_BASE_ADDR + 0x28)
626 #define HR_GPIOA_IE (HR_GPIOA_BASE_ADDR + 0x2C)
627 #define HR_GPIOA_RIS (HR_GPIOA_BASE_ADDR + 0x30)
628 #define HR_GPIOA_MIS (HR_GPIOA_BASE_ADDR + 0x34)
629 #define HR_GPIOA_IC (HR_GPIOA_BASE_ADDR + 0x38)
630
631 #define HR_GPIOB_BASE_ADDR (HR_APB_BASE_ADDR + 0x1400)
632 #define HR_GPIOB_DATA (HR_GPIOB_BASE_ADDR + 0x0)
633 #define HR_GPIOB_DATA_EN (HR_GPIOB_BASE_ADDR + 0x04)
634 #define HR_GPIOB_DATA_DIR (HR_GPIOB_BASE_ADDR + 0x08)
635 #define HR_GPIOB_DATA_PULLEN (HR_GPIOB_BASE_ADDR + 0x0c)
636 #define HR_GPIOB_AFSEL (HR_GPIOB_BASE_ADDR + 0x10)
637 #define HR_GPIOB_AFS1 (HR_GPIOB_BASE_ADDR + 0x14)
638 #define HR_GPIOB_AFS0 (HR_GPIOB_BASE_ADDR + 0x18)
639 #define HR_GPIOB_IS (HR_GPIOB_BASE_ADDR + 0x20)
640 #define HR_GPIOB_IBE (HR_GPIOB_BASE_ADDR + 0x24)
641 #define HR_GPIOB_IEV (HR_GPIOB_BASE_ADDR + 0x28)
642 #define HR_GPIOB_IE (HR_GPIOB_BASE_ADDR + 0x2C)
643 #define HR_GPIOB_RIS (HR_GPIOB_BASE_ADDR + 0x30)
644 #define HR_GPIOB_MIS (HR_GPIOB_BASE_ADDR + 0x34)
645 #define HR_GPIOB_IC (HR_GPIOB_BASE_ADDR + 0x38)
646
647 #define IO_PA_BASE_ADDR (HR_APB_BASE_ADDR + 0x1200)
648 #define IO_PA_DATA (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x0))
649 #define IO_PA_EN (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x4))
650 #define IO_PA_DIR (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x8))
651 #define IO_PA_REN (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0xC))
652 #define IO_PA_AFSEL (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x10))
653 #define IO_PA_AFS1 (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x14))
654 #define IO_PA_AFS0 (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x18))
655
656 #define IO_PB_BASE_ADDR (HR_APB_BASE_ADDR + 0x1400)
657 #define IO_PB_DATA (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0x0))
658 #define IO_PB_EN (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0x4))
659 #define IO_PB_DIR (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0x8))
660 #define IO_PB_REN (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0xC))
661 #define IO_PB_AFSEL (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0x10))
662 #define IO_PB_AFS1 (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0x14))
663 #define IO_PB_AFS0 (*(volatile unsigned int*)(IO_PB_BASE_ADDR + 0x18))
664
665 /***************************************************************
666 * TIMER Reg
667 ***************************************************************/
668 #define HR_TIMER_BASE_ADDR (HR_APB_BASE_ADDR + 0x1800)
669 #define HR_TIMER_CFG (HR_TIMER_BASE_ADDR + 0x0)
670 #define HR_TIMER0_5_CSR (HR_TIMER_BASE_ADDR + 0x04)
671 #define HR_TIMER0_PRD (HR_TIMER_BASE_ADDR + 0x08)
672 #define HR_TIMER1_PRD (HR_TIMER_BASE_ADDR + 0x0C)
673 #define HR_TIMER2_PRD (HR_TIMER_BASE_ADDR + 0x10)
674 #define HR_TIMER3_PRD (HR_TIMER_BASE_ADDR + 0x14)
675 #define HR_TIMER4_PRD (HR_TIMER_BASE_ADDR + 0x18)
676 #define HR_TIMER5_PRD (HR_TIMER_BASE_ADDR + 0x1C)
677 #define HR_TIMER0_CNT (HR_TIMER_BASE_ADDR + 0x20)
678 #define HR_TIMER1_CNT (HR_TIMER_BASE_ADDR + 0x24)
679 #define HR_TIMER2_CNT (HR_TIMER_BASE_ADDR + 0x28)
680 #define HR_TIMER3_CNT (HR_TIMER_BASE_ADDR + 0x2C)
681 #define HR_TIMER4_CNT (HR_TIMER_BASE_ADDR + 0x30)
682 #define HR_TIMER5_CNT (HR_TIMER_BASE_ADDR + 0x34)
683
684 /* timer csr bits defintion */
685 #define TLS_TIMER_MS_UNIT(n) (1UL<<(0+5*(n)))
686 #define TLS_TIMER_ONE_TIME(n) (1UL<<(1+5*(n)))
687 #define TLS_TIMER_EN(n) (1UL<<(2+5*(n)))
688 #define TLS_TIMER_INT_EN(n) (1UL<<(3+5*(n)))
689 #define TLS_TIMER_INT_CLR(n) (1UL<<(4+5*(n)))
690
691 /***************************************************************
692 * WATCH DOG Reg
693 ***************************************************************/
694 #define HR_WDG_BASE_ADDR (HR_APB_BASE_ADDR + 0x1600)
695 #define HR_WDG_LOAD_VALUE (HR_WDG_BASE_ADDR + 0x00)
696 #define HR_WDG_CUR_VALUE (HR_WDG_BASE_ADDR + 0x04)
697 #define HR_WDG_CTRL (HR_WDG_BASE_ADDR + 0x08)
698 #define HR_WDG_INT_CLR (HR_WDG_BASE_ADDR + 0x0C)
699 #define HR_WDG_INT_SRC (HR_WDG_BASE_ADDR + 0x10)
700 #define HR_WDG_INT_MIS (HR_WDG_BASE_ADDR + 0x14)
701 #define HR_WDG_LOCK (HR_WDG_BASE_ADDR + 0x40)
702
703 /** bit field of the lcd gate control in CLK gating register */
704 #define HR_CLK_LCD_GATE_Pos (14)
705
706 /***********************************************************//**
707 * LCD Reg
708 ***************************************************************/
709
710 #define HR_LCD_REG_BASE (HR_APB_BASE_ADDR + 0x1C00) // (0x4001 1C00)
711 #define HR_LCD_CR (HR_LCD_REG_BASE+0x000)
712 #define HR_LCD_FRAME_CNT (HR_LCD_REG_BASE+0x004)
713 #define HR_LCD_COM0_SEG (HR_LCD_REG_BASE+0x008)
714 #define HR_LCD_COM1_SEG (HR_LCD_REG_BASE+0x00C)
715 #define HR_LCD_COM2_SEG (HR_LCD_REG_BASE+0x010)
716 #define HR_LCD_COM3_SEG (HR_LCD_REG_BASE+0x014)
717 #define HR_LCD_COM4_SEG (HR_LCD_REG_BASE+0x018)
718 #define HR_LCD_COM5_SEG (HR_LCD_REG_BASE+0x01C)
719 #define HR_LCD_COM6_SEG (HR_LCD_REG_BASE+0x020)
720 #define HR_LCD_COM7_SEG (HR_LCD_REG_BASE+0x024)
721 #define HR_LCD_COM_EN (HR_LCD_REG_BASE+0x028)
722 #define HR_LCD_SEG_EN (HR_LCD_REG_BASE+0x02C)
723
724 #define LCD_CR_EN_Pos (8)
725 #define LCD_CR_PD_Pos (9)
726
727 #define LCD_VDD_ON (1UL<<9)
728 #define LCD_VDD_OFF (0UL<<9)
729 #define LCD_EN (1UL<<8)
730
731 #define LCD_BIAS_MASK (3UL<<6)
732 #define LCD_BIAS_MASK_Pos (6)
733 #define LCD_BIAS_ONEFOURTH (0UL<<6)
734 #define LCD_BIAS_ONEHALF (1UL<<6)
735 #define LCD_BIAS_ONETHIRD (2UL<<6)
736 #define LCD_BIAS_STATIC (3UL<<6)
737
738 #define LCD_VLCD_MASK (7UL<<3)
739 #define LCD_VLCD_MASK_Pos (3)
740 #define LCD_VLCD_27 (0UL<<3)
741 #define LCD_VLCD_29 (1UL<<3)
742 #define LCD_VLCD_31 (2UL<<3)
743 #define LCD_VLCD_33 (3UL<<3)
744
745 #define LCD_DUTY_MASK (7UL<<0)
746 #define LCD_DUTY_MASK_Pos (0)
747 #define LCD_DUTY_STATIC (0UL<<0)
748 #define LCD_DUTY_ONEHALF (1UL<<0)
749 #define LCD_DUTY_ONETHIRD (2UL<<0)
750 #define LCD_DUTY_ONEFOURTH (3UL<<0)
751 #define LCD_DUTY_ONEFIFTH (4UL<<0)
752 #define LCD_DUTY_ONESIXTH (5UL<<0)
753 #define LCD_DUTY_ONESEVENTH (6UL<<0)
754 #define LCD_DUTY_ONEEIGHTH (7UL<<0)
755
756 /***********************************************************//**
757 * I2S Reg
758 ***************************************************************/
759 #define HR_CLK_I2S_GATE_Pos (10)
760
761 #define HR_I2S_REG_BASE (HR_APB_BASE_ADDR+0x2000)
762 #define HR_I2S_CTRL (HR_I2S_REG_BASE+0x000)
763 #define HR_I2S_INT_MASK (HR_I2S_REG_BASE+0x004)
764 #define HR_I2S_INT_SRC (HR_I2S_REG_BASE+0x008)
765 #define HR_I2S_STATUS (HR_I2S_REG_BASE+0x00C)
766 #define HR_I2S_TX (HR_I2S_REG_BASE+0x010)
767 #define HR_I2S_RX (HR_I2S_REG_BASE+0x014)
768
769 /*****************************************************************/
770 /* APB2SPI modem spi access register definition(BT) */
771 /*****************************************************************/
772 #define APB2SPI_REG_BASE (HR_APB_BASE_ADDR+ 0x2200)
773 #define APB2SPI_REG_CFG (APB2SPI_REG_BASE+ 0x0000)
774 #define APB2SPI_REG_PS_CR (APB2SPI_REG_BASE+ 0x0004)
775 #define APB2SPI_REG_TX_DATA (APB2SPI_REG_BASE+ 0x0008)
776 #define APB2SPI_REG_RX_DATA (APB2SPI_REG_BASE+ 0x000C)
777
778 /******************************************************************************/
779 /* */
780 /* PWM */
781 /* */
782 /******************************************************************************/
783 #define HR_PWM_REG_BASE (HR_APB_BASE_ADDR+0x1E00)
784 #define HR_PWM_CLKDIV01 (HR_PWM_REG_BASE+0x0000)
785 #define HR_PWM_CLKDIV23 (HR_PWM_REG_BASE+0x0004)
786 #define HR_PWM_CTL (HR_PWM_REG_BASE+0x0008)
787 #define HR_PWM_PERIOD (HR_PWM_REG_BASE+0x000C)
788 #define HR_PWM_PNUM (HR_PWM_REG_BASE+0x0010)
789 #define HR_PWM_CMPDAT (HR_PWM_REG_BASE+0x0014)
790 #define HR_PWM_DTCTL (HR_PWM_REG_BASE+0x0018)
791 #define HR_PWM_INTEN (HR_PWM_REG_BASE+0x001C)
792 #define HR_PWM_INTSTS (HR_PWM_REG_BASE+0x0020)
793 #define HR_PWM_CAPDAT (HR_PWM_REG_BASE+0x0024)
794 #define HR_PWM_BRKCTL (HR_PWM_REG_BASE+0x0028)
795 #define HR_PWM_CH4_REG1 (HR_PWM_REG_BASE+0x002C)
796 #define HR_PWM_CH4_REG2 (HR_PWM_REG_BASE+0x0030)
797 #define HR_PWM_CAP2DAT (HR_PWM_REG_BASE+0x0034)
798 #define HR_PWM_CAP2CTL (HR_PWM_REG_BASE+0x0038)
799
800 /******************************************************************************/
801 /* */
802 /* TOUCH SENSOR */
803 /* */
804 /******************************************************************************/
805 #define HR_TC_REG_BASE (HR_APB_BASE_ADDR+0x2400)
806
807 #define HR_TC_CONFIG (HR_TC_REG_BASE+0x0000)
808 #define SCAN_PERID_SHIFT_BIT (26)
809 #define CAPDET_CNT_SHIFT_BIT (20)
810 #define TOUCH_SENSOR_SEL_SHIFT_BIT (4)
811 #define TOUCH_SENSOR_EN_BIT (0)
812
813 #define HR_TC1_TRESHOLD_REG (HR_TC_REG_BASE+0x0004)
814 #define HR_TC1_COUNT_REG (HR_TC_REG_BASE+0x0004)
815
816 #define HR_TC2_TRESHOLD_REG (HR_TC_REG_BASE+0x0008)
817 #define HR_TC2_COUNT_REG (HR_TC_REG_BASE+0x0008)
818
819 #define HR_TC3_TRESHOLD_REG (HR_TC_REG_BASE+0x000C)
820 #define HR_TC3_COUNT_REG (HR_TC_REG_BASE+0x000C)
821
822 #define HR_TC4_TRESHOLD_REG (HR_TC_REG_BASE+0x0010)
823 #define HR_TC4_COUNT_REG (HR_TC_REG_BASE+0x0010)
824
825 #define HR_TC5_TRESHOLD_REG (HR_TC_REG_BASE+0x0014)
826 #define HR_TC5_COUNT_REG (HR_TC_REG_BASE+0x0014)
827
828 #define HR_TC6_TRESHOLD_REG (HR_TC_REG_BASE+0x0018)
829 #define HR_TC6_COUNT_REG (HR_TC_REG_BASE+0x0018)
830
831 #define HR_TC7_TRESHOLD_REG (HR_TC_REG_BASE+0x001C)
832 #define HR_TC7_COUNT_REG (HR_TC_REG_BASE+0x001C)
833
834 #define HR_TC8_TRESHOLD_REG (HR_TC_REG_BASE+0x0020)
835 #define HR_TC8_COUNT_REG (HR_TC_REG_BASE+0x0020)
836
837 #define HR_TC9_TRESHOLD_REG (HR_TC_REG_BASE+0x0024)
838 #define HR_TC9_COUNT_REG (HR_TC_REG_BASE+0x0024)
839
840 #define HR_TC10_TRESHOLD_REG (HR_TC_REG_BASE+0x0028)
841 #define HR_TC10_COUNT_REG (HR_TC_REG_BASE+0x0028)
842
843 #define HR_TC11_TRESHOLD_REG (HR_TC_REG_BASE+0x002C)
844 #define HR_TC11_COUNT_REG (HR_TC_REG_BASE+0x002C)
845
846 #define HR_TC12_TRESHOLD_REG (HR_TC_REG_BASE+0x0030)
847 #define HR_TC12_COUNT_REG (HR_TC_REG_BASE+0x0030)
848
849 #define HR_TC13_TRESHOLD_REG (HR_TC_REG_BASE+0x0034)
850 #define HR_TC13_COUNT_REG (HR_TC_REG_BASE+0x0034)
851
852 #define HR_TC14_TRESHOLD_REG (HR_TC_REG_BASE+0x0038)
853 #define HR_TC14_COUNT_REG (HR_TC_REG_BASE+0x0038)
854
855 #define HR_TC15_TRESHOLD_REG (HR_TC_REG_BASE+0x003C)
856 #define HR_TC15_COUNT_REG (HR_TC_REG_BASE+0x003C)
857
858 #define HR_TC16_TRESHOLD_REG (HR_TC_REG_BASE+0x0040)
859 #define HR_TC16_COUNT_REG (HR_TC_REG_BASE+0x0040)
860
861 #define HR_TC_INT_EN (HR_TC_REG_BASE+0x0044) /* bit 31:16 */
862 #define HR_TC_INT_STATUS (HR_TC_REG_BASE+0x0044) /* bit 15:0 */
863
864 /**
865 * @defgroup System_APIs System APIs
866 * @brief System APIs
867 */
868
869 /**
870 * @addtogroup System_APIs
871 * @{
872 */
873
874 /**
875 * @defgroup REG_APIs REG APIs
876 * @brief Register operate APIs
877 */
878
879 /**
880 * @addtogroup REG_APIs
881 * @{
882 */
883
884 /**
885 * @brief This function is used to write value to register or memory
886 *
887 * @param[in] reg address to be written
888 * @param[in] val value to write
889 *
890 * @return None
891 *
892 * @note None
893 */
tls_reg_write32(unsigned int reg,unsigned int val)894 static __inline void tls_reg_write32(unsigned int reg, unsigned int val)
895 {
896 *(TLS_REG *)reg = val;
897 }
898
899 /**
900 * @brief This function is used to read value from register or memory
901 *
902 * @param[in] reg address to read
903 *
904 * @retval val read from register or memory
905 *
906 * @note None
907 */
tls_reg_read32(unsigned int reg)908 static __inline unsigned int tls_reg_read32(unsigned int reg)
909 {
910 unsigned int val = *(TLS_REG *)reg;
911 return val;
912 }
913
914 /**
915 * @brief This function is used to write specified bit through
916 bit-band alias region
917 *
918 * @param[in] addr 32-bit aligned byte address where the bit exists.
919 * @param[in] bit Bit position.
920 * @param[in] val The value that the bit is set to, 0 or 1.
921 *
922 * @return None
923 *
924 * @note Only when bit-band mechnism is supported, you can use it
925 */
tls_bitband_write(volatile unsigned int addr,unsigned int bit,unsigned int val)926 static __inline void tls_bitband_write(volatile unsigned int addr, unsigned int bit, unsigned int val)
927 {
928 unsigned int temp;
929
930 temp = (M32(addr) & ~(1 << bit)) | (val << bit);
931
932 *((volatile unsigned int *)addr) = temp;
933 }
934
935 /**
936 * @brief This function is used to read a single bit from address
937 by bit-band alias region
938 *
939 * @param[in] addr 32-bit aligned byte address where the bit exists
940 * @param[in] bit Bit position
941 *
942 * @retval The value of the requested bit
943 *
944 * @note Only when bit-band mechnism is supported, you can use it
945 */
tls_bitband_read(volatile unsigned int addr,unsigned int bit)946 static __inline unsigned int tls_bitband_read(volatile unsigned int addr, unsigned int bit)
947 {
948 unsigned int temp;
949
950 temp = (M32(addr) >> bit) & 0x1;
951
952 return *((volatile unsigned int *)temp);
953 }
954
955 /**
956 * @}
957 */
958
959 /**
960 * @}
961 */
962
963 #endif /* WM_REGS_H */