Searched refs:HR_PWM_DTCTL (Results 1 – 2 of 2) sorted by relevance
391 temp = tls_reg_read32(HR_PWM_DTCTL) & ~0x00030000; in tls_pwm_deadzone_config()393 tls_reg_write32(HR_PWM_DTCTL, temp); /* dead zone clock divider */ in tls_pwm_deadzone_config()396 temp = tls_reg_read32(HR_PWM_DTCTL) & ~0x000000FF; in tls_pwm_deadzone_config()398 tls_reg_write32(HR_PWM_DTCTL, temp); /* the number of the counting clock cycle */ in tls_pwm_deadzone_config()400 …tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) | BIT(20)); /* whether enalbe the deat … in tls_pwm_deadzone_config()402 temp = tls_reg_read32(HR_PWM_DTCTL) & ~0x0000FF00; in tls_pwm_deadzone_config()404 tls_reg_write32(HR_PWM_DTCTL, temp); /* the number of the counting clock cycle */ in tls_pwm_deadzone_config()406 …tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) | BIT(21)); /* whether enalbe the deat … in tls_pwm_deadzone_config()410 …tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(20))); /* whether enalbe the deat… in tls_pwm_deadzone_config()412 …tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(21))); /* whether enalbe the deat… in tls_pwm_deadzone_config()
790 #define HR_PWM_DTCTL (HR_PWM_REG_BASE+0x0018) macro