Searched refs:INTENABLE (Results 1 – 5 of 5) sorted by relevance
| /device/soc/esp/esp32/components/xtensa/ |
| D | xtensa_intr_asm.S | 149 xsr a3, INTENABLE /* Disables all interrupts */
156 wsr a5, INTENABLE /* Reenable interrupts */
160 xsr a3, INTENABLE /* Disables all interrupts */
163 wsr a2, INTENABLE /* Re-enable ints */
198 xsr a3, INTENABLE /* Disables all interrupts */
206 wsr a5, INTENABLE /* Reenable interrupts */
210 xsr a4, INTENABLE /* Disables all interrupts */
214 wsr a3, INTENABLE /* Re-enable ints */
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| /device/soc/esp/esp32/components/xtensa/esp32/include/xtensa/config/ |
| D | specreg.h | 85 #define INTENABLE 228 macro
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| /device/soc/esp/esp32/components/esp_system/port/soc/esp32/ |
| D | dport_panic_highint_hdl.S | 117 rsr a0, INTENABLE
120 wsr a0, INTENABLE
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| /device/soc/esp/esp32/components/osal/port/xtensa/ |
| D | xtensa_vectors.S | 211 rsr a2, INTENABLE
285 rsr a3, INTENABLE
287 wsr a3, INTENABLE
357 wsr a4, INTENABLE /* update INTENABLE */
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| D | xtensa_context.S | 298 wsr a4, INTENABLE /* update INTENABLE */
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