1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2017 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __PHYDMPREDEFINE_H__ 27 #define __PHYDMPREDEFINE_H__ 28 29 /**************************************************************** 30 * 1 ============================================================ 31 * 1 Definition 32 * 1 ============================================================ 33 ***************************************************************/ 34 35 #define PHYDM_CODE_BASE "PHYDM_V051_GIT" 36 #define PHYDM_RELEASE_DATE "20210415.0" 37 38 /*PHYDM API status*/ 39 #define PHYDM_SET_FAIL 0 40 #define PHYDM_SET_SUCCESS 1 41 #define PHYDM_SET_NO_NEED 3 42 43 /*PHYDM Set/Revert*/ 44 #define PHYDM_SET 1 45 #define PHYDM_REVERT 2 46 47 /* @Max path of IC */ 48 /*N-IC*/ 49 #define MAX_PATH_NUM_8188E 1 50 #define MAX_PATH_NUM_8188F 1 51 #define MAX_PATH_NUM_8710B 1 52 #define MAX_PATH_NUM_8723B 1 53 #define MAX_PATH_NUM_8723D 1 54 #define MAX_PATH_NUM_8703B 1 55 #define MAX_PATH_NUM_8192E 2 56 #define MAX_PATH_NUM_8192F 2 57 #define MAX_PATH_NUM_8197F 2 58 #define MAX_PATH_NUM_8198F 4 59 #define MAX_PATH_NUM_8197G 2 60 #define MAX_PATH_NUM_8721D 1 61 #define MAX_PATH_NUM_8710C 1 62 #define MAX_PATH_NUM_8723F 2 63 64 /*@AC-IC*/ 65 #define MAX_PATH_NUM_8821A 1 66 #define MAX_PATH_NUM_8881A 1 67 #define MAX_PATH_NUM_8821C 1 68 #define MAX_PATH_NUM_8195B 1 69 #define MAX_PATH_NUM_8812A 2 70 #define MAX_PATH_NUM_8822B 2 71 #define MAX_PATH_NUM_8822C 2 72 #define MAX_PATH_NUM_8814A 4 73 #define MAX_PATH_NUM_8814B 4 74 #define MAX_PATH_NUM_8814C 4 75 #define MAX_PATH_NUM_8195B 1 76 #define MAX_PATH_NUM_8812F 2 77 78 /* @Max RF path */ 79 #define PHYDM_MAX_RF_PATH_N 2 /*@For old N-series IC*/ 80 #define PHYDM_MAX_RF_PATH 4 81 82 /* number of entry */ 83 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 84 #ifdef DM_ODM_CE_MAC80211 85 /* @defined in wifi.h (32+1) */ 86 #else 87 #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* @Max size of asoc_entry[].*/ 88 #endif 89 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 90 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP)) 91 #define ASSOCIATE_ENTRY_NUM NUM_STAT 92 #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM + 1) 93 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT)) 94 #ifdef CONFIG_CONCURRENT_MODE 95 #define ASSOCIATE_ENTRY_NUM NUM_STA + 2 /*@2 is for station mod*/ 96 #else 97 #define ASSOCIATE_ENTRY_NUM NUM_STA /*@8 is for max size of asoc_entry[].*/ 98 #endif 99 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 100 #else 101 #define ODM_ASSOCIATE_ENTRY_NUM (((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1) 102 #endif 103 104 /* @-----MGN rate--------------------------------- */ 105 106 enum PDM_RATE_TYPE { 107 PDM_1SS = 1, /*VHT/HT 1SS*/ 108 PDM_2SS = 2, /*VHT/HT 2SS*/ 109 PDM_3SS = 3, /*VHT/HT 3SS*/ 110 PDM_4SS = 4, /*VHT/HT 4SS*/ 111 PDM_CCK = 11, /*@B*/ 112 PDM_OFDM = 12 /*@G*/ 113 }; 114 115 enum ODM_MGN_RATE { 116 ODM_MGN_1M = 0x02, 117 ODM_MGN_2M = 0x04, 118 ODM_MGN_5_5M = 0x0B, 119 ODM_MGN_6M = 0x0C, 120 ODM_MGN_9M = 0x12, 121 ODM_MGN_11M = 0x16, 122 ODM_MGN_12M = 0x18, 123 ODM_MGN_18M = 0x24, 124 ODM_MGN_24M = 0x30, 125 ODM_MGN_36M = 0x48, 126 ODM_MGN_48M = 0x60, 127 ODM_MGN_54M = 0x6C, 128 ODM_MGN_MCS32 = 0x7F, 129 ODM_MGN_MCS0 = 0x80, 130 ODM_MGN_MCS1, 131 ODM_MGN_MCS2, 132 ODM_MGN_MCS3, 133 ODM_MGN_MCS4, 134 ODM_MGN_MCS5, 135 ODM_MGN_MCS6, 136 ODM_MGN_MCS7 = 0x87, 137 ODM_MGN_MCS8, 138 ODM_MGN_MCS9, 139 ODM_MGN_MCS10, 140 ODM_MGN_MCS11, 141 ODM_MGN_MCS12, 142 ODM_MGN_MCS13, 143 ODM_MGN_MCS14, 144 ODM_MGN_MCS15, 145 ODM_MGN_MCS16 = 0x90, 146 ODM_MGN_MCS17, 147 ODM_MGN_MCS18, 148 ODM_MGN_MCS19, 149 ODM_MGN_MCS20, 150 ODM_MGN_MCS21, 151 ODM_MGN_MCS22, 152 ODM_MGN_MCS23, 153 ODM_MGN_MCS24 = 0x98, 154 ODM_MGN_MCS25, 155 ODM_MGN_MCS26, 156 ODM_MGN_MCS27, 157 ODM_MGN_MCS28, 158 ODM_MGN_MCS29, 159 ODM_MGN_MCS30, 160 ODM_MGN_MCS31, 161 ODM_MGN_VHT1SS_MCS0 = 0xa0, 162 ODM_MGN_VHT1SS_MCS1, 163 ODM_MGN_VHT1SS_MCS2, 164 ODM_MGN_VHT1SS_MCS3, 165 ODM_MGN_VHT1SS_MCS4, 166 ODM_MGN_VHT1SS_MCS5, 167 ODM_MGN_VHT1SS_MCS6, 168 ODM_MGN_VHT1SS_MCS7, 169 ODM_MGN_VHT1SS_MCS8, 170 ODM_MGN_VHT1SS_MCS9, 171 ODM_MGN_VHT2SS_MCS0 = 0xaa, 172 ODM_MGN_VHT2SS_MCS1 = 0xab, 173 ODM_MGN_VHT2SS_MCS2, 174 ODM_MGN_VHT2SS_MCS3, 175 ODM_MGN_VHT2SS_MCS4, 176 ODM_MGN_VHT2SS_MCS5 = 0xaf, 177 ODM_MGN_VHT2SS_MCS6 = 0xb0, 178 ODM_MGN_VHT2SS_MCS7, 179 ODM_MGN_VHT2SS_MCS8, 180 ODM_MGN_VHT2SS_MCS9 = 0xb3, 181 ODM_MGN_VHT3SS_MCS0 = 0xb4, 182 ODM_MGN_VHT3SS_MCS1, 183 ODM_MGN_VHT3SS_MCS2, 184 ODM_MGN_VHT3SS_MCS3, 185 ODM_MGN_VHT3SS_MCS4, 186 ODM_MGN_VHT3SS_MCS5, 187 ODM_MGN_VHT3SS_MCS6, 188 ODM_MGN_VHT3SS_MCS7 = 0xbb, 189 ODM_MGN_VHT3SS_MCS8 = 0xbc, 190 ODM_MGN_VHT3SS_MCS9 = 0xbd, 191 ODM_MGN_VHT4SS_MCS0 = 0xbe, 192 ODM_MGN_VHT4SS_MCS1, 193 ODM_MGN_VHT4SS_MCS2, 194 ODM_MGN_VHT4SS_MCS3, 195 ODM_MGN_VHT4SS_MCS4, 196 ODM_MGN_VHT4SS_MCS5, 197 ODM_MGN_VHT4SS_MCS6, 198 ODM_MGN_VHT4SS_MCS7, 199 ODM_MGN_VHT4SS_MCS8, 200 ODM_MGN_VHT4SS_MCS9 = 0xc7, 201 ODM_MGN_UNKNOWN 202 }; 203 204 #define ODM_MGN_MCS0_SG 0xc0 205 #define ODM_MGN_MCS1_SG 0xc1 206 #define ODM_MGN_MCS2_SG 0xc2 207 #define ODM_MGN_MCS3_SG 0xc3 208 #define ODM_MGN_MCS4_SG 0xc4 209 #define ODM_MGN_MCS5_SG 0xc5 210 #define ODM_MGN_MCS6_SG 0xc6 211 #define ODM_MGN_MCS7_SG 0xc7 212 #define ODM_MGN_MCS8_SG 0xc8 213 #define ODM_MGN_MCS9_SG 0xc9 214 #define ODM_MGN_MCS10_SG 0xca 215 #define ODM_MGN_MCS11_SG 0xcb 216 #define ODM_MGN_MCS12_SG 0xcc 217 #define ODM_MGN_MCS13_SG 0xcd 218 #define ODM_MGN_MCS14_SG 0xce 219 #define ODM_MGN_MCS15_SG 0xcf 220 221 /* @-----DESC rate--------------------------------- */ 222 223 #define ODM_RATEMCS15_SG 0x1c 224 #define ODM_RATEMCS32 0x20 225 226 enum phydm_ctrl_info_rate { 227 ODM_RATE1M = 0x00, 228 ODM_RATE2M = 0x01, 229 ODM_RATE5_5M = 0x02, 230 ODM_RATE11M = 0x03, 231 /* OFDM Rates, TxHT = 0 */ 232 ODM_RATE6M = 0x04, 233 ODM_RATE9M = 0x05, 234 ODM_RATE12M = 0x06, 235 ODM_RATE18M = 0x07, 236 ODM_RATE24M = 0x08, 237 ODM_RATE36M = 0x09, 238 ODM_RATE48M = 0x0A, 239 ODM_RATE54M = 0x0B, 240 /* @MCS Rates, TxHT = 1 */ 241 ODM_RATEMCS0 = 0x0C, 242 ODM_RATEMCS1 = 0x0D, 243 ODM_RATEMCS2 = 0x0E, 244 ODM_RATEMCS3 = 0x0F, 245 ODM_RATEMCS4 = 0x10, 246 ODM_RATEMCS5 = 0x11, 247 ODM_RATEMCS6 = 0x12, 248 ODM_RATEMCS7 = 0x13, 249 ODM_RATEMCS8 = 0x14, 250 ODM_RATEMCS9 = 0x15, 251 ODM_RATEMCS10 = 0x16, 252 ODM_RATEMCS11 = 0x17, 253 ODM_RATEMCS12 = 0x18, 254 ODM_RATEMCS13 = 0x19, 255 ODM_RATEMCS14 = 0x1A, 256 ODM_RATEMCS15 = 0x1B, 257 ODM_RATEMCS16 = 0x1C, 258 ODM_RATEMCS17 = 0x1D, 259 ODM_RATEMCS18 = 0x1E, 260 ODM_RATEMCS19 = 0x1F, 261 ODM_RATEMCS20 = 0x20, 262 ODM_RATEMCS21 = 0x21, 263 ODM_RATEMCS22 = 0x22, 264 ODM_RATEMCS23 = 0x23, 265 ODM_RATEMCS24 = 0x24, 266 ODM_RATEMCS25 = 0x25, 267 ODM_RATEMCS26 = 0x26, 268 ODM_RATEMCS27 = 0x27, 269 ODM_RATEMCS28 = 0x28, 270 ODM_RATEMCS29 = 0x29, 271 ODM_RATEMCS30 = 0x2A, 272 ODM_RATEMCS31 = 0x2B, 273 ODM_RATEVHTSS1MCS0 = 0x2C, 274 ODM_RATEVHTSS1MCS1 = 0x2D, 275 ODM_RATEVHTSS1MCS2 = 0x2E, 276 ODM_RATEVHTSS1MCS3 = 0x2F, 277 ODM_RATEVHTSS1MCS4 = 0x30, 278 ODM_RATEVHTSS1MCS5 = 0x31, 279 ODM_RATEVHTSS1MCS6 = 0x32, 280 ODM_RATEVHTSS1MCS7 = 0x33, 281 ODM_RATEVHTSS1MCS8 = 0x34, 282 ODM_RATEVHTSS1MCS9 = 0x35, 283 ODM_RATEVHTSS2MCS0 = 0x36, 284 ODM_RATEVHTSS2MCS1 = 0x37, 285 ODM_RATEVHTSS2MCS2 = 0x38, 286 ODM_RATEVHTSS2MCS3 = 0x39, 287 ODM_RATEVHTSS2MCS4 = 0x3A, 288 ODM_RATEVHTSS2MCS5 = 0x3B, 289 ODM_RATEVHTSS2MCS6 = 0x3C, 290 ODM_RATEVHTSS2MCS7 = 0x3D, 291 ODM_RATEVHTSS2MCS8 = 0x3E, 292 ODM_RATEVHTSS2MCS9 = 0x3F, 293 ODM_RATEVHTSS3MCS0 = 0x40, 294 ODM_RATEVHTSS3MCS1 = 0x41, 295 ODM_RATEVHTSS3MCS2 = 0x42, 296 ODM_RATEVHTSS3MCS3 = 0x43, 297 ODM_RATEVHTSS3MCS4 = 0x44, 298 ODM_RATEVHTSS3MCS5 = 0x45, 299 ODM_RATEVHTSS3MCS6 = 0x46, 300 ODM_RATEVHTSS3MCS7 = 0x47, 301 ODM_RATEVHTSS3MCS8 = 0x48, 302 ODM_RATEVHTSS3MCS9 = 0x49, 303 ODM_RATEVHTSS4MCS0 = 0x4A, 304 ODM_RATEVHTSS4MCS1 = 0x4B, 305 ODM_RATEVHTSS4MCS2 = 0x4C, 306 ODM_RATEVHTSS4MCS3 = 0x4D, 307 ODM_RATEVHTSS4MCS4 = 0x4E, 308 ODM_RATEVHTSS4MCS5 = 0x4F, 309 ODM_RATEVHTSS4MCS6 = 0x50, 310 ODM_RATEVHTSS4MCS7 = 0x51, 311 ODM_RATEVHTSS4MCS8 = 0x52, 312 ODM_RATEVHTSS4MCS9 = 0x53, 313 }; 314 315 enum phydm_legacy_spec_rate { 316 PHYDM_SPEC_RATE_6M = 0xb, 317 PHYDM_SPEC_RATE_9M = 0xf, 318 PHYDM_SPEC_RATE_12M = 0xa, 319 PHYDM_SPEC_RATE_18M = 0xe, 320 PHYDM_SPEC_RATE_24M = 0x9, 321 PHYDM_SPEC_RATE_36M = 0xd, 322 PHYDM_SPEC_RATE_48M = 0x8, 323 PHYDM_SPEC_RATE_54M = 0xc 324 }; 325 326 #define NUM_RATE_AC_4SS (ODM_RATEVHTSS4MCS9 + 1) 327 #define NUM_RATE_AC_3SS (ODM_RATEVHTSS3MCS9 + 1) 328 #define NUM_RATE_AC_2SS (ODM_RATEVHTSS2MCS9 + 1) 329 #define NUM_RATE_AC_1SS (ODM_RATEVHTSS1MCS9 + 1) 330 #define NUM_RATE_N_4SS (ODM_RATEMCS31 + 1) 331 #define NUM_RATE_N_3SS (ODM_RATEMCS23 + 1) 332 #define NUM_RATE_N_2SS (ODM_RATEMCS15 + 1) 333 #define NUM_RATE_N_1SS (ODM_RATEMCS7 + 1) 334 335 /*Define from larger rate size to small rate size, DO NOT change the position*/ 336 /*[AC-4SS]*/ 337 #if (RTL8814B_SUPPORT) 338 #define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS 339 /*[AC-3SS]*/ 340 #elif (RTL8814A_SUPPORT) 341 #define PHY_NUM_RATE_IDX NUM_RATE_AC_3SS 342 /*[AC-2SS]*/ 343 #elif (RTL8812A_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ 344 RTL8812F_SUPPORT) 345 #define PHY_NUM_RATE_IDX NUM_RATE_AC_2SS 346 /*[AC-1SS]*/ 347 #elif (RTL8881A_SUPPORT || RTL8821A_SUPPORT || RTL8821C_SUPPORT ||\ 348 RTL8195B_SUPPORT) 349 #define PHY_NUM_RATE_IDX NUM_RATE_AC_1SS 350 /*[N-4SS]*/ 351 #elif (RTL8198F_SUPPORT) 352 #define PHY_NUM_RATE_IDX NUM_RATE_N_4SS 353 /*[N-2SS]*/ 354 #elif (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT ||\ 355 RTL8197G_SUPPORT) 356 #define PHY_NUM_RATE_IDX NUM_RATE_N_2SS 357 /*[N-1SS]*/ 358 #elif (RTL8723B_SUPPORT || RTL8703B_SUPPORT || RTL8188E_SUPPORT || \ 359 RTL8188F_SUPPORT || RTL8723D_SUPPORT || RTL8195A_SUPPORT ||\ 360 RTL8710B_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT) 361 #define PHY_NUM_RATE_IDX NUM_RATE_N_1SS 362 #else 363 #define PHY_NUM_RATE_IDX NUM_RATE_AC_4SS 364 #endif 365 366 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) 367 #define CONFIG_SFW_SUPPORTED 368 #endif 369 370 /**************************************************************** 371 * 1 ============================================================ 372 * 1 enumeration 373 * 1 ============================================================ 374 ***************************************************************/ 375 376 /* ODM_CMNINFO_INTERFACE */ 377 enum odm_interface { 378 ODM_ITRF_PCIE = 0x1, 379 ODM_ITRF_USB = 0x2, 380 ODM_ITRF_SDIO = 0x4, 381 ODM_ITRF_ALL = 0x7, 382 }; 383 384 enum phydm_api_host { 385 RUN_IN_FW = 0, 386 RUN_IN_DRIVER = 1, 387 }; 388 389 /*@========[Run time IC flag] ===================================*/ 390 391 enum phydm_ic { 392 ODM_RTL8188E = BIT(0), 393 ODM_RTL8812 = BIT(1), 394 ODM_RTL8821 = BIT(2), 395 ODM_RTL8192E = BIT(3), 396 ODM_RTL8723B = BIT(4), 397 ODM_RTL8814A = BIT(5), 398 ODM_RTL8881A = BIT(6), 399 ODM_RTL8822B = BIT(7), 400 ODM_RTL8703B = BIT(8), 401 ODM_RTL8195A = BIT(9), 402 ODM_RTL8188F = BIT(10), 403 ODM_RTL8723D = BIT(11), 404 ODM_RTL8197F = BIT(12), 405 ODM_RTL8821C = BIT(13), 406 ODM_RTL8814B = BIT(14), 407 ODM_RTL8198F = BIT(15), 408 ODM_RTL8710B = BIT(16), 409 ODM_RTL8192F = BIT(17), 410 ODM_RTL8822C = BIT(18), 411 ODM_RTL8195B = BIT(19), 412 ODM_RTL8812F = BIT(20), 413 ODM_RTL8197G = BIT(21), 414 ODM_RTL8721D = BIT(22), 415 ODM_RTL8710C = BIT(23), 416 ODM_RTL8723F = BIT(24), 417 ODM_RTL8814C = BIT(25) 418 }; 419 420 #define ODM_IC_N_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\ 421 ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\ 422 ODM_RTL8710B | ODM_RTL8721D | ODM_RTL8710C) 423 #define ODM_IC_N_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F) 424 #define ODM_IC_N_3SS 0 425 #define ODM_IC_N_4SS 0 426 427 #define ODM_IC_AC_1SS (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\ 428 ODM_RTL8195B) 429 #define ODM_IC_AC_2SS (ODM_RTL8812 | ODM_RTL8822B) 430 #define ODM_IC_AC_3SS 0 431 #define ODM_IC_AC_4SS (ODM_RTL8814A) 432 433 #define ODM_IC_JGR3_1SS (ODM_RTL8723F) 434 #define ODM_IC_JGR3_2SS (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G) 435 #define ODM_IC_JGR3_3SS 0 436 #define ODM_IC_JGR3_4SS (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8814C) 437 438 /*@====the following macro DO NOT need to update when adding a new IC======= */ 439 #define ODM_IC_1SS (ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS) 440 #define ODM_IC_2SS (ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS) 441 #define ODM_IC_3SS (ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS) 442 #define ODM_IC_4SS (ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS) 443 444 #define PHYDM_IC_ABOVE_1SS (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\ 445 ODM_IC_4SS) 446 #define PHYDM_IC_ABOVE_2SS (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS) 447 #define PHYDM_IC_ABOVE_3SS (ODM_IC_3SS | ODM_IC_4SS) 448 #define PHYDM_IC_ABOVE_4SS ODM_IC_4SS 449 450 #define ODM_IC_11N_SERIES (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\ 451 ODM_IC_N_4SS) 452 #define ODM_IC_11AC_SERIES (ODM_IC_AC_1SS | ODM_IC_AC_2SS |\ 453 ODM_IC_AC_3SS | ODM_IC_AC_4SS) 454 #define ODM_IC_JGR3_SERIES (ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\ 455 ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS) 456 /*@====================================================*/ 457 458 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) 459 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\ 460 ODM_RTL8195B) 461 462 /*@[Phy status type]*/ 463 #define PHYSTS_2ND_TYPE_IC (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\ 464 ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\ 465 ODM_RTL8192F | ODM_RTL8721D | ODM_RTL8710C) 466 #define PHYSTS_3RD_TYPE_IC (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C |\ 467 ODM_RTL8812F | ODM_RTL8197G | ODM_RTL8723F |\ 468 ODM_RTL8814C) 469 /*@[FW Type]*/ 470 #define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\ 471 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\ 472 ODM_RTL8188F | ODM_RTL8192F | ODM_RTL8721D |\ 473 ODM_RTL8710C) 474 #define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ 475 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ 476 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814B |\ 477 ODM_RTL8197G | ODM_RTL8723F | ODM_RTL8814C) 478 /*@[LA mode]*/ 479 #define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\ 480 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\ 481 ODM_RTL8192F | ODM_RTL8822C | ODM_RTL8812F |\ 482 ODM_RTL8195B | ODM_RTL8814B | ODM_RTL8197G |\ 483 ODM_RTL8723F | ODM_RTL8814C) 484 /*@[BF]*/ 485 #define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\ 486 ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\ 487 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\ 488 ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8812F |\ 489 ODM_RTL8814B | ODM_RTL8197G | ODM_RTL8814C) 490 #define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\ 491 ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C |\ 492 ODM_RTL8812F | ODM_RTL8723F | ODM_RTL8814C) 493 #define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\ 494 ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8814C) 495 496 #define PHYDM_IC_SUPPORT_MU (PHYDM_IC_SUPPORT_MU_BFEE |\ 497 PHYDM_IC_SUPPORT_MU_BFER) 498 /*@[PHYDM API]*/ 499 #define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\ 500 ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\ 501 ODM_RTL8198F | ODM_RTL8812F | ODM_RTL8814B |\ 502 ODM_RTL8197G | ODM_RTL8721D | ODM_RTL8710C |\ 503 ODM_RTL8723F | ODM_RTL8814C) 504 505 /* fw offload ability*/ 506 #define PHYDM_IC_SUPPORT_FW_PARAM_OFFLOAD (ODM_RTL8814A | ODM_RTL8822B |\ 507 ODM_RTL8821C | ODM_RTL8822C) 508 509 /* halmac offload ability*/ 510 #define PHYDM_IC_SUPPORT_HALMAC_PARAM_OFFLOAD (ODM_RTL8822C | ODM_RTL8812F |\ 511 ODM_RTL8814B | ODM_RTL8723F |\ 512 ODM_RTL8814C) 513 514 /*[CCX]*/ 515 #define PHYDM_IC_SUPPORT_FAHM (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8198F |\ 516 ODM_RTL8814B | ODM_RTL8822C | ODM_RTL8812F |\ 517 ODM_RTL8197G | ODM_RTL8723F | ODM_RTL8814C) 518 #define PHYDM_IC_SUPPORT_IFS_CLM (ODM_RTL8822C | ODM_RTL8812F | ODM_RTL8197G |\ 519 ODM_RTL8723F) 520 #define PHYDM_IC_SUPPORT_EDCCA_CLM (ODM_RTL8822C | ODM_RTL8812F |\ 521 ODM_RTL8197G | ODM_RTL8723F) 522 523 /*[ARFR]*/ 524 /*for MAC HW control rate_id=0~12 and 2.4g vht mode(1ss/2ss) support*/ 525 #define PHYDM_IC_RATEID_IDX_TYPE2 (ODM_RTL8822B | ODM_RTL8822C | ODM_RTL8195B |\ 526 ODM_RTL8821C) 527 528 /*@========[Compile time IC flag] ========================*/ 529 /*@========[AC-3/AC/N Support] ===========================*/ 530 531 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT ||\ 532 RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 533 #define PHYDM_IC_JGR3_SERIES_SUPPORT 534 #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) 535 #define PHYDM_IC_JGR3_80M_SUPPORT 536 #endif 537 #endif 538 539 #if (RTL8822C_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\ 540 RTL8723F_SUPPORT) 541 #define PHYDM_IC_HALMAC_PARAM_SUPPORT 542 #endif 543 544 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) 545 546 #ifdef RTK_AC_SUPPORT 547 #define ODM_IC_11AC_SERIES_SUPPORT 1 548 #else 549 #define ODM_IC_11AC_SERIES_SUPPORT 0 550 #endif 551 552 #define ODM_IC_11N_SERIES_SUPPORT 1 553 554 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 555 556 #define ODM_IC_11AC_SERIES_SUPPORT 1 557 #define ODM_IC_11N_SERIES_SUPPORT 1 558 559 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211) 560 561 #define ODM_IC_11AC_SERIES_SUPPORT 1 562 #define ODM_IC_11N_SERIES_SUPPORT 1 563 564 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2) 565 566 #define ODM_IC_11AC_SERIES_SUPPORT 1 567 #define ODM_IC_11N_SERIES_SUPPORT 1 568 569 #else /*ODM_CE*/ 570 571 #if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\ 572 RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\ 573 RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\ 574 RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 575 #define ODM_IC_11N_SERIES_SUPPORT 1 576 #define ODM_IC_11AC_SERIES_SUPPORT 0 577 #else 578 #define ODM_IC_11N_SERIES_SUPPORT 0 579 #define ODM_IC_11AC_SERIES_SUPPORT 1 580 #endif 581 #endif 582 583 /*@===IC SS Compile Flag, prepare for code size reduction==============*/ 584 #if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\ 585 RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\ 586 RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\ 587 RTL8710B_SUPPORT || RTL8195B_SUPPORT || RTL8721D_SUPPORT ||\ 588 RTL8710C_SUPPORT || RTL8723F_SUPPORT) 589 590 #define PHYDM_COMPILE_IC_1SS 591 #endif 592 593 #if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\ 594 RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT ||\ 595 RTL8812F_SUPPORT || RTL8197G_SUPPORT) 596 #define PHYDM_COMPILE_IC_2SS 597 #endif 598 599 /*@#define PHYDM_COMPILE_IC_3SS*/ 600 601 #if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT)) 602 #define PHYDM_COMPILE_IC_4SS 603 #endif 604 605 /*@==[ABOVE N-SS COMPILE FLAG]=================================================*/ 606 #if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\ 607 defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 608 #define PHYDM_COMPILE_ABOVE_1SS 609 #endif 610 611 #if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\ 612 defined(PHYDM_COMPILE_IC_4SS)) 613 #define PHYDM_COMPILE_ABOVE_2SS 614 #endif 615 616 #if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS)) 617 #define PHYDM_COMPILE_ABOVE_3SS 618 #endif 619 620 #if (defined(PHYDM_COMPILE_IC_4SS)) 621 #define PHYDM_COMPILE_ABOVE_4SS 622 #endif 623 624 /*@==[Max RF path number among all compiled ICs]==============================*/ 625 /*@ ex: support 8814B & 8821C => size=4 */ 626 /*@ ex: support 8822C & 8821C => size=2 */ 627 #if (defined(PHYDM_COMPILE_IC_4SS)) 628 #define RF_PATH_MEM_SIZE 4 629 #elif (defined(PHYDM_COMPILE_IC_3SS)) 630 #define RF_PATH_MEM_SIZE 3 631 #elif (defined(PHYDM_COMPILE_IC_2SS)) 632 #define RF_PATH_MEM_SIZE 2 633 #else 634 #define RF_PATH_MEM_SIZE 1 635 #endif 636 637 /*@========[New Phy-Status Support] ========================*/ 638 #if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\ 639 RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\ 640 RTL8192F_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT) 641 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 1 642 #else 643 #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT 0 644 #endif 645 646 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\ 647 RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 648 #define PHYSTS_3RD_TYPE_SUPPORT 649 #endif 650 651 #ifdef PHYSTS_3RD_TYPE_SUPPORT 652 #define PHYSTS_AUTO_SWITCH_IC (ODM_RTL8822C) 653 #endif 654 655 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT ||\ 656 RTL8812F_SUPPORT || RTL8197G_SUPPORT || RTL8723F_SUPPORT) 657 #define BB_RAM_SUPPORT 658 #endif 659 660 #if (RTL8821C_SUPPORT || RTL8822B_SUPPORT || RTL8822C_SUPPORT ||\ 661 RTL8812F_SUPPORT || RTL8814B_SUPPORT || RTL8195B_SUPPORT ||\ 662 RTL8198F_SUPPORT) 663 #define PHYDM_COMPILE_MU 664 #endif 665 666 #if (RTL8822B_SUPPORT) 667 #define CONFIG_MU_JAGUAR_2 668 #endif 669 670 #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) 671 #define CONFIG_MU_JAGUAR_3 672 #endif 673 674 #if (defined(CONFIG_MU_JAGUAR_2) || defined(CONFIG_MU_JAGUAR_3)) 675 #if (RTL8814B_SUPPORT) 676 #define MU_EX_MACID 76 677 #elif (RTL8822B_SUPPORT || RTL8822C_SUPPORT || RTL8812F_SUPPORT) 678 #define MU_EX_MACID 30 679 #endif 680 #endif 681 /*@============================================================================*/ 682 683 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\ 684 RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\ 685 RTL8198F_SUPPORT || RTL8812F_SUPPORT || RTL8814B_SUPPORT ||\ 686 RTL8197G_SUPPORT || RTL8721D_SUPPORT || RTL8710C_SUPPORT || RTL8723F_SUPPORT) 687 #define PHYDM_COMMON_API_SUPPORT 688 #endif 689 690 #define PHYDM_COMMON_API_IC (ODM_IC_JGR3_SERIES | ODM_RTL8822B |\ 691 ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8192F | ODM_RTL8195B |\ 692 ODM_RTL8721D | ODM_RTL8710C) 693 694 #if (RTL8188E_SUPPORT || RTL8192E_SUPPORT || RTL8821A_SUPPORT ||\ 695 RTL8812A_SUPPORT || RTL8723B_SUPPORT || RTL8703B_SUPPORT ||\ 696 RTL8195A_SUPPORT || RTL8814A_SUPPORT) 697 #define PHYDM_COMMON_API_NOT_SUPPORT 698 #endif 699 700 #if (RTL8821C_SUPPORT || RTL8197F_SUPPORT || RTL8197G_SUPPORT) 701 #define CONFIG_RFE_BY_HW_INFO 702 #endif 703 704 #define CCK_RATE_NUM 4 705 #define OFDM_RATE_NUM 8 706 707 #define LEGACY_RATE_NUM 12 708 709 #define HT_RATE_NUM_4SS 32 710 #define VHT_RATE_NUM_4SS 40 711 712 #define HT_RATE_NUM_3SS 24 713 #define VHT_RATE_NUM_3SS 30 714 715 #define HT_RATE_NUM_2SS 16 716 #define VHT_RATE_NUM_2SS 20 717 718 #define HT_RATE_NUM_1SS 8 719 #define VHT_RATE_NUM_1SS 10 720 #if (defined(PHYDM_COMPILE_ABOVE_4SS)) 721 #define HT_RATE_NUM HT_RATE_NUM_4SS 722 #define VHT_RATE_NUM VHT_RATE_NUM_4SS 723 #elif (defined(PHYDM_COMPILE_ABOVE_3SS)) 724 #define HT_RATE_NUM HT_RATE_NUM_3SS 725 #define VHT_RATE_NUM VHT_RATE_NUM_3SS 726 #elif (defined(PHYDM_COMPILE_ABOVE_2SS)) 727 #define HT_RATE_NUM HT_RATE_NUM_2SS 728 #define VHT_RATE_NUM VHT_RATE_NUM_2SS 729 #else 730 #define HT_RATE_NUM HT_RATE_NUM_1SS 731 #define VHT_RATE_NUM VHT_RATE_NUM_1SS 732 #endif 733 734 #define LOW_BW_RATE_NUM VHT_RATE_NUM 735 736 #if (DM_ODM_SUPPORT_TYPE == ODM_CE) 737 #define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD4: HAL_PRIME_CHNL_OFFSET_UPPER*/ 738 #define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD4: HAL_PRIME_CHNL_OFFSET_LOWER*/ 739 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) 740 #define SECOND_CH_AT_LSB 2 /*@primary CH @ MSB, SD7: HAL_PRIME_CHNL_OFFSET_UPPER*/ 741 #define SECOND_CH_AT_USB 1 /*@primary CH @ LSB, SD7: HAL_PRIME_CHNL_OFFSET_LOWER*/ 742 #else /*if (DM_ODM_SUPPORT_TYPE == ODM_AP)*/ 743 #define SECOND_CH_AT_LSB 1 /*@primary CH @ MSB, SD8: HT_2NDCH_OFFSET_BELOW*/ 744 #define SECOND_CH_AT_USB 2 /*@primary CH @ LSB, SD8: HT_2NDCH_OFFSET_ABOVE*/ 745 #endif 746 747 enum phydm_ic_ip { 748 PHYDM_IC_N = 0, 749 PHYDM_IC_AC = 1, 750 PHYDM_IC_JGR3 = 2 751 }; 752 753 enum phydm_phy_sts_type { 754 PHYDM_PHYSTS_TYPE_1 = 1, 755 PHYDM_PHYSTS_TYPE_2 = 2, 756 PHYDM_PHYSTS_TYPE_3 = 3 757 }; 758 759 /* ODM_CMNINFO_CUT_VER */ 760 enum odm_cut_version { 761 ODM_CUT_A = 0, 762 ODM_CUT_B = 1, 763 ODM_CUT_C = 2, 764 ODM_CUT_D = 3, 765 ODM_CUT_E = 4, 766 ODM_CUT_F = 5, 767 ODM_CUT_G = 6, 768 ODM_CUT_H = 7, 769 ODM_CUT_I = 8, 770 ODM_CUT_J = 9, 771 ODM_CUT_K = 10, 772 ODM_CUT_L = 11, 773 ODM_CUT_M = 12, 774 ODM_CUT_N = 13, 775 ODM_CUT_O = 14, 776 ODM_CUT_TEST = 15, 777 }; 778 779 /* ODM_CMNINFO_FAB_VER */ 780 enum odm_fab { 781 ODM_TSMC = 0, 782 ODM_UMC = 1, 783 }; 784 785 /* ODM_CMNINFO_OP_MODE */ 786 enum odm_operation_mode { 787 ODM_NO_LINK = BIT(0), 788 ODM_LINK = BIT(1), 789 ODM_SCAN = BIT(2), 790 ODM_POWERSAVE = BIT(3), 791 ODM_AP_MODE = BIT(4), 792 ODM_CLIENT_MODE = BIT(5), 793 ODM_AD_HOC = BIT(6), 794 ODM_WIFI_DIRECT = BIT(7), 795 ODM_WIFI_DISPLAY = BIT(8), 796 }; 797 798 /* ODM_CMNINFO_WM_MODE */ 799 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) 800 enum odm_wireless_mode { 801 ODM_WM_UNKNOW = 0x0, 802 ODM_WM_B = BIT(0), 803 ODM_WM_G = BIT(1), 804 ODM_WM_A = BIT(2), 805 ODM_WM_N24G = BIT(3), 806 ODM_WM_N5G = BIT(4), 807 ODM_WM_AUTO = BIT(5), 808 ODM_WM_AC = BIT(6), 809 }; 810 #else 811 enum odm_wireless_mode { 812 ODM_WM_UNKNOWN = 0x00,/*@0x0*/ 813 ODM_WM_A = BIT(0), /* @0x1*/ 814 ODM_WM_B = BIT(1), /* @0x2*/ 815 ODM_WM_G = BIT(2),/* @0x4*/ 816 ODM_WM_AUTO = BIT(3),/* @0x8*/ 817 ODM_WM_N24G = BIT(4),/* @0x10*/ 818 ODM_WM_N5G = BIT(5),/* @0x20*/ 819 ODM_WM_AC_5G = BIT(6),/* @0x40*/ 820 ODM_WM_AC_24G = BIT(7),/* @0x80*/ 821 ODM_WM_AC_ONLY = BIT(8),/* @0x100*/ 822 ODM_WM_MAX = BIT(11)/* @0x800*/ 823 824 }; 825 #endif 826 827 /* ODM_CMNINFO_BAND */ 828 enum odm_band_type { 829 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) 830 ODM_BAND_2_4G = BIT(0), 831 ODM_BAND_5G = BIT(1), 832 #else 833 ODM_BAND_2_4G = 0, 834 ODM_BAND_5G, 835 ODM_BAND_ON_BOTH, 836 ODM_BANDMAX 837 #endif 838 }; 839 840 enum odm_rf_band { 841 ODM_RF_BAND_2G = 0, 842 ODM_RF_BAND_5G_LOW = 1, 843 ODM_RF_BAND_5G_MID = 2, 844 ODM_RF_BAND_5G_HIGH = 3, 845 }; 846 847 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 848 enum phydm_sec_chnl_offset { 849 PHYDM_DONT_CARE = 0, 850 PHYDM_BELOW = 1, 851 PHYDM_ABOVE = 2 852 }; 853 854 /* ODM_CMNINFO_SEC_MODE */ 855 enum odm_security { 856 ODM_SEC_OPEN = 0, 857 ODM_SEC_WEP40 = 1, 858 ODM_SEC_TKIP = 2, 859 ODM_SEC_RESERVE = 3, 860 ODM_SEC_AESCCMP = 4, 861 ODM_SEC_WEP104 = 5, 862 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 863 ODM_SEC_SMS4 = 7, 864 }; 865 866 /* ODM_CMNINFO_CHNL */ 867 868 /* ODM_CMNINFO_BOARD_TYPE */ 869 enum odm_board_type { 870 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 871 ODM_BOARD_MINICARD = BIT(0), /* @0 = non-mini card, 1= mini card. */ 872 ODM_BOARD_SLIM = BIT(1), /* @0 = non-slim card, 1 = slim card */ 873 ODM_BOARD_BT = BIT(2), /* @0 = without BT card, 1 = with BT */ 874 ODM_BOARD_EXT_PA = BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 875 ODM_BOARD_EXT_LNA = BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 876 ODM_BOARD_EXT_TRSW = BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */ 877 ODM_BOARD_EXT_PA_5G = BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 878 ODM_BOARD_EXT_LNA_5G = BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 879 }; 880 881 enum odm_package_type { 882 ODM_PACKAGE_DEFAULT = 0, 883 ODM_PACKAGE_QFN68 = BIT(0), 884 ODM_PACKAGE_TFBGA90 = BIT(1), 885 ODM_PACKAGE_TFBGA79 = BIT(2), 886 }; 887 888 enum odm_type_gpa { 889 TYPE_GPA0 = 0x0000, 890 TYPE_GPA1 = 0x0055, 891 TYPE_GPA2 = 0x00AA, 892 TYPE_GPA3 = 0x00FF, 893 TYPE_GPA4 = 0x5500, 894 TYPE_GPA5 = 0x5555, 895 TYPE_GPA6 = 0x55AA, 896 TYPE_GPA7 = 0x55FF, 897 TYPE_GPA8 = 0xAA00, 898 TYPE_GPA9 = 0xAA55, 899 TYPE_GPA10 = 0xAAAA, 900 TYPE_GPA11 = 0xAAFF, 901 TYPE_GPA12 = 0xFF00, 902 TYPE_GPA13 = 0xFF55, 903 TYPE_GPA14 = 0xFFAA, 904 TYPE_GPA15 = 0xFFFF, 905 }; 906 907 enum odm_type_apa { 908 TYPE_APA0 = 0x0000, 909 TYPE_APA1 = 0x0055, 910 TYPE_APA2 = 0x00AA, 911 TYPE_APA3 = 0x00FF, 912 TYPE_APA4 = 0x5500, 913 TYPE_APA5 = 0x5555, 914 TYPE_APA6 = 0x55AA, 915 TYPE_APA7 = 0x55FF, 916 TYPE_APA8 = 0xAA00, 917 TYPE_APA9 = 0xAA55, 918 TYPE_APA10 = 0xAAAA, 919 TYPE_APA11 = 0xAAFF, 920 TYPE_APA12 = 0xFF00, 921 TYPE_APA13 = 0xFF55, 922 TYPE_APA14 = 0xFFAA, 923 TYPE_APA15 = 0xFFFF, 924 }; 925 926 enum odm_type_glna { 927 TYPE_GLNA0 = 0x0000, 928 TYPE_GLNA1 = 0x0055, 929 TYPE_GLNA2 = 0x00AA, 930 TYPE_GLNA3 = 0x00FF, 931 TYPE_GLNA4 = 0x5500, 932 TYPE_GLNA5 = 0x5555, 933 TYPE_GLNA6 = 0x55AA, 934 TYPE_GLNA7 = 0x55FF, 935 TYPE_GLNA8 = 0xAA00, 936 TYPE_GLNA9 = 0xAA55, 937 TYPE_GLNA10 = 0xAAAA, 938 TYPE_GLNA11 = 0xAAFF, 939 TYPE_GLNA12 = 0xFF00, 940 TYPE_GLNA13 = 0xFF55, 941 TYPE_GLNA14 = 0xFFAA, 942 TYPE_GLNA15 = 0xFFFF, 943 }; 944 945 enum odm_type_alna { 946 TYPE_ALNA0 = 0x0000, 947 TYPE_ALNA1 = 0x0055, 948 TYPE_ALNA2 = 0x00AA, 949 TYPE_ALNA3 = 0x00FF, 950 TYPE_ALNA4 = 0x5500, 951 TYPE_ALNA5 = 0x5555, 952 TYPE_ALNA6 = 0x55AA, 953 TYPE_ALNA7 = 0x55FF, 954 TYPE_ALNA8 = 0xAA00, 955 TYPE_ALNA9 = 0xAA55, 956 TYPE_ALNA10 = 0xAAAA, 957 TYPE_ALNA11 = 0xAAFF, 958 TYPE_ALNA12 = 0xFF00, 959 TYPE_ALNA13 = 0xFF55, 960 TYPE_ALNA14 = 0xFFAA, 961 TYPE_ALNA15 = 0xFFFF, 962 }; 963 964 #if (RTL8721D_SUPPORT) 965 /* ODM_CMNINFO_POWER_VOLTAGE */ 966 enum odm_power_voltage { 967 ODM_POWER_18V = 0, 968 ODM_POWER_33V = 1, 969 }; 970 971 /* ODM_CMNINFO_ANTDIV_GPIO */ 972 enum odm_antdiv_gpio { 973 ANTDIV_GPIO_PA2PA4 = 0, 974 ANTDIV_GPIO_PA5PA6 = 1, 975 ANTDIV_GPIO_PA12PA13 = 2, 976 ANTDIV_GPIO_PA14PA15 = 3, 977 ANTDIV_GPIO_PA16PA17 = 4, 978 ANTDIV_GPIO_PB1PB2 = 5, 979 ANTDIV_GPIO_PB26PB29 = 6, 980 ANTDIV_GPIO_PB1PB2PB26 = 7, // add by Jiao Qi for AmebaD SP3T only 981 }; 982 983 /* ODM_CMNINFO_PEAK_DETECT_MODE */ 984 enum odm_peak_detect_mode { 985 ODM_PD_DIS = 0, 986 ODM_PD_ENG = 1, 987 ODM_PD_ENA = 2, 988 ODM_PD_ENALL = 3, 989 }; 990 #endif 991 992 #define PAUSE_FAIL 0 993 #define PAUSE_SUCCESS 1 994 995 enum odm_parameter_init { 996 ODM_PRE_SETTING = 0, 997 ODM_POST_SETTING = 1, 998 ODM_INIT_FW_SETTING = 2, 999 ODM_PRE_RF_SET = 3, 1000 ODM_POST_RF_SET = 4 1001 }; 1002 1003 enum phydm_pause_type { 1004 PHYDM_PAUSE = 1, /*Pause & Set new value*/ 1005 PHYDM_PAUSE_NO_SET = 2, /*Pause & Stay in current value*/ 1006 PHYDM_RESUME = 3 1007 }; 1008 1009 enum phydm_backup_type { 1010 PHYDM_BACKUP = 1, 1011 PHYDM_RESTORE = 2 1012 }; 1013 1014 enum phydm_pause_level { 1015 PHYDM_PAUSE_RELEASE = -1, 1016 PHYDM_PAUSE_LEVEL_0 = 0, /* @Low Priority function */ 1017 PHYDM_PAUSE_LEVEL_1 = 1, /* @Middle Priority function */ 1018 PHYDM_PAUSE_LEVEL_2 = 2, /* @High priority function (ex: Check hang function) */ 1019 PHYDM_PAUSE_LEVEL_3 = 3, /* @Debug function (the highest priority) */ 1020 PHYDM_PAUSE_MAX_NUM = 4 1021 }; 1022 1023 enum phydm_dis_hw_fun { 1024 HW_FUN_DIS = 0, /*@Disable a cetain HW function & backup the original value*/ 1025 HW_FUN_RESUME = 1 /*Revert */ 1026 }; 1027 1028 #endif 1029