1 /* 2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _DUET_H_ 17 #define _DUET_H_ 18 #include <stdint.h> 19 #include <stdio.h> 20 #if 0 // use duet_cm33.h 21 typedef enum { RESET = 0, SET = !RESET} FlagStatus, ITstatus; 22 typedef enum { DISABLE = 0, ENABLE = !DISABLE } State; 23 24 typedef enum IRQn { 25 /************** Processor Exceptions Numbers ******************************************/ 26 NonMaskableInt_IRQn = -14, /* !< 2 Non Maskable Interrupt */ 27 MemoryManagement_IRQn = -12, /* !< 4 Cortex-M3 Memory Management Interrupt */ 28 BusFault_IRQn = -11, /* !< 5 Cortex-M3 Bus Fault Interrupt */ 29 UsageFault_IRQn = -10, /* !< 6 Cortex-M3 Usage Fault Interrupt */ 30 SVCall_IRQn = -5, /* !< 11 Cortex-M3 SV Call Interrupt */ 31 DebugMonitor_IRQn = -4, /* !< 12 Cortex-M3 Debug Monitor Interrupt */ 32 PendSV_IRQn = -2, /* !< 14 Cortex-M3 Pend SV Interrupt */ 33 SysTick_IRQn = -1, /* !< 15 Cortex-M3 System Tick Interrupt */ 34 /****** Interrupt Numbers *******************************************************/ 35 CEVA_RW_IP_IRQn = 0, /* !< CEVA RW IP Interrupt */ 36 SLEEP_IRQn = 1, /* !< Sleep Wake-Up Interrupt */ 37 WDG_IRQn = 2, /* !< Window WatchDog */ 38 FLASH_IRQn = 3, /* !< FLASH Interrupt */ 39 GPIO_IRQn = 4, /* !< GPIO Interrupt */ 40 TIMER_IRQn = 5, /* !< Timer Interrupt */ 41 CRYPTOCELL310_IRQn = 6, /* !< CryptoCell 310 Interrupt */ 42 DMA_IRQn = 7, /* !< Generic DMA Ctrl Interrupt */ 43 UART0_IRQn = 8, /* !< UART0 Interrupt */ 44 UART1_IRQn = 9, /* !< UART1 Interrupt */ 45 UART2_IRQn = 10, /* !< UART2 Interrupt */ 46 SPI0_IRQn = 11, /* !< SPI0 Interrupt */ 47 SPI1_IRQn = 12, /* !< SPI1 Interrupt */ 48 SPI2_IRQn = 13, /* !< SPI2 */ 49 I2C0_IRQn = 14, /* !< I2C0 Interrupt */ 50 I2C1_IRQn = 15, /* !< I2C1 Interrupt */ 51 SDIO_IRQn = 16, /* !< SDIO Combined Interrupt */ 52 D_APLL_UNLOCK_IRQn = 17, /* !< RF added: D_APLL_UNLOCK Interrupt */ 53 D_SX_UNLOCK_IRQn = 18, /* !< RF added: D_SX_UNLOCK Interrupt */ 54 PLF_WAKEUP_IRQn = 23, /* !< WiFi Platform Wake-Up Interrupt */ 55 I2S_IRQn = 24, /* !< I2S Interrupt */ 56 RW_BLE_IRQn = 25, /* !< BLE Interrupt */ 57 } IRQn_Type; 58 #endif 59 #include "duet_cm4.h" 60 #include "core_cm4.h" 61 62 // Macro to read a register 63 #define REG_RD(addr) (*(volatile uint32_t *)(addr)) 64 // Macro to write a register 65 #define REG_WR(addr, value) (*(volatile uint32_t *)(addr)) = (value) 66 67 /* 68 system control register definition 69 */ 70 typedef struct Sys_Con_Block { 71 union { 72 struct { 73 __IO uint32_t hclk_src_sel : 2; 74 __IO uint32_t pclk_div_sel : 3; 75 __IO uint32_t kp_sclk_sel : 1; 76 __IO uint32_t timer1_sclk_sel : 1; 77 __IO uint32_t timer2_sclk_sel : 1; 78 __IO uint32_t timer3_sclk_sel : 1; 79 __IO uint32_t timer4_sclk_sel : 1; 80 __IO uint32_t rw_mst_clk_freq_sel : 6; 81 __I uint32_t rsv0 : 1; 82 __IO uint32_t pwm_pclk_sel : 1; 83 __I uint32_t rsv1 : 14; 84 } BITS_CLK_SEL; 85 __IO uint32_t REG_00; 86 }; 87 __IO uint32_t REG_04; 88 __IO uint32_t REG_08; 89 __I uint32_t REG_0C; 90 __I uint32_t REG_10; 91 __IO uint32_t REG_14; 92 __IO uint32_t REG_18; 93 __IO uint32_t REG_1C; 94 /* I2S clock divider */ 95 union { 96 struct { 97 __IO uint32_t i2s_ws_div : 8; 98 __IO uint32_t i2s_sclk_div : 8; 99 __IO uint32_t i2s_mclk_div : 8; 100 __IO uint32_t RESV3 : 8; 101 } BITS_REG_20; 102 __IO uint32_t REG_20; 103 }; 104 __IO uint32_t REG_24; 105 __I uint32_t REG_28; 106 __IO uint32_t REG_2C; 107 __IO uint32_t REG_30; 108 __IO uint32_t REG_34; 109 __I uint32_t REG_38; 110 __I uint32_t REG_3C; 111 __IO uint32_t REG_40; 112 __IO uint32_t REG_44; 113 __IO uint32_t REG_48; 114 __IO uint32_t REG_4C; 115 __IO uint32_t REG_50; 116 __IO uint32_t REG_54; 117 __IO uint32_t REG_58; 118 __IO uint32_t REG_5C; 119 __IO uint32_t REG_60; 120 __IO uint32_t REG_64; 121 union { 122 struct { 123 __IO uint32_t zr_gp0_sel : 4; 124 __IO uint32_t zr_gp1_sel : 4; 125 __IO uint32_t zr_gp2_sel : 4; 126 __IO uint32_t zr_gp3_sel : 4; 127 __IO uint32_t zr_gp4_sel : 4; 128 __IO uint32_t zr_gp5_sel : 4; 129 __IO uint32_t zr_gp6_sel : 4; 130 __IO uint32_t zr_gp7_sel : 4; 131 } BITS_REG_68; 132 __IO uint32_t REG_68; /* pinmux control */ 133 }; 134 union { 135 struct { 136 __IO uint32_t zr_gp8_sel : 4; 137 __IO uint32_t zr_gp9_sel : 4; 138 __IO uint32_t zr_gp10_sel : 4; 139 __IO uint32_t zr_gp11_sel : 4; 140 __IO uint32_t zr_gp12_sel : 4; 141 __IO uint32_t zr_gp13_sel : 4; 142 __IO uint32_t zr_gp14_sel : 4; 143 __IO uint32_t zr_gp15_sel : 4; 144 } BITS_REG_6C; 145 __IO uint32_t REG_6C; /* pinmux control */ 146 }; 147 union { 148 struct { 149 __IO uint32_t zr_gp16_sel : 4; 150 __IO uint32_t zr_gp17_sel : 4; 151 __IO uint32_t zr_gp18_sel : 4; 152 __IO uint32_t zr_gp19_sel : 4; 153 __IO uint32_t zr_gp20_sel : 4; 154 __IO uint32_t zr_gp21_sel : 4; 155 __IO uint32_t zr_gp22_sel : 4; 156 __IO uint32_t zr_gp23_sel : 4; 157 } BITS_REG_70; 158 __IO uint32_t REG_70; /* pinmux control */ 159 }; 160 union { 161 struct { 162 __IO uint32_t zr_gp24_sel : 4; 163 __IO uint32_t zr_gp25_sel : 4; 164 __IO uint32_t zr_gp26_sel : 4; 165 __IO uint32_t zr_gp27_sel : 4; 166 __IO uint32_t zr_gp28_sel : 4; 167 __IO uint32_t zr_gp29_sel : 4; 168 __IO uint32_t zr_gp30_sel : 4; 169 __I uint32_t rsv7 : 4; 170 } BITS_REG_74; 171 __IO uint32_t REG_74; /* pinmux control */ 172 }; 173 174 __IO uint32_t REG_78; 175 __IO uint32_t REG_7C; 176 __IO uint32_t REG_80; 177 __IO uint32_t REG_84; 178 __IO uint32_t REG_88; 179 __IO uint32_t REG_8C; 180 __IO uint32_t REG_90; /* IR control */ 181 __IO uint32_t REG_94; 182 __IO uint32_t REG_98; 183 __IO uint32_t REG_9C; 184 __IO uint32_t REG_A0; 185 __IO uint32_t REG_A4; 186 __IO uint32_t REG_A8; 187 __I uint32_t REG_AC; 188 __IO uint32_t REG_B0; 189 __IO uint32_t REG_B4; 190 __IO uint32_t REG_B8; 191 __IO uint32_t REG_BC; 192 __IO uint32_t REG_C0; 193 } SYS_CON_BLOCK; 194 195 #define SYS_CON_REG_BASE (0x40000000) 196 #define SYS_CON ((SYS_CON_BLOCK *)(SYS_CON_REG_BASE)) 197 198 #define PINMUX_REG_BASE (SYS_CON_REG_BASE + 0x04) 199 #define PAD_PULL_CTRL_REG_BASE (SYS_CON_REG_BASE + 0x54) 200 201 #define PERI_CG_REG_BASE (SYS_CON_REG_BASE + 0x14) 202 #define PERI_SOFT_RESET_REG_BASE (SYS_CON_REG_BASE + 0x18) 203 #define REG_PERI_CG_EN (*((volatile uint32_t *)(PERI_CG_REG_BASE))) 204 #define REG_PERI_SOFT_RESET_REG (*((volatile uint32_t *)(PERI_SOFT_RESET_REG_BASE))) 205 206 #define SYSCTRL_BASE SYS_CON_REG_BASE 207 #define SYS_CON_00 *(volatile int unsigned *)(SYSCTRL_BASE + (0x000*4)) 208 #define RTC_COUNT_1S *(volatile int unsigned *)(SYSCTRL_BASE + (0x023*4)) 209 210 #define APBCLK_DIV_0 (0) 211 #define APBCLK_DIV_2 (0x00000001<<2) 212 #define APBCLK_DIV_3 (0x00000002<<2) 213 #define APBCLK_DIV_4 (0x00000003<<2) 214 #define APBCLK_DIV_CFG APBCLK_DIV_0 215 216 #define APB_CLK_DIV_REG (0X40000808) 217 #define PERI_CLK_EN_REG0 (0X40000840) 218 #define PERI_CLK_EN_REG1 (0X40000844) 219 #define PERI_CLK_DIS_REG0 (0X40000848) 220 #define PERI_CLK_DIS_REG1 (0X4000084C) 221 #define DUTE_IRQ_EN_REG (0X40000944) 222 #define DUTE_IRQ_DIS_REG (0X40000948) 223 #define DMA_BUFFER_REG (0X4000C000) 224 225 /* pinmux definitions */ 226 enum PINMUX_FUNC { 227 GPIO_FUNC, 228 UART_FUNC, 229 SPI_FUNC, 230 I2C_I2S_FUNC, 231 PWM_FUNC, 232 AXIS_FUNC, 233 KEYPAD_FUNC, 234 DEBUG_FUNC 235 }; 236 237 /* 238 DUET DMA definitions 239 */ 240 #define DMA_REG_BASE (0x40004000) 241 242 typedef struct __DMACR { 243 __I uint32_t STAT; 244 __O uint32_t CFG; 245 __IO uint32_t CTL_BASE_PTR; 246 __I uint32_t ALT_CTL_BASE_PTR; 247 __I uint32_t WAIT_ON_REQ_STAT; 248 __O uint32_t CHAN_SW_REQ; 249 __IO uint32_t CHAN_USE_BURST_SET; 250 __O uint32_t CHAN_USE_BURST_CLR; 251 __IO uint32_t CHAN_REQ_MASK_SET; 252 __O uint32_t CHAN_REQ_MASK_CLR; 253 __IO uint32_t CHAN_EN_SET; 254 __O uint32_t CHAN_EN_CLR; 255 __IO uint32_t CHAN_PRI_ALT_SET; 256 __O uint32_t CHAN_PRI_ALT_CLR; 257 __IO uint32_t CHAN_PRIORITY_SET; 258 __O uint32_t CHNA_PRIORITY_CLR; /* 0x3c */ 259 __I uint32_t RESV[3]; 260 __O uint32_t ERR_CLR; /* 0x4c */ 261 __I uint32_t RESV1[0x3ec]; /* 0x50 - 0xffc */ 262 } DMA_TypeDef; 263 264 #define DMA ((DMA_TypeDef *)DMA_REG_BASE) 265 #define DMA_ERROR (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x70)) 266 #define DMA_INT_STAT (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x74)) 267 #define DMA_RAW_INT_STAT (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x78)) 268 #define DMA_WAIT_ON_REQ (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x7C)) 269 #define DMA_REQ_DONE_EN (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x80)) 270 #define DMA_STALL (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x84)) 271 #define DMA_INT_CLR (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x88)) 272 #define DMA_INT_MASK (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x8C)) 273 #define DMA_HANDSHAKE_CFG0 (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x90)) 274 #define DMA_HANDSHAKE_CFG1 (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0x94)) 275 276 #define DMA_IRQ_BIT (0X01<<7) 277 #define DMA_CLK_EN (0X01<<13) 278 279 /* 280 DUET I2S definition 281 */ 282 typedef struct __I2S { 283 /* channel-common registers */ 284 __IO uint32_t IER; // 0x00 285 __IO uint32_t IRER; // 0x04 286 __IO uint32_t ITER; // 0x08 287 __IO uint32_t CER; // 0x0c 288 __IO uint32_t CCR; // 0x10 289 __O uint32_t RXFFR; // 0x14 290 __O uint32_t TXFFR; // 0x18 291 __I uint32_t RESV0; // 0x1c 292 293 /* channel-specific registers */ 294 __IO uint32_t LRBR_LTHR; // 0x20 295 __IO uint32_t RRBR_RTHR; // 0x24 296 __IO uint32_t RER; // 0x28 297 __IO uint32_t TER; // 0x2c 298 __IO uint32_t RCR; // 0x30 299 __IO uint32_t TCR; // 0x34 300 __I uint32_t ISR; // 0x38 301 __IO uint32_t IMR; // 0x3c 302 __I uint32_t ROR; // 0x40 303 __I uint32_t TOR; // 0x44 304 __IO uint32_t RFCR; // 0x48 305 __IO uint32_t TFCR; // 0x4c 306 __O uint32_t RFF; // 0x50 307 __O uint32_t TFF; // 0x54 308 __I uint32_t RESV1[0x5a]; 309 __IO uint32_t RXDMA; // 0x1c0 310 __O uint32_t RRXDMA; 311 __IO uint32_t TXDMA; 312 __O uint32_t RTXDMA; // 0x1cc 313 __I uint32_t RESV2[8]; 314 __I uint32_t I2S_COMP_PARAM_2; // 0x1f0 315 __I uint32_t I2S_COMP_PARAM_1; 316 __I uint32_t I2S_COMP_VERSION; 317 __I uint32_t I2S_COMP_TYPE; 318 } I2S_TypeDef; 319 320 #define REG_I2S_HW_SHFIT_SET (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC0)) 321 #define REG_I2S_HW_SHIFT_DATAIN (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC4)) 322 #define REG_I2S_HW_SHIFT_DATAOUT (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC8)) 323 324 #define I2S_BASE (0x4008D000) 325 #define I2S ((I2S_TypeDef *)I2S_BASE) 326 327 /* I2S clock divider */ 328 typedef struct { 329 __IO uint32_t i2s_lrclk_divider : 9; 330 __IO uint32_t i2s_lrclk_delay_sel : 1; 331 __IO uint32_t i2s_sclk_divider : 10; 332 __IO uint32_t i2s_mclk_divider : 10; 333 __IO uint32_t i2s_slave_mode : 1; 334 __IO uint32_t reserved : 1; 335 } I2S_CLK_DIV_TypeDef; 336 337 #define I2S_CLK_DIV ((I2S_CLK_DIV_TypeDef *)0x40000810) 338 339 /* 340 DUET SPI definitions 341 */ 342 343 /* SPI register block */ 344 typedef struct __SPI { 345 __IO uint32_t CR0 ; /* 0x0 */ 346 __IO uint32_t CR1 ; /* 0x4 */ 347 __IO uint32_t DR ; /* 0x8 */ 348 __I uint32_t SR ; /* 0xC */ 349 __IO uint32_t CPSR ; /* 0x10 */ 350 __IO uint32_t IMSC ; /* 0x14 */ 351 __I uint32_t RIS ; /* 0x18 */ 352 __I uint32_t MIS ; /* 0x1C */ 353 __IO uint32_t ICR ; /* 0x20 */ 354 __IO uint32_t DMA_CR ; /* 0x24 */ 355 } SPI_TypeDef ; 356 357 #define SPI_NUM_PORTS 3 358 #define SPI0_BASE (0x40080000+0x4000) 359 #define SPI1_BASE (0x40080000+0x5000) 360 #define SPI2_BASE (0x40080000+0x6000) 361 362 #define SPI0 ((SPI_TypeDef *)SPI0_BASE) 363 #define SPI1 ((SPI_TypeDef *)SPI1_BASE) 364 #define SPI2 ((SPI_TypeDef *)SPI2_BASE) 365 366 #define SPI0_BUS_CLK_EN (0X01<<4) 367 #define SPI0_PERI_CLK_EN (0X01<<17) 368 #define SPI1_BUS_CLK_EN (0X01<<5) 369 #define SPI1_PERI_CLK_EN (0X01<<18) 370 #define SPI2_BUS_CLK_EN (0X01<<6) 371 #define SPI2_PERI_CLK_EN (0X01<<19) 372 373 #define SPI0_IRQ_BIT (0X01<<11) 374 #define SPI1_IRQ_BIT (0X01<<12) 375 #define SPI2_IRQ_BIT (0X01<<13) 376 377 /* 378 SPI definition end 379 */ 380 381 /* 382 DUET KEYPAD definitions 383 */ 384 typedef struct __KEYPAD { 385 __IO uint32_t CR; /* 0x00 */ 386 __I uint32_t RESV0[7]; /* 0x04-0x1C */ 387 __I uint32_t SR; /* 0x20 */ 388 __I uint32_t RESV1; 389 __I uint32_t MULTI_KEY_COL01; /* 0x28 */ 390 __I uint32_t RESV2; 391 __I uint32_t MULTI_KEY_COL23; /* 0x30 */ 392 __I uint32_t RESV3; 393 __I uint32_t MULTI_KEY_COL45; /* 0x38 */ 394 __I uint32_t RESV4; 395 __I uint32_t MULTI_KEY_COL67; /* 0x40 */ 396 __I uint32_t RESV5; 397 __IO uint32_t DEBOUNCE_TIME; /* 0x48 */ 398 __I uint32_t RESV6; 399 __IO uint32_t ROW_MASK; /* 0x50 */ 400 } KEYPAD_TypeDef; 401 402 #define KEYPAD_BASE (0x40015000) 403 #define KEYPAD ((KEYPAD_TypeDef *)KEYPAD_BASE) 404 /* 405 DUET GPIO definitons 406 */ 407 typedef struct __GPIO { 408 __IO uint32_t DATA; 409 __IO uint32_t DATAOUT; 410 __I uint32_t DUMMY0[2]; 411 __IO uint32_t OUTENSET; 412 __IO uint32_t OUTENCLR; 413 __I uint32_t DUMMY1[2]; 414 __IO uint32_t INTENSET; 415 __IO uint32_t INTENCLR; 416 __IO uint32_t INTTYPESET; 417 __IO uint32_t INTTYPECLR; 418 __IO uint32_t INTPOLSET; 419 __IO uint32_t INTPOLCLR; 420 __IO uint32_t INTSTATUS; 421 } GPIO_TypeDef; 422 423 #define GPIO_GROUP0_REG_BASE 0x40001000 424 #define GPIO_GROUP1_REG_BASE 0x40002000 425 #define GPIO_GROUP0 ((GPIO_TypeDef *)(GPIO_GROUP0_REG_BASE)) 426 #define GPIO_GROUP1 ((GPIO_TypeDef *)(GPIO_GROUP1_REG_BASE)) 427 428 #define PAD_PE_REG 0x40000014 429 #define PAD_PS_REG 0x40000018 430 #define PAD_IS_REG 0x4000001C 431 #define HW_CTRL_PE_PS 0x40000020 432 433 /* 434 DUET GPIO END 435 */ 436 437 /* 438 DUET I2C BEGIN 439 */ 440 typedef struct __I2C { 441 __IO uint32_t CR; // 0x00 442 __IO uint32_t SR; 443 __IO uint32_t SAR; // 0x08 444 __IO uint32_t DBR; 445 __IO uint32_t LCR; 446 __IO uint32_t WCR; // 0x14 447 __IO uint32_t RST_CYCL; // 0x18 448 __I uint32_t BMR; // 0x1c 449 __IO uint32_t WFIFO; // 0x20 450 __IO uint32_t WFIFO_WPTR; // 0x24 451 __IO uint32_t WFIFO_RPTR; // 0x28 452 __IO uint32_t RFIFO; // 0x2c 453 __IO uint32_t RFIFO_WPTR; 454 __IO uint32_t RFIFO_RPTR; // 0x34 455 __IO uint32_t RESV[2]; // 0x38 0x3C 456 __I uint32_t WFIFO_STATUS; // 0x40 457 __I uint32_t RFIFO_STATUS; // 0x44 458 } I2C_TypeDef; 459 460 #define I2C0_BASE 0x4008A000 461 #define I2C1_BASE 0x4008B000 462 #define I2C0 ((I2C_TypeDef *)I2C0_BASE) 463 #define I2C1 ((I2C_TypeDef *)I2C1_BASE) 464 465 #define I2C0_BUS_CLOCK_BIT 7 466 #define I2C1_BUS_CLOCK_BIT 8 467 #define I2C0_PERI_CLOCK_BIT 20 468 #define I2C1_PERI_CLOCK_BIT 21 469 470 #define I2C0_BUS_CLOCK_ENABLE (1 << I2C0_BUS_CLOCK_BIT) 471 #define I2C1_BUS_CLOCK_ENABLE (1 << I2C1_BUS_CLOCK_BIT) 472 #define I2C0_PERI_CLOCK_ENABLE (1 << I2C0_PERI_CLOCK_BIT) 473 #define I2C1_PERI_CLOCK_ENABLE (1 << I2C1_PERI_CLOCK_BIT) 474 475 #define I2C0_BUS_CLOCK_DISABLE (1 << I2C0_BUS_CLOCK_BIT) 476 #define I2C1_BUS_CLOCK_DISABLE (1 << I2C1_BUS_CLOCK_BIT) 477 #define I2C0_PERI_CLOCK_DISABLE (1 << I2C0_PERI_CLOCK_BIT) 478 #define I2C1_PERI_CLOCK_DISABLE (1 << I2C1_PERI_CLOCK_BIT) 479 480 #define I2C0_IRQ_BIT 14 481 #define I2C1_IRQ_BIT 15 482 483 #define I2C0_IRQ_ENABLE (1 << I2C0_IRQ_BIT) 484 #define I2C1_IRQ_ENABLE (1 << I2C1_IRQ_BIT) 485 486 #define I2C0_IRQ_DISABLE (1 << I2C0_IRQ_BIT) 487 #define I2C1_IRQ_DISABLE (1 << I2C1_IRQ_BIT) 488 /// set pad2:3 for i2c0 func 4 489 // #define I2C0_PINMUX_MASK0 0x0000FF00 490 // #define I2C0_PINMUX_VALUE0 0x00004400 491 /// set pad20:21 for i2c0 scl/sda func 1 492 // #define I2C0_PINMUX_MASK1 0x00FF0000 493 // #define I2C0_PINMUX_VALUE1 0x00110000 494 /// set pad 8:9 for i2c1 func 3 495 // #define I2C1_PINMUX_MASK0 0x000000FF 496 // #define I2C1_PINMUX_VALUE0 0x00000033 497 /// set pad22:23 for i2c1 scl/sda func 1 498 // #define I2C1_PINMUX_MASK1 0xFF000000 499 // #define I2C1_PINMUX_VALUE1 0x11000000 500 501 /* 502 DUET I2C END 503 */ 504 505 /* 506 DUET PWM BEGIN 507 */ 508 //////////////////// to do//////////////////////////// 509 /* 510 DUET PWM END 511 */ 512 513 /* 514 DUET RTC BEGIN 515 */ 516 typedef struct __RTC { 517 __IO uint32_t CTRL; 518 __IO uint32_t CNT_TICK; 519 __IO uint32_t CNT_DATE; 520 __I uint32_t DUMMY[3]; 521 __I uint32_t CURRENT_TICK; 522 __I uint32_t CURRENT_DATE; 523 } RTC_TypeDef; 524 525 #define RTC_REG_BASE 0x40000A20 526 #define RTC ((RTC_TypeDef *)(RTC_REG_BASE)) 527 528 #define COUNT_IN_SECOND 32768 529 530 #define RTC_IRQ_BIT 0 531 532 #define RTC_CNT_CYCLE_ENABLE (1 << 15) 533 #define RTC_ENABLE (1 << 14) 534 #define CLK32K_SEL (1 << 12) // A0V1 bug, sel ext XO no function, same as internal RC clk 535 #define RTC_INT_ENABLE (1 << 11) 536 #define SW_OVERRIDE_REG_POR (1 << 4) 537 538 #define RTC_TICK_CNT 32768 // 1s for asic 539 540 #define GET_RTC_CURRENT_DATE() (RTC->CURRENT_DATE) 541 542 #define RTC_INIT_YEAR 118 // 2018 543 #define RTC_INIT_MONTH 8 // month 9 544 #define RTC_INIT_DATE 12 545 #define RTC_INIT_HOUR 8 546 #define RTC_INIT_MINUTE 0 547 #define RTC_INIT_SECOND 0 548 #define RTC_INIT_WEEKDAY 0 // auto modify 549 550 #define RTC_REFRESH_DAY 255 // 255 max unit: day 551 #define RTC_REFRESH_HOUR 23 // 0 - 23 552 #define RTC_REFRESH_MINUTE 59 // 0 - 59 553 #define RTC_REFRESH_SECOND 59 // 0 - 59 554 555 #define RTC_MAX_DAY 256 556 #define SECOND_PER_DAY (24*3600) 557 558 #define DUET_IRQ_STS_REG_ADDR 0x40000AA0 559 560 // retention ram addr need to be planned 561 #define RTC_TIME_RETENTION_RAM_ADDR 0x40008000 562 #define RTC_FLAG_RETENTION_RAM_ADDR 0x40008008 563 564 #define RTC_BUS_CLK_BIT (0X01<<6) 565 #define SLEEP_IRQ_BIT (0X01<<1) 566 /* 567 DUET RTC END 568 */ 569 570 /* 571 RETENTION SRAM BEGIN 572 */ 573 struct DUET_RETENTION_SRAM { 574 __IO uint8_t RTC_DATE[16]; 575 __IO uint32_t BOOT_CFG; 576 __IO uint32_t BOOT_TYPE; 577 uint8_t RSVD1[40]; 578 }; 579 580 #define RETENTION_RAM_ADDR 0x40008000 581 #define RETENTION_SRAM ((struct DUET_RETENTION_SRAM *)(RETENTION_RAM_ADDR)) 582 #define DUET_RETENTION_SRAM_CUSTOM_SIZE 64 583 // #define RTC_TIME_RETENTION_RAM_ADDR RETENTION_RAM_ADDR 584 585 /* 586 RETENTION SRAM END 587 */ 588 589 /* 590 DUET TIMER BEGIN 591 */ 592 593 //////////// to do //////////// 594 /* 595 DUET TIMER END 596 */ 597 598 /* 599 DUET UART BEGIN 600 */ 601 602 /* DUET UART register block */ 603 typedef struct __UART { 604 __IO uint32_t DR ; /* 0x0 */ 605 __IO uint32_t RSC_ECR ; /* 0x4 */ 606 __I uint32_t RSV0[4] ; /* 0x8~0x14 */ 607 __I uint32_t FR ; /* 0x18 */ 608 __I uint32_t RSV1 ; /* 0x1C */ 609 __IO uint32_t ILPR ; /* 0x20 */ 610 __IO uint32_t IBRD ; /* 0x24 */ 611 __IO uint32_t FBRD ; /* 0x28 */ 612 __IO uint32_t LCR_H ; /* 0x2C */ 613 __IO uint32_t CR ; /* 0x30 */ 614 __IO uint32_t IFLS ; /* 0x34 */ 615 __IO uint32_t IMSC ; /* 0x38 */ 616 __I uint32_t RIS ; /* 0x3C */ 617 __I uint32_t MIS ; /* 0x40 */ 618 __O uint32_t ICR ; /* 0x44 */ 619 __IO uint32_t DMACR ; /* 0x48 */ 620 __I uint32_t RSV2[997] ; /* 0x04C~0xFDC */ 621 __I uint32_t ID[8] ; /* 0xFE0~0xFFC */ 622 } UART_TypeDef; 623 624 #define UART0_BASE (0x40080000+0x1000) 625 #define UART1_BASE (0x40080000+0x2000) 626 #define UART2_BASE (0x40080000+0x3000) 627 628 #define UART0 ((UART_TypeDef *)UART0_BASE) 629 #define UART1 ((UART_TypeDef *)UART1_BASE) 630 #define UART2 ((UART_TypeDef *)UART2_BASE) 631 632 #define UART0_BUS_CLK_EN (0X01<<1) 633 #define UART0_PERI_CLK_EN (0X01<<14) 634 #define UART1_BUS_CLK_EN (0X01<<2) 635 #define UART1_PERI_CLK_EN (0X01<<15) 636 #define UART2_BUS_CLK_EN (0X01<<3) 637 #define UART2_PERI_CLK_EN (0X01<<16) 638 639 #define UART0_IRQ_BIT (0X01<<8) 640 #define UART1_IRQ_BIT (0X01<<9) 641 #define UART2_IRQ_BIT (0X01<<10) 642 643 /* 644 DUET UART END 645 */ 646 647 /* 648 DUET WDG BEGIN 649 */ 650 struct DUET_WDOG { 651 __IO uint32_t LOAD; 652 __I uint32_t VALUE; 653 __IO uint32_t CONTROL; 654 __O uint32_t INTCLR; 655 __I uint32_t RIS; 656 __I uint32_t MIS; // 0x14 657 __I uint32_t DUMMY0[0x2FA]; 658 __IO uint32_t LOCK; // 0xC00 659 __I uint32_t DUMMY1[0xBF]; 660 __IO uint32_t ITCR; // 0xF00 661 __O uint32_t ITOP; // 0xF04 662 __I uint32_t DUMMY2[0x32]; 663 __I uint32_t PERIPHID4; // 0xFD0 664 __I uint32_t PERIPHID5; 665 __I uint32_t PERIPHID6; 666 __I uint32_t PERIPHID7; 667 __I uint32_t PERIPHID0; 668 __I uint32_t PERIPHID1; 669 __I uint32_t PERIPHID2; 670 __I uint32_t PERIPHID3; 671 __I uint32_t PCELLID0; 672 __I uint32_t PCELLID1; 673 __I uint32_t PCELLID2; 674 __I uint32_t PCELLID3; 675 }; 676 #define WDOG_BASE 0x40080000 677 #define WATCHDOG ((struct DUET_WDOG *)(WDOG_BASE)) 678 679 #define WDG_LOCK_TOKEN 0x1ACCE551 680 #define WDG_RESEN (1 << 1) 681 #define WDG_INTEN 1 682 #define WDG_BUS_CLK_BIT (0X01<<9) 683 #define WDG_IRQ_BIT (0X01<<2) 684 /* 685 DUET WDG END 686 */ 687 688 /* 689 DUET TIMER BEGIN 690 */ 691 struct DUET_TIMER { 692 __IO uint32_t LOAD; 693 __I uint32_t VALUE; 694 __IO uint32_t CONTROL; 695 __O uint32_t INTCLR; 696 __I uint32_t RIS; 697 __I uint32_t MIS; 698 __IO uint32_t BGLOAD; 699 }; 700 701 #define TIMER1_REG_BASE 0x40087000 702 #define TIMER2_REG_BASE 0x40087020 703 #define TIMER1 ((struct DUET_TIMER *)(TIMER1_REG_BASE)) 704 #define TIMER2 ((struct DUET_TIMER *)(TIMER2_REG_BASE)) 705 706 #define COUNTER_16BIT 0 707 #define COUNTER_32BIT (1 << 1) 708 #define TIMER_SIZE COUNTER_32BIT 709 710 #define CLOCK_DIV_1 0 711 #define CLOCK_DIV_16 (1 << 2) 712 #define CLOCK_DIV_256 (2 << 2) 713 #define TIMER_PRESCALE CLOCK_DIV_1 714 715 #define FREE_RUNNING_MODE 0 716 #define PERIODIC_MODE (1 << 6) 717 #define ONE_SHOT_MODE 1 718 719 #define INTERRUPT_EN (1 << 5) 720 #define INTERRUPT_DIS 0 721 722 #define TIMER_ENABLE (1 << 7) 723 #define TIMER_DISABLE 0 724 725 #define TIMER_BUS_CLK_BIT (0X01<<10) 726 #define TIMER_IRQ_BIT (0X01<<5) 727 /* 728 DUET TIMER END 729 */ 730 731 /* 732 DUET PWM BEGIN 733 */ 734 struct DUET_PWM { 735 __IO uint32_t PWMCFG; 736 __IO uint32_t PWMINVERTTRIG; 737 __IO uint32_t PWM01TRIG; 738 __IO uint32_t PWM23TRIG; 739 __IO uint32_t PWM45TRIG; 740 __IO uint32_t PWMINTEN1; 741 __IO uint32_t PWMINTEN2; 742 __I uint32_t PWMRIS1; 743 __I uint32_t PWMRIS2; 744 __IO uint32_t PWMRIC1; 745 746 __IO uint32_t PWMRIC2; 747 __I uint32_t PWMIS1; 748 __I uint32_t PWMIS2; 749 __IO uint32_t PWMCTL; 750 __IO uint32_t PWM01LOAD; 751 __IO uint32_t PWM23LOAD; 752 __IO uint32_t PWM45LOAD; 753 __I uint32_t PWM01COUNT; 754 __I uint32_t PWM23COUNT; 755 __I uint32_t PWM45COUNT; 756 757 __IO uint32_t PWM0CMP; 758 __IO uint32_t PWM1CMP; 759 __IO uint32_t PWM2CMP; 760 __IO uint32_t PWM3CMP; 761 __IO uint32_t PWM4CMP; 762 __IO uint32_t PWM5CMP; 763 __IO uint32_t PWM01DB; 764 __IO uint32_t PWM23DB; 765 __IO uint32_t PWM45DB; 766 __IO uint32_t CAPCTL; 767 768 __IO uint32_t CAPINTEN; 769 __I uint32_t CAPRIS; 770 __IO uint32_t CAPIC; 771 __I uint32_t CAPIS; 772 __I uint32_t CAP01T; 773 __I uint32_t CAP23T; 774 __I uint32_t CAP45T; 775 __IO uint32_t CAP01MATCH; 776 __IO uint32_t CAP23MATCH; 777 __IO uint32_t CAP45MATCH; 778 779 __IO uint32_t TIMINTEN; 780 __I uint32_t TIMRIS; 781 __IO uint32_t TIMIC; 782 __I uint32_t TIMIS; 783 __IO uint32_t TIM01LOAD; 784 __IO uint32_t TIM23LOAD; 785 __IO uint32_t TIM45LOAD; 786 __IO uint32_t TIM01COUNT; 787 __IO uint32_t TIM23COUNT; 788 __IO uint32_t TIM45COUNT; 789 }; 790 #define PWM_REG_BASE 0x40088000 791 #define PWM ((struct DUET_PWM *)(PWM_REG_BASE)) 792 793 #define COUNT_UP_MODE 0 794 #define COUNT_UP_DOWN_MODE 1 795 #define PWM_COUNT_MODE COUNT_UP_MODE 796 797 #define CNT_CLK_DIV_EN (0x00000001 << 27) 798 #define CNT_CLK_DIV_DIS 0 799 #define CLK_DIV_2 (0) 800 #define CLK_DIV_4 (0x00000001 << 24) 801 #define CLK_DIV_8 (0x00000002 << 24) 802 #define CLK_DIV_16 (0x00000003 << 24) 803 #define CLK_DIV_32 (0x00000004 << 24) 804 #define CLK_DIV_64 (0x00000005 << 24) 805 #define CLK_DIV_128 (0x00000006 << 24) 806 #define CLK_DIV_CFG CLK_DIV_8 807 808 #define PWM0_INVERT_EN (0x00000001 << 0) 809 #define PWM1_INVERT_EN (0x00000001 << 1) 810 #define PWM2_INVERT_EN (0x00000001 << 2) 811 #define PWM3_INVERT_EN (0x00000001 << 3) 812 #define PWM4_INVERT_EN (0x00000001 << 4) 813 #define PWM5_INVERT_EN (0x00000001 << 5) 814 #define PWM6_INVERT_EN (0x00000001 << 6) 815 #define PWM7_INVERT_EN (0x00000001 << 7) 816 #define PWMX_INVERT_EN 0 817 818 #define PWM_BUS_CLK_BIT (0X01<<11) 819 820 /* 821 DUET PWM END 822 */ 823 824 /* 825 DUET EFUDE BEGIN 826 */ 827 struct DUET_EFUSE { 828 __IO uint32_t CFG_TYPE; // 0x00 829 __IO uint32_t WR_TYPE; 830 __IO uint32_t START; 831 __IO uint32_t RD_CNT; 832 __IO uint32_t WR_CNT; // 0x10 833 __IO uint32_t DIV_CNT; 834 __IO uint32_t B_ADDR; 835 __IO uint32_t PGM_DATA; 836 __IO uint32_t RDBK_DATA; // 0x20 837 __I uint32_t RSVD; 838 __IO uint32_t INT_EN; 839 __IO uint32_t INT_CLR; 840 __IO uint32_t E_ENABLE; // 0x30 841 }; 842 843 #define EFUSE_CTRL_BASE 0x40005000 844 #define EFUSE ((struct DUET_EFUSE *)(EFUSE_CTRL_BASE)) 845 846 #define EFUSE_CTRL_BASE 0x40005000 847 #define EFUSE_REG_CFG_TYPE *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x000)) 848 #define EFUSE_REG_WR_TYPE *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x004)) 849 #define EFUSE_REG_START *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x008)) 850 #define EFUSE_REG_RD_CNT *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x00C)) 851 #define EFUSE_REG_WR_CNT *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x010)) 852 #define EFUSE_REG_DIV_CNT *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x014)) 853 #define EFUSE_REG_B_ADDR *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x018)) 854 #define EFUSE_REG_PGM_DATA *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x01C)) 855 #define EFUSE_REG_RDBK_DATA *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x020)) 856 // #define EFUSE_REG_DONE *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x024)) 857 #define EFUSE_REG_INT_EN *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x028)) 858 #define EFUSE_REG_INT_CLR *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x02C)) 859 #define EFUSE_REG_ENABLE *((volatile uint32_t *)(EFUSE_CTRL_BASE + 0x030)) 860 861 #define PSRAM_REG_BASE 0x4000A000 862 #define PSRAM_MCR (PSRAM_REG_BASE + 0x000) 863 #define PSRAM_IPCR (PSRAM_REG_BASE + 0x008) 864 #define PSRAM_FLSHCR (PSRAM_REG_BASE + 0x00C) 865 #define PSRAM_BUF0CR (PSRAM_REG_BASE + 0x010) 866 #define PSRAM_BUF1CR (PSRAM_REG_BASE + 0x014) 867 #define PSRAM_BUF2CR (PSRAM_REG_BASE + 0x018) 868 #define PSRAM_BUF3CR (PSRAM_REG_BASE + 0x01C) 869 #define PSRAM_BFGENCR (PSRAM_REG_BASE + 0x020) 870 #define PSRAM_SOCCR (PSRAM_REG_BASE + 0x024) 871 #define PSRAM_BUF0IND (PSRAM_REG_BASE + 0x030) 872 #define PSRAM_BUF1IND (PSRAM_REG_BASE + 0x034) 873 #define PSRAM_BUF2IND (PSRAM_REG_BASE + 0x038) 874 #define PSRAM_SFAR (PSRAM_REG_BASE + 0x100) 875 #define PSRAM_SMPR (PSRAM_REG_BASE + 0x108) 876 #define PSRAM_RBSR (PSRAM_REG_BASE + 0x10C) 877 #define PSRAM_RBCT (PSRAM_REG_BASE + 0x110) 878 #define PSRAM_TBSR (PSRAM_REG_BASE + 0x150) 879 #define PSRAM_TBDR (PSRAM_REG_BASE + 0x154) 880 #define PSRAM_TBCT (PSRAM_REG_BASE + 0x158) 881 #define PSRAM_SR (PSRAM_REG_BASE + 0x15C) 882 #define PSRAM_FR (PSRAM_REG_BASE + 0x160) 883 #define PSRAM_RSER (PSRAM_REG_BASE + 0x164) 884 #define PSRAM_SPNDST (PSRAM_REG_BASE + 0x168) 885 #define PSRAM_SPTRCLR (PSRAM_REG_BASE + 0x16C) 886 #define PSRAM_SFA1AD (PSRAM_REG_BASE + 0x180) 887 #define PSRAM_SFA2AD (PSRAM_REG_BASE + 0x184) 888 #define PSRAM_SFB1AD (PSRAM_REG_BASE + 0x188) 889 #define PSRAM_SFB2AD (PSRAM_REG_BASE + 0x18C) 890 #define PSRAM_DLPV (PSRAM_REG_BASE + 0x190) 891 #define PSRAM_RBDR0 (PSRAM_REG_BASE + 0x200) 892 #define PSRAM_RBDR1 (PSRAM_REG_BASE + 0x204) 893 #define PSRAM_RBDR2 (PSRAM_REG_BASE + 0x208) 894 #define PSRAM_LUTKEY (PSRAM_REG_BASE + 0x300) 895 #define PSRAM_LCKCR (PSRAM_REG_BASE + 0x304) 896 #define PSRAM_LUT0 (PSRAM_REG_BASE + 0x310) 897 #define PSRAM_LUT1 (PSRAM_REG_BASE + 0x314) 898 #define PSRAM_LUT2 (PSRAM_REG_BASE + 0x318) 899 #define PSRAM_LUT3 (PSRAM_REG_BASE + 0x31C) 900 901 /* 902 DUET EFUDE END 903 */ 904 905 /* 906 DUET LPUART BEGIN 907 */ 908 ////////////////////// to do ///////////////// 909 /* 910 DUET LPUART END 911 */ 912 #endif // _DUET_H_ 913