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Searched refs:RTC_CNTL_REG (Results 1 – 5 of 5) sorted by relevance

/device/soc/esp/esp32/components/esp_hw_support/port/esp32/
Drtc_init.c39 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); in rtc_init()
40 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10); in rtc_init()
76 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_FORCE_PU); in rtc_init()
77 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU); in rtc_init()
79 SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); in rtc_init()
81 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD); in rtc_init()
Drtc_sleep.c206 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); in rtc_sleep_init()
207 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); in rtc_sleep_init()
208 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); in rtc_sleep_init()
209 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); in rtc_sleep_init()
Drtc_clk.c365 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); in rtc_clk_bbpll_configure()
405 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); in rtc_clk_bbpll_configure()
473 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M); in rtc_clk_cpu_freq_to_xtal()
475 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); in rtc_clk_cpu_freq_to_xtal()
482 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); in rtc_clk_cpu_freq_to_8m()
538 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); in rtc_clk_cpu_freq_to_pll_mhz()
Drtc_clk_init.c70 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); in rtc_clk_init()
/device/soc/esp/esp32/components/soc/esp32/include/soc/
Drtc_cntl_reg.h1083 #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) macro