1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_RTC_H_ 16 #define _ROM_RTC_H_ 17 18 #include "ets_sys.h" 19 20 #include <stdbool.h> 21 #include <stdint.h> 22 23 #include "soc/soc.h" 24 #include "soc/rtc_cntl_reg.h" 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /** \defgroup rtc_apis, rtc registers and memory related apis 31 * @brief rtc apis 32 */ 33 34 /** @addtogroup rtc_apis 35 * @{ 36 */ 37 38 /************************************************************************************** 39 * Note: * 40 * Some Rtc memory and registers are used, in ROM or in internal library. * 41 * Please do not use reserved or used rtc memory or registers. * 42 * * 43 ************************************************************************************* 44 * RTC Memory & Store Register usage 45 ************************************************************************************* 46 * rtc memory addr type size usage 47 * 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry 48 * 0x3ff61000+SIZE_CP Slow 8192-SIZE_CP 49 * 50 * 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code 51 * 52 ************************************************************************************* 53 * RTC store registers usage 54 * RTC_CNTL_STORE0_REG Reserved 55 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value 56 * RTC_CNTL_STORE2_REG Boot time, low word 57 * RTC_CNTL_STORE3_REG Boot time, high word 58 * RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code. 59 * RTC_CNTL_STORE5_REG APB bus frequency 60 * RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY 61 * RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC 62 ************************************************************************************* 63 */ 64 65 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG 66 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG 67 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG 68 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG 69 #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG 70 #define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG 71 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG 72 #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG 73 74 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code. 75 76 typedef enum { 77 AWAKE = 0, //<CPU ON 78 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode. 79 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up 80 } SLEEP_MODE; 81 82 typedef enum { 83 NO_MEAN = 0, 84 POWERON_RESET = 1, /**<1, Vbat power on reset*/ 85 SW_RESET = 3, /**<3, Software reset digital core*/ 86 OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/ 87 DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/ 88 SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/ 89 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/ 90 TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/ 91 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/ 92 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/ 93 TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/ 94 SW_CPU_RESET = 12, /**<12, Software reset CPU*/ 95 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/ 96 EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/ 97 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/ 98 RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/ 99 } RESET_REASON; 100 101 typedef enum { 102 NO_SLEEP = 0, 103 EXT_EVENT0_TRIG = BIT0, 104 EXT_EVENT1_TRIG = BIT1, 105 GPIO_TRIG = BIT2, 106 TIMER_EXPIRE = BIT3, 107 SDIO_TRIG = BIT4, 108 MAC_TRIG = BIT5, 109 UART0_TRIG = BIT6, 110 UART1_TRIG = BIT7, 111 TOUCH_TRIG = BIT8, 112 SAR_TRIG = BIT9, 113 BT_TRIG = BIT10 114 } WAKEUP_REASON; 115 116 typedef enum { 117 DISEN_WAKEUP = NO_SLEEP, 118 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG, 119 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG, 120 GPIO_TRIG_EN = GPIO_TRIG, 121 TIMER_EXPIRE_EN = TIMER_EXPIRE, 122 SDIO_TRIG_EN = SDIO_TRIG, 123 MAC_TRIG_EN = MAC_TRIG, 124 UART0_TRIG_EN = UART0_TRIG, 125 UART1_TRIG_EN = UART1_TRIG, 126 TOUCH_TRIG_EN = TOUCH_TRIG, 127 SAR_TRIG_EN = SAR_TRIG, 128 BT_TRIG_EN = BT_TRIG 129 } WAKEUP_ENABLE; 130 131 typedef enum { 132 NO_INT = 0, 133 WAKEUP_INT = BIT0, 134 REJECT_INT = BIT1, 135 SDIO_IDLE_INT = BIT2, 136 RTC_WDT_INT = BIT3, 137 RTC_TIME_VALID_INT = BIT4 138 } RTC_INT_REASON; 139 140 typedef enum { 141 DISEN_INT = 0, 142 WAKEUP_INT_EN = WAKEUP_INT, 143 REJECT_INT_EN = REJECT_INT, 144 SDIO_IDLE_INT_EN = SDIO_IDLE_INT, 145 RTC_WDT_INT_EN = RTC_WDT_INT, 146 RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT 147 } RTC_INT_EN; 148 149 /** 150 * @brief Get the reset reason for CPU. 151 * 152 * @param int cpu_no : CPU no. 153 * 154 * @return RESET_REASON 155 */ 156 RESET_REASON rtc_get_reset_reason(int cpu_no); 157 158 /** 159 * @brief Get the wakeup cause for CPU. 160 * 161 * @param int cpu_no : CPU no. 162 * 163 * @return WAKEUP_REASON 164 */ 165 WAKEUP_REASON rtc_get_wakeup_cause(void); 166 167 /** 168 * @brief Get CRC for Fast RTC Memory. 169 * 170 * @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory. 171 * 172 * @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte. 173 * 174 * @return uint32_t : CRC32 result 175 */ 176 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len); 177 178 /** 179 * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7. 180 * 181 * @param None 182 * 183 * @return None 184 */ 185 void set_rtc_memory_crc(void); 186 187 /** 188 * @brief Software Reset digital core. 189 * 190 * It is not recommended to use this function in esp-idf, use 191 * esp_restart() instead. 192 * 193 * @param None 194 * 195 * @return None 196 */ 197 void __attribute__((noreturn)) software_reset(void); 198 199 /** 200 * @brief Software Reset digital core. 201 * 202 * It is not recommended to use this function in esp-idf, use 203 * esp_restart() instead. 204 * 205 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU. 206 * 207 * @return None 208 */ 209 void software_reset_cpu(int cpu_no); 210 211 /** 212 * @} 213 */ 214 215 #ifdef __cplusplus 216 } 217 #endif 218 219 #endif /* _ROM_RTC_H_ */ 220